Abstract: In laser annealing using a solid state laser, a focus position of a minor axial direction of a rectangular beam is easily corrected depending on positional variation of a laser irradiated portion of a semiconductor film. By using a minor-axis condenser lens 29 condensing incident light in a minor axial direction and a projection lens 30 projecting light, which comes from the minor-axis condenser lens 29, onto a surface of a semiconductor film 3, laser beam 1 is condensed on the surface of the semiconductor film 3 in the minor axial direction of a rectangular beam. The positional variation of a vertical direction of the semiconductor film 3 in a laser irradiated portion of the semiconductor film 3 is detected by a positional variation detector 31, and the minor-axis condenser lens 29 is moved in an optical axis direction based on a value of the detection.

Abstract: A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is formed on the SOI layer at a gradient of Ge concentration gradually decreasing toward the surface and then subjected to a heat treatment in an oxidizing atmosphere.

Abstract: The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed by a heat treatment at a relaxation temperature at which the material constituting the thin film deforms by elastic deformation is deposited on the thin film; c) the thin film and the relaxation layer are transferred onto a substrate; and d) a thermal budget is applied at least the relaxation temperature, so as to cause the plastic deformation of the relaxation layer and the at least partial relaxation of the thin film by elastic deformation, and thus to obtain the final heterostructure.

Abstract: A technique for forming nanostructures including a definition of a charge pattern on a substrate and introduction of charged molecular scale sized building blocks (MSSBBs) to a region proximate the charge pattern so that the MSSBBs adhere to the charge pattern to form the feature.

Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.

Abstract: An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a plurality areas defined laterally in the substrate through a bottom surface of the substrate; and a light source facing a top surface of the substrate, configured to irradiate a pulsed light at a pulse width of about 0.1 ms to about 100 ms on the entire top surface of the substrate.

Abstract: The invention relates to a device for depositing semiconductor layers, comprising a process chamber (1) arranged substantially rotationally symmetrically about a center (11), a susceptor (2), a process chamber ceiling (3), a gas inlet element (4) having gas inlet chambers (8, 9, 10) that are arranged vertically on top of each other, and a heater (27) arranged below the susceptor (2), wherein the topmost (8) of the gas inlet chambers is directly adjacent to the process chamber ceiling (3) and is connected to a feed line (14) for feeding a hydride together with a carrier gas into the process chamber (1), wherein the lowest (10) of the gas inlet chambers is directly adjacent to the susceptor (2) and is connected to a feed line (16) for feeding a hydride together with a carrier gas into the process chamber (1), wherein at least one center gas inlet chamber (9) arranged between the lowest (10) and the topmost (8) gas inlet chamber is connected to a feed line (15) for feeding an organometallic compound into the pro

Abstract: The invention relates to methods of fabricating a layer of at least partially relaxed material, such as for electronics, optoelectronics or photovoltaics. An exemplary method includes supplying a structure that includes a layer of strained material situated between a reflow layer and a stiffener layer. The method further includes applying a heat treatment that brings the reflow layer to a temperature equal to or greater than the glass transition temperature of the reflow layer, and the thickness of the stiffener layer is progressively reduced during heat treatment. The invention also relates to an exemplary method of fabricating semiconductor devices on a layer of at least partially relaxed material. Specifically, at least one active layer may be formed on the at least partially relaxed material layer. The active layer may include laser components, photovoltaic components and/or electroluminescent diodes.

Abstract: A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.

Abstract: Techniques for low temperature ion implantation are provided to improve throughput. Specifically, the pressure of the backside gas may temporarily, continually or continuously increase before the starting of the implant process, such that the wafer may be quickly cooled down from room temperature to be essentially equal to the prescribed implant temperature. Further, after the vacuum venting process, the wafer may wait an extra time in the load lock chamber before the wafer is moved out the ion implanter, in order to allow the wafer temperature to reach a higher temperature quickly for minimizing water condensation on the wafer surface. Furthermore, to accurately monitor the wafer temperature during a period of changing wafer temperature, a non-contact type temperature measuring device may be used to monitor wafer temperature in a real time manner with minimized condensation.

Abstract: A method of transferring a layer of a first material onto a second substrate of a second material includes, a step of forming a first embrittlement plane in a first substrate in first material, by a first ion and/or atom implantation through a first face of said substrate, a step of forming a second embrittlement plane in said first substrate, by a first ion and/or atom implantation through a second face of said substrate, in order to reduce a curvature of this first substrate, a step of assembling the first and second substrates, and a step of separating a layer from the first substrate at the level of the first embrittlement plane, without separation at the level of the second embrittlement plane.

Abstract: Provided is a method of manufacturing a crystalline semiconductor thin film formed on an amorphous or poly-crystalline substrate such as a glass substrate, a ceramic substrate, and a plastic substrate through induction heating using photo-charges. The method of manufacturing a crystalline semiconductor thin film includes a process of forming a low-concentration semiconductor layer on an inexpensive amorphous or poly-crystalline substrate such as a glass substrate, a ceramic substrate, and a plastic substrate and a process of crystallizing the low-concentration semiconductor layer through an induction heating manner using photo-charges. Accordingly, a low-concentration crystalline semiconductor thin film having characteristics better than those of general amorphous or poly-crystalline semiconductor thin film can be obtained by using simple processes at low production cost.

Abstract: A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.

Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.

Abstract: The present invention relates a method for forming a monocrystalline GeN layer (4) on a substrate (1) comprising at least a Ge surface (3). The method comprises, while heating the substrate (1) to a temperature between 550° C. and 940° C., exposing the substrate (1) to a nitrogen gas flow. The present invention furthermore provides a structure comprising a monocrystalline GeN layer (4) on a substrate (1). The monocrystalline GeN formed by the method according to embodiments of the invention allows passivation of surface states present at the Ge surface (3).

Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.

Abstract: Disclosed is a method of providing a poly-Si layer used in fabricating poly-Si TFT's or devices containing poly-Si layers. Particularly, a method utilizing at least one metal plate covering the amorphous silicon layer or the substrate, and applying RTA (Rapid Thermal Annealing) for light illuminating process, then the light converted into heat by the metal plate will further be conducted to the amorphous silicon layer to realize rapid thermal crystallization. Thus the poly-Si layer of the present invention is obtained.

Abstract: A method for fabricating a copper indium diselenide semiconductor film is provided using substrates having a copper and indium composite structure. The substrates are placed vertically in a furnace and a gas including a selenide species and a carrier gas are introduced. The temperature is increased from about 350° C. to about 450° C. to initiate formation of a copper indium diselenide film from the copper and indium composite on the substrates.

Abstract: A method for manufacturing a flash memory device is capable of controlling a phenomenon in which a length of the channel between a source and a drain is decreased due to undercut. The method includes forming a gate electrode comprising a floating gate, an ONO film and a control gate using a hard mask pattern over a semiconductor substrate, forming a spacer over the sidewall of the gate electrode, forming an low temperature oxide (LTO) film over the entire surface of the semiconductor substrate including the gate electrode and the spacer, etching the LTO film such that a top portion of the source/drain region and a top portion of the gate electrode are exposed, and removing the LTO film present over the sidewall of the gate electrode by wet-etching.

Abstract: A disclosed heating apparatus for heating a substrate on which a film is coated includes a process chamber having a gas supply opening for supplying a first gas to the process chamber and a gas evacuation opening for evacuating the first gas from the process chamber; a heating plate that is arranged in the process chamber and includes a heating element for heating the substrate; plural protrusions arranged on the heating plate so as to support the substrate; plural suction holes formed in the heating plate so as to attract by suction the substrate toward the heating plate; and a gas inlet adapted to supply a second gas to a gap between the heating plate and the substrate supported by the plural protrusions.

Abstract: A method of making II-VI core-shell semiconductor nanowires includes providing a support; depositing a layer including metal alloy nanoparticles on the support; and heating the support and growing II-VI core semiconductor nanowires where the metal alloy nanoparticles act as catalysts and selectively cause localized growth of the core nanowires. The method further includes modifying the growth conditions and shelling the core nanowires to form II-VI core-shell semiconductor nanowires.

Abstract: An object of the present invention is obtaining a semiconductor film with uniform characteristics by improving irradiation variations of the semiconductor film. The irradiation variations are generated due to scanning while irradiating with a linear laser beam of the pulse emission. At a laser crystallization step of irradiating a semiconductor film with a laser light, a continuous light emission excimer laser emission device is used as a laser light source. For example, in a method of fabricating an active matrix type liquid crystal display device, a continuous light emission excimer laser beam is irradiated to a semiconductor film, which is processed to be a linear shape, while scanning in a vertical direction to the linear direction. Therefore, more uniform crystallization can be performed because irradiation marks can be avoided by a conventional pulse laser.

Abstract: Provided is a silicon wafer including: a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer; and a bulk area formed between the first denuded zone and a backside of the silicon wafer, wherein the first denuded zone is formed with a depth ranging from approximately 20 um to approximately 80 um from the top surface, and wherein a concentration of oxygen in the bulk area is uniformly distributed within a variation of 10% over the bulk area.

Abstract: A strained Si—SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.

Abstract: Exemplary embodiments provide semiconductor devices with a high-quality semiconductor material on a lattice mismatched substrate and methods for their manufacturing using low temperature growth techniques followed by an insulator-capped annealing process. The semiconductor material can have high-quality with a sufficiently low threading dislocation (TD) density, and can be effectively used for integrated circuit applications such as an integration of optically-active materials (e.g., Group III-V materials) with silicon circuitry. In an exemplary embodiment, the high-quality semiconductor material can include one or more ultra-thin high-quality semiconductor epitaxial layers/films/materials having a desired thickness on the lattice mismatched substrate. Each ultra-thin high-quality semiconductor epitaxial layer can be formed by capping a low-temperature grown initial ultra-thin semiconductor material, annealing the capped initial ultra-thin semiconductor material, and removing the capping layer.

Abstract: The present invention relates to a method for growing a nitride semiconductor epitaxial layer, which comprises the steps of growing a second nitride semiconductor epitaxial layer on a first nitride semiconductor epitaxial layer at a first temperature, growing a third nitride semiconductor epitaxial layer on the second nitride semiconductor epitaxial layer at a second temperature, and releasing nitrogen from the second nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature, thereby, it is possible to lower the defect density of epitaxial layers and reduce warpage of a substrate.

Abstract: Processes for forming full graphene wafers on silicon or silicon-on-insulator substrates. The processes comprise formation of a metal carbide layer on the substrate and annealing of the metal carbide layer under high vacuum. For volatile metals, this annealing step results in volatilization of the metal species of the metal carbide layer and reformation of the carbon atoms into the desired graphene wafer. Alternatively, for non-volatile metals, the annealing step results in migration of the metal in the metal carbide layer to the top surface of the layer, thereby forming a metal rich top layer. The desired graphene layer is formed by the carbon atoms left at the interface with the metal rich top layer. The thickness of the graphene layer is controlled by the thickness of the metal carbide layer and by solid phase reactions.

Abstract: An object of an embodiment of the present invention to be disclosed is to prevent oxygen from being taken in a single crystal semiconductor layer in laser irradiation even when crystallinity of the single crystal semiconductor layer is repaired by irradiation with a laser beam; and to make substantially equal or reduce an oxygen concentration in the semiconductor layer after the laser irradiation comparing before the laser irradiation. A single crystal semiconductor layer which is provided over a base substrate by bonding is irradiated with a laser beam, whereby the crystallinity of the single crystal semiconductor layer is repaired. The laser irradiation is performed under a reducing atmosphere or an inert atmosphere.

Abstract: A nitride semiconductor free-standing substrate includes a diameter of not less than 40 mm, a thickness of not less than 100 ?m, a dislocation density of not more than 5×106/cm2, an impurity concentration of not more than 4×1019/cm3, and a nanoindentation hardness of not less than 19.0 GPa at a maximum load in a range of not less than 1 mN and not more than 50 mN.

Abstract: A method of providing a layer in a semiconductor device, wherein the layer includes Si1-x-yGexCy, and wherein the carbon in the layer is in a stable condition, includes preparing a silicon substrate; preparing a SiGeC precursor; forming a Si1-x-yGexCy layer on the silicon substrate from the precursor; forming a top silicon layer on the Si1-x-yGexCy layer; and completing the semiconductor device.

Abstract: A silicon carbide semiconductor device comprising a region of germanium and a region of crystalline or polycrystalline silicon carbide. The germanium region and the silicon carbide region are configured to form a germanium/silicon carbide heterojunction.

Abstract: On the side of a surface (the bonding surface side) of a single crystal Si substrate, a uniform ion implantation layer is formed at a prescribed depth (L) in the vicinity of the surface. The surface of the single crystal Si substrate and a surface of a transparent insulating substrate as bonding surfaces are brought into close contact with each other, and bonding is performed by heating the substrates in this state at a temperature of 350° C. or below. After this bonding process, an Si—Si bond in the ion implantation layer is broken by applying impact from the outside, and a single crystal silicon thin film is mechanically peeled along a crystal surface at a position equivalent to the prescribed depth (L) in the vicinity of the surface of the single crystal Si substrate.

Abstract: Processes for forming full graphene wafers on silicon or silicon-on-insulator substrates. The processes comprise formation of a metal carbide layer on the substrate and annealing of the metal carbide layer under high vacuum. For volatile metals, this annealing step results in volatilization of the metal species of the metal carbide layer and reformation of the carbon atoms into the desired graphene wafer. Alternatively, for non-volatile metals, the annealing step results in migration of the metal in the metal carbide layer to the top surface of the layer, thereby forming a metal rich top layer. The desired graphene layer is formed by the carbon atoms left at the interface with the metal rich top layer. The thickness of the graphene layer is controlled by the thickness of the metal carbide layer and by solid phase reactions.

Abstract: A semiconductor structure is formed of nitrides of group III metals having wurtzite crystal structure and grown in vapor phase on a (0001) oriented semiconductor substrate. The structure comprises a bottom cladding layer, a top cladding layer, and a diffusion region positioned between the cladding layers for diffusing light propagating within the semiconductor structure. The diffuse region has refractive index different from those of the cladding layers and non-flat surfaces for providing light diffusing interfaces between the diffusion region and the cladding layers. According to the invention, the diffusion region comprises a plurality of diffusion layers, compositions and thicknesses of said diffusion layers having been chosen to avoid formation of strain-induced dislocations in the diffusion region, and adjacent diffusion layers having different refractive indices in order to further enhance the diffusion efficiency.

Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.

Abstract: A zinc oxide (ZnO) film is fabricated. Metal-organic chemical vapor deposition (MOCVD) is used to obtain the film with few defects, high integrity and low cost through an easy procedure. The ZnO film above a silicon substrate has a matching crystal orientation to the substrate. Thus, the ZnO film is fit for ultraviolet light-emitting diodes (UV LED), solar cells and related laser devices.

Abstract: Among others, techniques are described for forming nanotubes. In one aspect, a method includes forming a base layer of a transition metal on a substrate. The method also includes heating the substrate with the base layer in a mixture of gases to grow nanotubes on the base layer.

Abstract: A method includes forming a release layer of a semiconductor device being fabricated, where the release layer has a trapezoidal shape. The method also includes forming a cantilever, which has a cantilever arm formed over the release layer. The method further includes removing at least part of the release layer from under the cantilever arm. The release layer could be formed using a photo-resist material. The photo-resist material can be patterned by exposing the photo-resist material using multiple exposures. A first exposure could expose a portion of the photo-resist material, where the exposed portion has substantially vertical sides. A second exposure could give the exposed portion of the photo-resist material slanted sides. A wet etch could be performed to remove the release layer from under the cantilever arm.

Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.

Abstract: A method for fabricating a silicon nano wire, a solar cell including the silicon nano wire and a method for fabricating the solar cell. The solar cell includes a substrate, a first++-type poly-Si layer formed on the substrate, a first-type silicon nano wire layer including a first-type silicon nano wire grown from the first++-type poly-Si layer, an intrinsic layer formed on the substrate having the first-type silicon nano wire layer, and a second-type doping layer formed on the intrinsic layer.

Abstract: A method for producing a semiconductor includes providing a p-doped semiconductor body having a first side and a second side; implanting protons into the semiconductor body via the first side to a target depth of the semiconductor body; bonding the first side of the semiconductor body to a carrier substrate; forming an n-doped zone in the semiconductor body by heating the semiconductor body such that a pn junction arises in the semiconductor body; and removing the second side of the semiconductor body at least as far as a space charge zone spanned at the pn junction.

Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

Abstract: The present invention provides a method of manufacturing a bonded wafer. The method comprises an oxidation step in which an oxide film is formed on at least one surface of a base wafer, a bonding step in which the base wafer on which the oxide film has been formed is bonded to a top wafer to form a bonded wafer, and a thinning step in which the top wafer included in the bonded wafer is thinned. The oxidation step comprises heating the base wafer to a heating temperature ranging from 800 to 1300° C. at a rate of temperature increase ranging from 1 to 300° C./second in an oxidizing atmosphere, and the bonding step is carried out so as to position the oxide film formed in the oxidation step at an interface of the top wafer and the base wafer.

Abstract: A process for manufacturing an integrated differential pressure sensor includes forming, in a monolithic body of semiconductor material having a first face and a second face, a cavity extending at a distance from the first face and delimiting therewith a flexible membrane, forming an access passage in fluid communication with the cavity, and forming, in the flexible membrane, at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and delimits, together with the second face, a portion of the monolithic body. In order to form the access passage, the monolithic body is etched so as to form an access trench extending through it.

Abstract: A method of subjecting a silicon wafer doped with boron to a heat treatment in an argon atmosphere, wherein the argon atmosphere is replaced with a hydrogen atmosphere or a mixed gas of an argon gas and a hydrogen gas in a proper fashion, to thereby uniformize a boron concentration in the thickness direction of the surface layer of the silicon wafer doped with boron.

Abstract: The GaN single-crystal substrate 11 in accordance with the present invention has a polished surface subjected to heat treatment for at least 10 minutes at a substrate temperature of at least 1020° C. in a mixed gas atmosphere containing at least an NH3 gas. As a consequence, an atomic rearrangement is effected in the surface of the substrate 11 in which a large number of minute defects are formed by polishing, so as to flatten the surface of the substrate 11. Therefore, the surface of an epitaxial layer 12 formed on the substrate 11 can be made flat.

Abstract: A method and apparatus for manufacturing a semiconductor device is disclosed, which is capable of realizing an extension of a cleaning cycle for a processing chamber, the method comprising preheating a substrate; placing the preheated substrate onto a substrate-supporting unit provided in a susceptor while the preheated substrate is maintained at a predetermined height from an upper surface of the susceptor provided in a processing chamber; and forming a thin film on the preheated substrate, wherein a temperature of the preheated substrate is higher than a processing temperature for forming the thin film in the processing chamber.

Abstract: A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor substrate to a supporting substrate, separating the single-crystal semiconductor substrate at the hydrogen-added layer by thermal annealing, performing thermal annealing again to stabilize the adhering interface, and selectively removing the porous silicon layer to give single-crystal silicon layer divided into islands.

Abstract: A method for growing a silicon single crystal having a hydrogen defect density of equal to or less than 0.003 pieces/cm2 using a Czochralski method, includes: a crystal growth step performed in an atmospheric gas containing a hydrogen-containing gas so as to allow hydrogen gas to have a partial pressure of equal to or higher than 40 Pa and equal to or lower than 400 Pa; and a cooling state control step of setting the amount of time in a hydrogen aggregation temperature range which is a range of equal to or lower than 850° C. and equal to or higher than 550° C. to be equal to or longer than 100 minutes and equal to or shorter than 480 minutes.

Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.