Using Same Conductivity-type Dopant Patents (Class 438/529)
  • Patent number: 8999824
    Abstract: A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n+ impurity layer on the whole back surface of n? semiconductor wafer. A resist mask on the back surface of the wafer covers a part corresponding to where n+ cathode layer will be formed. A second ion implanting process implants p-type impurity using the resist mask to form p+ impurity layer in the interior of the n+ impurity layer. Second ion implanting process is split into two or more times. The dose of p-type impurity in second ion implanting process is greater than that of n-type impurity in first ion implanting process. The resist mask is removed, and p+ the n+ impurity layers activated.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: April 7, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Seiji Noguchi, Hidenao Kuribayashi
  • Publication number: 20150072480
    Abstract: Among other things, one or more systems and techniques for defining one or more implant regions or for doping a semiconductor arrangement are provided. A first implant region is defined based upon a first implant mask overlaying a first active region of a semiconductor arrangement. A second implant region is defined based upon the first implant mask and a second implant mask overlaying a second active region of the semiconductor arrangement. A third implant region is defined based upon the second implant mask overlaying a third active region of the semiconductor arrangement. One or more doping processes are performed through the first implant mask and the second implant mask to dope the semiconductor arrangement. Because the first implant mask and the second implant mask overlap the second active region, doping area coverage is improved thus mitigating undesirable voltage threshold variations otherwise resulting from inadequate doping area coverage.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Juing-Yi Wu, Jyh-Kang Ting, Tsung-Chieh Tsai, Liang-Yao Lee
  • Patent number: 8975169
    Abstract: A method of manufacture of an optoelectronic device includes the steps of: providing or forming a body of crystalline silicon containing substitutional carbon atoms, and irradiating said body of crystalline silicon with protons (H+) to create radiative defect centers in a photoactive region of the device, wherein at least some of said defect centers are G-center complexes having the form Cs—SiI—Cs, where Cs is a substitutional carbon atom and S¾ is an interstitial silicon atom. An optoelectronic device (FIG. 3) manufactured using the method is described.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: March 10, 2015
    Assignee: The University of Surrey
    Inventors: Kevin Peter Homewood, Russell Mark Gwilliam
  • Publication number: 20140377942
    Abstract: A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n+ impurity layer on the whole back surface of n? semiconductor wafer. A resist mask on the back surface of the wafer covers a part corresponding to where n+ cathode layer will be formed. A second ion implanting process implants p-type impurity using the resist mask to form p+ impurity layer in the interior of the n+ impurity layer. Second ion implanting process is split into two or more times. The dose of p-type impurity in second ion implanting process is greater than that of n-type impurity in first ion implanting process. The resist mask is removed, and p+ the n+ impurity layers activated.
    Type: Application
    Filed: June 11, 2014
    Publication date: December 25, 2014
    Inventors: Seiji NOGUCHI, Hidenao KURIBAYASHI
  • Publication number: 20140353678
    Abstract: A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region.
    Type: Application
    Filed: August 2, 2012
    Publication date: December 4, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Kenji Hamada, Kohei Ebihara, Akihiko Furukawa, Yuji Murakami
  • Patent number: 8822315
    Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 2, 2014
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Patent number: 8786010
    Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: July 22, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Christopher L. Rexer, Jaegil Lee, Hamza Yilmaz, Chongman Yun
  • Publication number: 20140187026
    Abstract: A method of manufacture of an optoelectronic device includes the steps of: providing or forming a body of crystalline silicon containing substitutional carbon atoms, and irradiating said body of crystalline silicon with protons (H+) to create radiative defect centres in a photoactive region of the device, wherein at least some of said defect centres are G-centre complexes having the form Cs—SiI—Cs, where Cs is a substitutional carbon atom and S¾ is an interstitial silicon atom. An optoelectronic device (FIG. 3) manufactured using the method is described.
    Type: Application
    Filed: August 9, 2012
    Publication date: July 3, 2014
    Applicant: THE UNIVERSITY OF SURREY
    Inventors: Kevin Peter Homewood, Russell Mark Gwilliam
  • Publication number: 20140167205
    Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 19, 2014
    Applicant: PFC DEVICE HOLDINGS LIMITED
    Inventors: Paul Chung-Chen CHANG, Kuo-Liang CHAO, Mei-Ling CHEN, Lung-Ching KAO
  • Publication number: 20140162442
    Abstract: In one embodiment a method of forming low contact resistance in a substrate includes forming a silicide layer on the substrate, the silicide layer and substrate defining an interface therebetween in a source/drain region, and performing a hot implant of a dopant species into the silicide layer while the substrate is at a substrate temperature greater than 150° C., where the hot implant is effective to generate an activated dopant layer containing the dopant species, and the activated dopant layer extends from the interface into the source/drain region.
    Type: Application
    Filed: June 19, 2013
    Publication date: June 12, 2014
    Inventors: Fareen Adeni Khaja, Benjamin Colombeau
  • Patent number: 8716717
    Abstract: A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: May 6, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Naruhisa Miura, Yasuhiro Kagawa, Kenji Hamada, Yoshiyuki Nakaki
  • Patent number: 8703578
    Abstract: A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: April 22, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Jan Hoentschel, Shiang Yang Ong, Stefan Flachowsky, Thilo Scheiper
  • Patent number: 8563381
    Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: October 22, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8558643
    Abstract: The invention relates to a micromechanical device comprising a semiconductor element capable of deflecting or resonating and comprising at least two regions having different material properties and drive or sense means functionally coupled to said semiconductor element. According to the invention, at least one of said regions comprises one or more n-type doping agents, and the relative volumes, doping concentrations, doping agents and/or crystal orientations of the regions being configured so that the temperature sensitivities of the generalized stiffness are opposite in sign at least at one temperature for the regions, and the overall temperature drift of the generalized stiffness of the semiconductor element is 50 ppm or less on a temperature range of 100° C. The device can be a resonator. Also a method of designing the device is disclosed.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: October 15, 2013
    Assignee: Teknologian Tutkimuskeskus VTT
    Inventors: Mika Prunnila, Antti Jaakkola, Tuomas Pensala
  • Patent number: 8507373
    Abstract: A semiconductor device having a DRAM region and a logic region embedded together therein, including a first transistor formed in a DRAM region, and having a first source/drain region containing at least a first impurity, and a second transistor formed in a logic region, and having a second source/drain region containing at least a second impurity, wherein each of the first source/drain region and the second source/drain region has a silicide layer respectively formed in the surficial portion thereof, and the first source/drain region has a junction depth which is determined by an impurity and is deeper than the junction depth of the second source/drain region.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: August 13, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Shirai
  • Patent number: 8501570
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 6, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ziwei Fang, Jeff J. Xu, Ming-Jie Huang, Yimin Huang, Zhiqiang Wu, Min Cao
  • Patent number: 8486815
    Abstract: A method for fabricating a back-side illumination image sensor includes: implanting a first type of dopant into an epitaxial layer disposed over a first side of a substrate layer to form a first dopant layer in a first side of the epitaxial layer; adhering a carry layer over the first dopant layer for carrying the substrate layer; grinding a second side of the substrate layer for exposing a second side of the epitaxial layer; implanting the first type of dopant into the epitaxial layer from the second side of the epitaxial layer to form a second dopant layer in the second side of the epitaxial layer; forming at least one metal layer over the second dopant layer after forming the second dopant layer in the second side of the epitaxial layer; removing the carry layer; and forming a color filtering module over the first dopant layer.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: July 16, 2013
    Assignees: Himax Imaging, Inc., Himax Semiconductor, Inc.
    Inventors: Fang-Ming Huang, Tsung-Chieh Chang
  • Patent number: 8470677
    Abstract: Gate electrodes are formed in a high speed transistor forming region, a low leakage transistor forming region, and a medium voltage transistor forming region, respectively. Thereafter, a photoresist film covering the medium voltage transistor forming region is formed. Then, ions of an impurity are implanted into a semiconductor substrate while using the photoresist film and the gate electrodes as a mask, and p-type pocket regions, extension regions, and impurity regions are thereby formed. Subsequently, another photoresist film covering the high speed transistor forming region is formed. Then, ions of an impurity are implanted into the semiconductor substrate while using the other photoresist film and the gate electrodes as a mask, and impurity regions and extension regions are thereby formed.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: June 25, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Junichi Ariyoshi
  • Patent number: 8461032
    Abstract: A method of tailoring the dopant profile of a substrate by utilizing two different dopants, each having a different diffusivity is disclosed. The substrate may be, for example, a solar cell. By introducing two different dopants, such as by ion implantation, furnace diffusion, or paste, it is possible to create the desired dopant profile. In addition, the dopants may be introduced simultaneously, partially simultaneously, or sequentially. Dopant pairs preferably consist of one lighter species and one heavier species, where the lighter species has a greater diffusivity. For example, dopant pairs such as boron and gallium, boron and indium, phosphorus and arsenic, and phosphorus and antimony, can be utilized.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: June 11, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas Bateman, Atul Gupta, Christopher Hatem, Deepak Ramappa
  • Publication number: 20130140582
    Abstract: The present invention relates to a semiconductor device and a method for manufacturing the same. A RESURF layer (101) including a plurality of P-type implantation layers having a relatively low concentration of P-type impurity is formed adjacent to an active region (2). The RESURF layer (101) includes a first RESURF layer (11), a second RESURF layer (12), a third RESURF layer (13), a fourth RESURF layer (14), and a fifth RESURF layer (15) that are arranged sequentially from the P-type base (2) side so as to surround the P-type base (2). The second RESURF layer (12) is configured with small regions (11?) having an implantation amount equal to that of the first RESURF layer (11) and small regions (13?) having an implantation amount equal to that of the third RESURF layer (13) being alternately arranged in multiple.
    Type: Application
    Filed: April 15, 2011
    Publication date: June 6, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Naruhisa Miura, Yasuhiro Kagawa, Kenji Hamada, Yoshiyuki Nakaki
  • Patent number: 8431455
    Abstract: Disclosed herein is a method of forming a memory device. In one example, the method includes performing a first ion implantation process with dopant atoms of a first type to partially form extension implant regions for a pull-down transistor and to fully form extension implant regions for a pass gate transistor of the memory device and, after performing the first ion implantation process, forming a first masking layer that masks the pass gate transistor and exposes the pull-down transistor to further processing. The method concludes with the step of performing a second ion implantation process with dopant atoms of the first type to introduce additional dopant atoms into the extension implant regions for the pull-down transistor that were formed during the first ion implantation process while masking the pass gate transistor from the second ion implantation process with the first masking layer.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: April 30, 2013
    Assignee: Globalfoundries Inc.
    Inventors: Ralf van Bentum, Nihar-Ranjan Mohapatra
  • Patent number: 8399309
    Abstract: A manufacturing method is disclosed which ensures strength of a wafer and improves device performance. A thermal diffusion layer is formed from a front surface of a wafer. A tapered groove which reaches the thermal diffusion layer is formed from a back surface by anisotropic etching with alkaline solution. In-groove thermal diffusion layer is formed on side wall surfaces of the groove. A separation layer of a reverse blocking IGBT is configured of the thermal diffusion layer and the in-groove diffusion layer. The thermal diffusion layer is formed shallowly by forming the in-groove diffusion layer. It is possible to considerably reduce thermal diffusion time. By carrying out an ion implantation forming the in-groove diffusion layer and an ion implantation forming a collector layer separately, it is possible to select an optimum value for tradeoff between turn-on voltage and switching loss, while ensuring reverse blocking voltage of the reverse blocking IGBT.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: March 19, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masaaki Ogino, Hiroki Wakimoto, Masayuki Miyazaki
  • Patent number: 8343863
    Abstract: A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jee Hwan Kim, Stephen W. Bedell, Siegfried Maurer, Devendra K. Sadana
  • Patent number: 8328936
    Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 11, 2012
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Patent number: 8329568
    Abstract: In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a first conductivity type. A channel region is included within the active area. A gate region overlays the channel region, and the first source/drain region and the second source/drain region are embedded in the active area and spaced from each other by the channel region. The first source/drain region and the second source/drain region each include a second semiconductor material of a second conductivity type opposite of the first conductivity type. A well-tap region is embedded in the active area and spaced from the first source/drain region by the channel region and the second source/drain region. The well-tap region includes the second semiconductor material of the first conductivity type. The first source/drain region and the second source/drain region and the well-tap region are epitaxial deposits.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: December 11, 2012
    Assignee: Xilinx, Inc.
    Inventors: Jae-Gyung Ahn, Myongseob Kim, Ping-Chin Yeh, Zhiyuan Wu, John Cooksey
  • Patent number: 8309445
    Abstract: A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Brian L. Ji, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8298875
    Abstract: A method to fabricate a junction-less transistor comprising: forming at least two regions of semiconductor doping; first region with a relatively high level of dopant concentration and second region with at least 1/10 lower dopant concentration, and etching away a portion of said first region for the formation of the transistor gate.
    Type: Grant
    Filed: March 6, 2011
    Date of Patent: October 30, 2012
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Paul Lim
  • Patent number: 8227329
    Abstract: A method for manufacturing a semiconductor device includes steps of preparing a semiconductor substrate having a first conductive type; implanting a first impurity having the first conductive type in the semiconductor substrate to form a well region having a bottom portion; and implanting a second impurity having a second conductive type in the semiconductor substrate to form an impurity region having a top portion, the top of the impurity region being in contact with the bottom portion of the well region. Implantation of the second impurity includes a first step of implanting the second impurity and a second step of implanting the second impurity, wherein a first implantation area of the first step of implanting the second impurity being broader or narrower than a second implantation area of the second step of implanting the second impurity.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 24, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takuji Tanaka
  • Publication number: 20120181655
    Abstract: When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.
    Type: Application
    Filed: September 15, 2011
    Publication date: July 19, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Thilo Scheiper, Stefan Flachowsky
  • Patent number: 8211784
    Abstract: A semiconductor device has at least two main carbon-rich regions and two additional carbon-rich regions. The main carbon-rich regions are separately located in a substrate so that a channel region is located between them. The additional carbon-rich regions are respectively located underneath the main carbon-rich regions. The carbon concentrations is higher in the main carbon-rich regions and lower in the additional carbon-rich regions, and optionally, the absolute value of a gradient of the carbon concentration of the bottom portion of the main carbon-rich regions is higher than the absolute value of a gradient of the carbon concentration of the additional carbon-rich regions. Therefore, the leakage current induced by a lattice mismatch effect at the carbon-rich and the carbon-free interface can be minimized.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: July 3, 2012
    Assignee: Advanced Ion Beam Technology, Inc.
    Inventors: Jason Hong, Daniel Tang
  • Publication number: 20120135587
    Abstract: A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage.
    Type: Application
    Filed: January 25, 2012
    Publication date: May 31, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jee Hwan Kim, Stephen W. Bedell, Siegfried Maurer, Devendra K. Sadana
  • Patent number: 8187959
    Abstract: Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) making a first amorphous layer in a top layer of the semiconductor substrate by a suitable implant, the first amorphous layer having a first depth, c) implanting a first dopant into the semiconductor substrate to provide the first amorphous layer with a first doping profile, d) applying a first solid phase epitaxial regrowth action to partially regrow the first amorphous layer and form a second amorphous layer having a second depth that is less than the first depth and activate the first dopant, e) implanting a second dopant into the semiconductor substrate to provide the second amorphous layer with a second doping profile with a higher doping concentration than the first doping profile, f) applying a second solid phase epitaxial regrowth action to regrow the second amorphous layer and activate the second dopant.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: May 29, 2012
    Assignee: IMEC
    Inventors: Bartlomiej Jan Pawlak, Raymond James Duffy, Richard Lindsay
  • Patent number: 8178412
    Abstract: A plurality of memory cells each constituted of a memory cell transistor having a gate electrode in a laminated structure composed of a charge storage layer and a control gate layer and a select transistor having source/drain diffusion layers while one of the source/drain diffusion layers is shared by the memory cell transistor are arranged in and on a semiconductor substrate. The impurity concentration of the source/drain diffusion layer shared by the memory cell transistor and the select transistor in each of the plurality of memory cells is set lower than the impurity concentration of the other source/drain diffusion layers in each of the memory cells.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: May 15, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuaki Isobe
  • Patent number: 8105926
    Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: January 31, 2012
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Hiroyuki Ito, Bunji Mizuno
  • Publication number: 20120018846
    Abstract: A bipolar semiconductor component, in particular a diode, comprising an anode structure which controls its emitter efficiency in a manner dependent on the current density in such a way that the emitter efficiency is low at small current densities and sufficiently high at large current densities, and an optional cathode structure, which can inject additional holes during commutation, and production methods therefor.
    Type: Application
    Filed: September 30, 2010
    Publication date: January 26, 2012
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Roman Baburske, Josef Lutz, Ralf Siemieniec, Hans-Joachim Schulze
  • Patent number: 8084341
    Abstract: The present invention provides a method for manufacturing a semiconductor device which includes a step of forming one optional impurity region in a semiconductor substrate at a place apart from the surface thereof, and in the method described above, ion implantation is performed a plurality of times while the position of an end portion of a mask pattern used for ion implantation is changed.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: December 27, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takuji Tanaka
  • Publication number: 20110256698
    Abstract: An improved method of moving a mask to perform a pattern implant of a substrate is disclosed. The mask has a plurality of apertures, and is placed between the ion source and the substrate. After the substrate is exposed to the ion beam, the mask is indexed to a new position relative to the substrate and a subsequent implant step is performed. Through the selection of the aperture size and shape, the index distance and the number of implant steps, a variety of implant patterns may be created. In some embodiments, the implant pattern includes heavily doped horizontal stripes with lighter doped regions between the stripes. In some embodiments, the implant pattern includes a grid of heavily doped regions. In other embodiments, the implant pattern is suitable for use with a bus-bar structure.
    Type: Application
    Filed: October 18, 2010
    Publication date: October 20, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Benjamin B. Riordon, Nicholas P.T. Bateman, Charles T. Carlson
  • Patent number: 8003501
    Abstract: A method of doping p-type impurity ions in a dual poly gate, comprising: forming a polysilicon layer doped with n-type impurity ions on a substrate with a gate insulation layer being interposed between the polysilicon layer and the substrate; exposing a region of the polysilicon layer; implementing a first doping of p-type impurity ions into the exposed region of the polysilicon layer by ion implantation so with a projection range Rp to a predetermined depth of the polysilicon layer; and implementing a second doping of p-type impurity ions into the exposed region of the polysilicon layer doped with the p-type impurity ions by plasma doping with a sloped doping profile.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: August 23, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Bong Rouh, Seung Mi Lee
  • Publication number: 20110201187
    Abstract: A vertical IGBT includes a floating region of the first conductive type being formed within the body region of the second conductive type. A density of first conductive type impurities at a boundary of the floating region and the body region that is above the floating region is distributed to increase from an upper side to a lower side. A density of the first conductive type impurities at a boundary of the floating region and the body region that is under the floating region is distributed to decrease from an upper side to a lower side. A density of second conductive type impurities at a boundary of the floating region and the body region that is above the floating region is distributed to decrease from an upper side to a lower side. A density of the second conductive type impurities at a boundary of the floating region and the body region that is under the floating region is distributed to increase from an upper side to a lower side.
    Type: Application
    Filed: October 15, 2009
    Publication date: August 18, 2011
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tsuyoshi Nishiwaki, Jun Saito
  • Patent number: 7981747
    Abstract: A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 ?m or less, a p?type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p?type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masaki Shiraishi, Yoshito Nakazawa
  • Patent number: 7972947
    Abstract: In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: July 5, 2011
    Assignees: Infineon Technologies AG, IMEC VZW.
    Inventors: Luis-Felipe Giles, Thomas Hoffmann, Chris Stapelmann
  • Patent number: 7968401
    Abstract: A method of plasma immersion ion implantation of a workpiece having a photoresist mask on its top surface prevents photoresist failure from carbonization of the photoresist. The method includes performing successive ion implantation sub-steps, each of the ion implantation sub-steps having a time duration over which only a fractional top portion of the photoresist layer is damaged by ion implantation. After each one of the successive ion implantation sub-steps, the fractional top portion of the photoresist is removed while leaving the remaining portion of the photoresist layer in place by performing an ashing sub-step. The number of the successive ion implantation sub-steps is sufficient to reach a predetermined ion implantation dose in the workpiece.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: June 28, 2011
    Inventors: Martin A. Hilkene, Kartik Santhanam, Yen B. Ta, Peter I. Porshnev, Majeed A. Foad
  • Patent number: 7943459
    Abstract: A semiconductor device is provided with a conductor wire and a fuse wire formed in an insulating film over a semiconductor substrate, a first under-pad-wire insulating film formed above the insulating film, a second under-pad-wire insulating film formed on the first under-pad-wire insulating film, a pad wire formed in an area above the conductive wire, in the first and second under-pad-wire insulating films and an opening formed by leaving a part of the first under-pad-wire insulating film in an area above the fuse wire, in the first and second under-pad-wire insulating films, wherein the second under-pad-wire insulating film comprises an element different from that of the first under-pad-wire insulating film.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: May 17, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazutaka Akiyama, Takaya Matsushita
  • Patent number: 7939440
    Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: May 10, 2011
    Assignee: Spansion LLC
    Inventors: Shibly S. Ahmed, Jun Kang, Hsiao-Han Thio, Imran Khan, Dong-Hyuk Ju, Chuan Lin
  • Patent number: 7927954
    Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: April 19, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Wen-Han Hung, Tzyy-Ming Cheng, Meng-Yi Wu, Tsai-Fu Hsiao, Shu-Yen Chan
  • Patent number: 7867884
    Abstract: A wafer fabrication method includes a first step of forming a plurality of first channel regions in a first region on a surface of a water, a second step of forming a plurality of second channel regions having an impurity concentration different from an impurity concentration of the first channel regions, a third step of forming a plurality of third channel regions in a third region on the surface of the water, and a fourth step of forming a plurality of fourth channel regions having an impurity concentration different from an impurity concentration of the third channel regions in a fourth region, wherein the first region and the second region are divided by a first line segment on the wafer, and the third and fourth regions are divided by a second line segment intersecting with the first line segment on the wafer.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: January 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Kamimura, Kou Sasaki, Tomoharu Inoue
  • Patent number: 7868387
    Abstract: A high-voltage, low-leakage, bidirectional electrostatic discharge (ESD, or other electrical overstress) protection device includes a doped well disposed between the terminal regions and the substrate. The device includes an embedded diode for conducting current in one direction, and a transistor feedback circuit for conducting current in the other direction. Variations in the dimensions and doping of the doped well, as well as external passive reference via resistor connections, allow the circuit designer to flexibly adjust the operating characteristics of the device, such as trigger voltage and turn-on speed, to suit the required mixed-signal operating conditions.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: January 11, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Jean-Jacques Hajjar, Todd Thomas
  • Patent number: 7863147
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: January 4, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
  • Patent number: 7825016
    Abstract: In a method for fabricating a semiconductor element in a substrate, micro-cavities are formed in the substrate. Furthermore, doping atoms are implanted into the substrate, whereby crystal defects are produced in the substrate. The substrate is heated, so that at least some of the crystal defects are eliminated using the micro-cavities, and the semiconductor element is formed using the doping atoms.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventor: Luis-Felipe Giles
  • Patent number: 7825441
    Abstract: A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body that is doped with the same type of dopants as the gate. This is in contrast with conventional JFETs that have a body that is doped with the opposite conductivity type as the gate. The body may be electrically decoupled from the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate. The capability to form a thin hyperabrupt junction layer allows formation of a JFET in a semiconductor-on-insulator substrate.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ebenezer E. Eshun, Jeffrey B. Johnson, Richard A. Phelps, Robert M. Rassel, Michael J. Zierak