Including Multiple Implantation Steps Patents (Class 438/527)
  • Patent number: 10553701
    Abstract: A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xueming Dexter Tan, Kiok Boone Elgin Quek, Xinfu Liu
  • Patent number: 10211300
    Abstract: According to an embodiment of a method of forming a semiconductor device, a semiconductor layer including a first dopant species of a first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type is formed. The semiconductor layer is part of a semiconductor body having opposite first and second surfaces. Trenches are formed in the semiconductor layer at the first surface. The trenches are filled with a filling material including at least a semiconductor material. A thermal oxide is formed at one or both of the first and second surfaces, the thermal oxide having a thickness of at least 200 nm. Thermal processing of the semiconductor body causes diffusion of the first and second dopants species into the filling material.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 19, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Gabor Mezoesi, Hans Weber
  • Patent number: 10170337
    Abstract: A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher Collins, Mukta G. Farooq, Troy L. Graves-Abe, Brian J. Greene, Robert Hannon, Herbert L. Ho, Chandrasekharan Kothandaraman
  • Patent number: 10141408
    Abstract: A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a contact material layer on a two-dimensional crystal material layer; performing ion implantation; and performing thermal annealing.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: November 27, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Kunpeng Jia, Yajuan Su, Huilong Zhu, Chao Zhao
  • Patent number: 9780163
    Abstract: A structure having high, middle, and low impurity concentration regions disposed from a surface side of a substrate is more suitably manufactured. A method of manufacturing a semiconductor device includes: a first implantation of first conductivity type impurities into a first conductivity type semiconductor substrate from a surface; melting and solidifying a first semiconductor region between a depth and the surface, wherein the depth is deeper than a depth having a peak impurity concentration in an increased region where the impurity concentration was increased in the first implantation, and shallower than a deeper end of the increased region; a second implantation of the impurities from the surface into a region shallower than the depth; and melting and solidifying a region in which the impurity concentration was increased in the second implantation.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 3, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuki Horiuchi, Satoru Kameyama
  • Patent number: 9302904
    Abstract: A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: April 5, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsueh-I Huang, Ming-Tung Lee, Shuo-Lun Tu
  • Patent number: 9299566
    Abstract: A method for forming a germanium-based layer is provided. The method includes: providing a substrate having a Ge or GeSi surface layer; and implanting atoms, molecules, ions or plasmas containing an element Sn into the Ge surface layer to form a Ge-based GeSn layer, or implanting atoms, molecules, ions or plasmas containing an element Sn into the GeSi surface layer to form a Ge-based GeSnSi layer, or co-implanting atoms, molecules, ions or plasmas containing elements Sn and Si into the Ge surface layer to form a Ge-based GeSnSi layer.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 29, 2016
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Lei Xiao, Jing Wang, Mei Zhao, Renrong Liang, Jun Xu
  • Patent number: 9281328
    Abstract: According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate and element isolation portions formed to isolate the image-sensing elements, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy element isolation portions are arranged with a constant pitch in the boundary region between the image-sensing element region and the logic circuit region.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: March 8, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Ohno, Osamu Fujii, Masataka Shiratsuchi, Yoshinori Honguh
  • Patent number: 9263549
    Abstract: A method of forming a field effect transistor includes forming a punchthrough region having a first conductivity type in a substrate, forming an epitaxial layer having the first conductivity type on the substrate, patterning the epitaxial layer to form a fin that protrudes from the substrate, forming a dummy gate and gate sidewall spacers on the fin defining preliminary source and drain regions of the fin on opposite sides of the dummy gate, removing the preliminary source and drain regions of the fin, implanting second conductivity type dopant atoms into exposed portions of the substrate and the punchthrough region, and forming source and drain regions having the second conductivity type on opposite sides of the dummy gate and the gate sidewall spacers.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mark S. Rodder, Chris Bowen
  • Patent number: 9224603
    Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain. The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: December 29, 2015
    Assignee: Volterra Semiconductor LLC
    Inventors: Yang Lu, Budong You, Marco A. Zuniga, Hamza Yilmaz
  • Patent number: 9166191
    Abstract: A method of manufacturing a display device includes: preparing a carrier substrate by forming an adhesive layer on a hard glass substrate; forming a flexible substrate on the adhesive layer; forming a thin film transistor and an organic light emitting element on the flexible substrate and encapsulating the organic light emitting element; and separating the carrier substrate and the flexible substrate by irradiating laser light. The adhesive layer is formed on the carrier substrate in such a state that tensile stress is applied. The display device and the carrier substrate are also disclosed.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: October 20, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Young-Sik Yoon
  • Patent number: 9153505
    Abstract: A method for manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) implanting an impurity into a surface layer of an SiC substrate at a concentration of 1×1020 cm?3 or higher, (b) forming a graphite film on a surface of the SiC substrate after the step (a), (c) activating the impurity by annealing the SiC substrate after the step (b), (d) removing the graphite film after the step (c), (e) oxidizing the surface of the SiC substrate to form an oxide film after the step (d), (f) removing the oxide film, and (g) measuring resistance of the SiC substrate by a four-point probe method after the step (f).
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: October 6, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazuo Kobayashi
  • Patent number: 9040399
    Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
  • Publication number: 20150137060
    Abstract: Devices and methods for forming a device are disclosed. The device includes a substrate and a selector diode disposed over the substrate. The diode includes first and second terminals. The first terminal is disposed between the second terminal and the substrate. The diode includes a Schottky Barrier (SB) disposed at about an interface of the first and second terminals. The SB includes a tunable SB height defined by a SB region having segregated dopants. The device includes a memory element disposed over and coupled to the selector diode.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yuan SUN, Eng Huat TOH
  • Patent number: 9034741
    Abstract: A semiconductor device and method for manufacturing the same, wherein the method includes fabrication of field effect transistors (FET). The method includes growing a doped epitaxial halo region in a plurality of sigma-shaped source and drain recesses within a semiconductor substrate. An epitaxial stressor material is grown within the sigma-shaped source and drain recesses surrounded by the doped epitaxial halo forming source and drain regions with controlled current depletion towards the channel region to improve device performance. Selective growth of epitaxial regions allows for control of dopants profile and hence tailored and enhanced carrier mobility within the device.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Keith E. Fogel, Judson R. Holt, Balasubramanian Pranatharthiharan, Alexander Reznicek
  • Patent number: 9034743
    Abstract: A method of processing a workpiece is disclosed, where the ion chamber is first coated with the desired dopant species and another species. Following this conditioning process, a feedgas, which comprises fluorine and the desired dopant, is introduced to the chamber and ionized. Ions are then extracted from the chamber and accelerated toward the workpiece, where they are implanted without being first mass analyzed. The other species used during the conditioning process may be a Group 3, 4 or 5 element. The desired dopant species may be boron.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: May 19, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Peter F. Kurunczi, Bon-Woong Koo, John A. Frontiero, William T. Levay, Christopher J. Leavitt, Timothy J. Miller, Vikram M. Bhosle, John W. Graff, Nicholas P T Bateman
  • Patent number: 9034742
    Abstract: A method for fabricating a semiconductor device is provided. An ion implantation mask exposing a portion of a semiconductor substrate is formed on the semiconductor substrate. The implantation mask includes a second hardmask layer having a first thickness and a second hardmask layer having a second thickness. The first hardmask layer is disposed between the second hardmask layer and the semiconductor substrate. An ion implantation process is performed on the exposed portion of the semiconductor substrate using the implantation mask. The implantation mask is removed without forming an etch mask layer on the exposed portion of the semiconductor substrate.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: May 19, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Hun Choi, Chan-Sam Chang
  • Patent number: 9029250
    Abstract: A method for producing semiconductor regions including impurities includes forming a trench in a first surface of a semiconductor body. Impurity atoms are implanted into a bottom of the trench. The trench is extended deeper into the semiconductor body, thereby forming a deeper trench. Impurity atoms are implanted into a bottom of the deeper trench.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Hans-Joachim Schulze
  • Publication number: 20150123236
    Abstract: An embodiment of a diode includes a semiconductor substrate, a first contact region having a first conductivity type, a second contact region laterally spaced from the first contact region, and having a second conductivity type, an intermediate region disposed in the semiconductor substrate between the first and second contact regions, electrically connected with the first contact region, and having the first conductivity type, and a buried region disposed in the semiconductor substrate, having the second conductivity type, and electrically connected with the second contact region. The buried region extends laterally across the first contact region and the intermediate region to establish first and second junctions, respectively. The first junction has a lower breakdown voltage than the second junction.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9023706
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: May 5, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 9012313
    Abstract: A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Alexandru Romanescu
  • Patent number: 9012984
    Abstract: A transistor device includes a drift layer having a first conductivity type, a body layer on the drift layer, the body layer having a second conductivity type opposite the first conductivity type, and a source region on the body layer, the source region having the first conductivity type. The device further includes a trench extending through the source region and the body layer and into the drift layer, a channel layer on the inner sidewall of the trench, the channel layer having the second conductivity type and having an inner sidewall opposite an inner sidewall of the trench, a gate insulator on the inner sidewall of the channel layer, and a gate contact on the gate insulator.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 21, 2015
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant Agarwal, John Palmour
  • Patent number: 9012285
    Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 21, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Akihiro Usujima, Shigeo Satoh
  • Patent number: 9006041
    Abstract: A method for manufacturing a bipolar punch-through semiconductor device is disclosed, which includes providing a wafer having a first and a second side, wherein on the first side a high-doped layer of the first conductivity type having constant high doping concentration is arranged; epitaxially growing a low-doped layer of the first conductivity type on the first side; performing a diffusion step by which a diffused inter-space region is created at the inter-space of the layers; creating at least one layer of the second conductivity type on the first side; and reducing the wafer thickness within the high-doped layer on the second side so that a buffer layer is created, which can include the inter-space region and the remaining part of the high-doped layer, wherein the doping profile of the buffer layer decreases steadily from the doping concentration of the high-doped region to the doping concentration of the drift layer.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 14, 2015
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Arnost Kopta, Thomas Clausen, Maxi Andenna
  • Publication number: 20150099351
    Abstract: A method for fabricating a semiconductor device is provided. An ion implantation mask exposing a portion of a semiconductor substrate is formed on the semiconductor substrate. The implantation mask includes a second hardmask layer having a first thickness and a second hardmask layer having a second thickness. The first hardmask layer is disposed between the second hardmask layer and the semiconductor substrate. An ion implantation process is performed on the exposed portion of the semiconductor substrate using the implantation mask. The implantation mask is removed without forming an etch mask layer on the exposed portion of the semiconductor substrate.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk-Hun Choi, Chan-Sam Chang
  • Patent number: 8999824
    Abstract: A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n+ impurity layer on the whole back surface of n? semiconductor wafer. A resist mask on the back surface of the wafer covers a part corresponding to where n+ cathode layer will be formed. A second ion implanting process implants p-type impurity using the resist mask to form p+ impurity layer in the interior of the n+ impurity layer. Second ion implanting process is split into two or more times. The dose of p-type impurity in second ion implanting process is greater than that of n-type impurity in first ion implanting process. The resist mask is removed, and p+ the n+ impurity layers activated.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: April 7, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Seiji Noguchi, Hidenao Kuribayashi
  • Patent number: 8999795
    Abstract: An asymmetrical field effect transistor (FET) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical FET device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8999861
    Abstract: A method for fabricating a semiconductor structure so as to have reduced junction leakage is disclosed. The method includes providing substitutional boron in a semiconductor substrate. The method includes preparing the substrate using a pre-amorphization implant and a carbon implant followed by a recrystallization step and a separate defect repair/activation step. Boron is introduced to the pre-amorphized region preferably by ion implantation.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 7, 2015
    Assignee: SuVolta, Inc.
    Inventors: Lance Scudder, Pushkar Ranade, Charles Stager, Lucian Shifren, Dalong Zhao, U.C. Sridharan, Michael Duane
  • Patent number: 8993424
    Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Dhanyakumar Mahaveer Sathaiya, Wei-Hao Wu, Ken-Ichi Goto, Tzer-Min Shen, Zhiqiang Wu
  • Patent number: 8993425
    Abstract: An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ying Zhang
  • Patent number: 8981337
    Abstract: The various technologies presented herein relate to a three dimensional manufacturing technique for application with semiconductor technologies. A membrane layer can be formed over a cavity. An opening can be formed in the membrane such that the membrane can act as a mask layer to the underlying wall surfaces and bottom surface of the cavity. A beam to facilitate an operation comprising any of implantation, etching or deposition can be directed through the opening onto the underlying surface, with the opening acting as a mask to control the area of the underlying surfaces on which any of implantation occurs, material is removed, and/or material is deposited. The membrane can be removed, a new membrane placed over the cavity and a new opening formed to facilitate another implantation, etching, or deposition operation. By changing the direction of the beam different wall/bottom surfaces can be utilized to form a plurality of structures.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: March 17, 2015
    Assignee: Sandia Corporation
    Inventors: David Bruce Burckel, Paul S. Davids, Paul J. Resnick, Bruce L. Draper
  • Publication number: 20150061089
    Abstract: A vertical semiconductor device has a semiconductor body with a first surface and a second surface substantially parallel to the first surface. A first metallization is arranged on the first surface. A second metallization is arranged on the second surface. In a sectional plane perpendicular to the first surface, the semiconductor body includes an n-doped first semiconductor region in ohmic contact with the second metallization, a plurality of p-doped second semiconductor regions in ohmic contact with the first metallization, and a plurality of p-doped embedded semiconductor regions. The p-doped second semiconductor regions substantially extend to the first surface, are spaced apart from one another and form respective first pn-junctions with the first semiconductor region.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Inventors: Ralf Siemieniec, Jens Peter Konrath
  • Patent number: 8956937
    Abstract: The present invention discloses to a method of depositing the metal barrier layer comprising silicon dioxide. It is applied in the transistor device comprising a silicon substrate, a gate and a gate side wall. The method comprises the following steps: ions are implanted into the silicon substrate to form an active region in the said silicon substrate; a first dense silicon dioxide film is deposited; a second normal silicon dioxide film is deposited; the said transistor device is high temperature annealed. The present invention ensures that the implanted ion is not separated out of the substrate during the annealing. And it prevents the warping and fragment of the silicon surface.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: February 17, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: GuoFang Xuan, Fei Luo
  • Patent number: 8951896
    Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Jeffrey E. Hanrahan, Mark D. Jaffe, Alvin J. Joseph, Dale W. Martin, Gerd Pfeiffer, James A. Slinkman
  • Patent number: 8951857
    Abstract: The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate. Other methods for fabricating a semiconductor device improve distribution of transistor parameters across a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile, across the substrate.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: February 10, 2015
    Assignee: Sk hynix Inc.
    Inventors: Young-Sun Sohn, Seung-Woo Jin, Min-Yong Lee, Kyoung-Bong Rouh
  • Patent number: 8946067
    Abstract: A method of preparing a thin material layer from a semiconductor substrate is presented. The method entails forming a stress-generating epitaxial layer on a base substrate to form a stressed region, and achieving separation along the stressed region to produce a first part and a second part. The stress-generating epitaxial layer may be boron-doped or a Si(1-x)—Gex material. The separation may be achieved with spalling or etching.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 3, 2015
    Inventor: Bing Hu
  • Patent number: 8937005
    Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 20, 2015
    Assignee: SuVolta, Inc.
    Inventors: Lance S. Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
  • Publication number: 20140377941
    Abstract: When forming a p+ area and n+ area on the same surface of an n? semiconductor wafer, a first ion implantation forms the p+ area on the entire rear surface of the n? semiconductor wafer. Next, a resist mask selectively covering the rear surface of the n? semiconductor wafer is formed. With this resist mask as the mask, an n-type impurity is injected into the rear surface of the n? semiconductor wafer through a second ion implantation to form the n+ area on a portion deeper from the rear surface of the n? semiconductor wafer than the p+ type area. Thereafter, the n? semiconductor wafer is exposed to an oxygen (O2) gas atmosphere with fluorine (F) gas added to remove the resist mask and a silicon part between the rear surface of the n? semiconductor wafer in an FWD area not covered by the resist mask and the n+ area.
    Type: Application
    Filed: May 9, 2014
    Publication date: December 25, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Toshihito KAMEI, Seiji NOGUCHI
  • Patent number: 8912082
    Abstract: Methods to form complementary implant regions in a workpiece are disclosed. A mask may be aligned with respect to implanted or doped regions on the workpiece. The mask also may be aligned with respect to surface modifications on the workpiece, such as deposits or etched regions. A masking material also may be deposited on the implanted regions using the mask. The workpiece may be a solar cell.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: December 16, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, William T. Weaver, Paul Sullivan, John W. Graff
  • Patent number: 8900982
    Abstract: Herein, an improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be achieved using a mask for processing the substrate. The mask may be incorporated into a substrate processing system such as, for example, an ion implantation system. The mask may comprise one or more first apertures disposed in a first row; and one or more second apertures disposed in a second row, each row extending along a width direction of the mask, wherein the one or more first apertures and the one or more second apertures are non-uniform.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: December 2, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin M. Daniels, Russell L. Low, Nicholas P. T. Bateman, Benjamin B. Riordon
  • Patent number: 8895418
    Abstract: One embodiment describes a method of manufacturing a semiconductor device. Here, impurities are implanted into a semiconductor body via a first side of the semiconductor body. Thereafter, a drift zone layer on the first side of the semiconductor body is formed. The following is an ablation of the semiconductor body from a second side of the semiconductor body and up to pn junction defined by impurities.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: November 25, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Peter Irsigler, Thomas Neidhart, Guenter Schagerl, Hans-Joachim Schulze
  • Patent number: 8889529
    Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8884395
    Abstract: A Schottky diode includes a deep well formed in a substrate, an isolation layer formed in the substrate, a first conductive type guard ring formed in the deep well along an outer sidewall of the isolation layer and located at a left side of the isolation layer, a second conductive type well formed in the deep well along the outer sidewall of the isolation layer and located at a right side of the isolation layer, an anode electrode formed over the substrate and coupled to the deep well and the guard ring, and a cathode electrode formed over the substrate and coupled to the well. A part of the guard ring overlaps the isolation layer.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: November 11, 2014
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jin-Yeong Son
  • Patent number: 8878301
    Abstract: A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yuichi Hirano
  • Patent number: 8877619
    Abstract: Structures and processes are provided that can be used for effectively integrating different transistor designs across a process platform. In particular, a bifurcated process is provided in which dopants and other processes for forming some transistor types may be performed prior to STI or other device isolation processes, and other devices may be formed thereafter. Thus, doping and other steps and their sequence with respect to the STI process can be selected to be STI-first or STI-last, depending on the device type to be manufactured, the range of device types that are manufactured on the same wafer or die, or the range of device types that are planned to be manufactured using the same or similar mask sets.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 4, 2014
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Lance Scudder, Dalong Zhao, Teymur Bakhisher, Sameer Pradhan
  • Patent number: 8877596
    Abstract: a method comprises forming a hardmask over one or more gate structures. The method further comprises forming a photoresist over the hardmask. The method further comprises forming an opening in the photoresist over at least one of the gate structures. The method further comprises stripping the hardmask that is exposed in the opening and which is over the at least one of the gate structures. The method further comprises removing the photoresist. The method further comprises providing a halo implant on a side of the at least one of the gate structures.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Darshana N. Bhagat, Thomas J. Dunbar, Yen Li Lim, Jed H. Rankin, Eva A. Shah
  • Publication number: 20140312461
    Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 23, 2014
    Applicants: International Business Machines Corporation, Commissariat A L'Energie Atomique Et Aux Energies Alternatives, STMicroelectronics, Inc.
    Inventors: Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec, Qing Liu, Maud Vinet
  • Patent number: 8865557
    Abstract: In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: October 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8846461
    Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Hsin Lin, Weng Chang, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Ming-Hua Yu
  • Patent number: RE45944
    Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Tang-Xuang Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang