Abstract: This invention offers a manufacturing method which does not cause a reduction in thickness of a silicon substrate or a carbon contamination in forming a transistor having an LDD stricture and silicide layers formed by a salicide technology. After a gate electrode is formed on the silicon substrate through a gate insulation film, an insulation film made of the same material as the gate insulation film is formed on the gate electrode. A first insulation film made of a material different from the material of the gate insulation film and the insulation film on the gate electrode and a second insulation film made of the same material as the material of the gate insulation film and the insulation film on the gate electrode are formed over the silicon substrate. Spacers made of the second insulation film are formed by dry-etching. Then the LDD structure and openings for forming the silicide layers are formed using wet-etching.

Abstract: A method of manufacturing an EEPROM device is disclosed. An example method forms a screen oxide film on a semiconductor substrate, forms a first ion implantation mask defining a gate insulating film forming region on the screen oxide film, and performs a first ion implantation on the semiconductor substrate and the first ion implantation mask. The example method also performs a first annealing of the semiconductor substrate, removes the screen oxide film and the first ion implantation mask, and forms a gate oxide film on the semiconductor substrate. In addition, the example method forms a second ion implantation mask defining a gate insulating film forming region on the gate oxide film, performs a second ion implantation on the semiconductor substrate and the second ion implantation mask, performs a second annealing for the semiconductor substrate, removes the second ion implantation mask; and forms a tunnel oxide film on the gate oxide film.

Abstract: A method for fabricating a dual-gate semiconductor device is disclosed.

Abstract: Termination of a high voltage device is achieved by a plurality of discrete deposits of charge that are deposited in varying volumes and/or spacing laterally along a termination region. The manner in which the volumes and/or spacing varies also varies between different layers of a multiple layer device. In a preferred embodiment, the variations are such that the field strength is substantially constant along any horizontal or vertical cross section of the termination region.

Abstract: A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a high breakdown voltage and to provide a method of manufacturing the semiconductor device. The vertical MOSFET according to the invention includes an alternating-conductivity-type drain drift layer on an n+-type drain layer as a substrate. The alternating-conductivity-type drain drift layer is formed of n-type drift current path regions and p-type partition regions alternately arranged laterally with each other. The n-type drift current path regions and p-type partition regions extend in perpendicular to n+-type drain layer. Each p-type partition region is formed by vertically connecting p-type buried diffusion unit regions Up. The n-type drift current path regions are residual regions, left after connecting p-type buried diffusion unit regions Up, with the conductivity type thereof unchanged.

Abstract: A new process integration method is described to form heavily doped p+ source and drain regions in a CMOS device. After defining the p- and n-well regions on a semiconductor substrate, gate silicon dioxide is deposited and nitrided in a nitrogen-containing atmosphere. Poly-silicon is then deposited and the two NMOS and PMOS gates are formed. For the p+ doping of the poly-silicon gate and S/D regions around the PMOS gate, B+ ions are then implanted. Cap dielectric layer comprising silicon dioxide is then deposited, followed by dopant activation with high temperature rapid thermal annealing. The cap dielectric layer is then used as resist protective film; it is removed from those areas of the chip that would require formation of electrical contacts. Silicide electrical contacts are then formed in these areas.

Abstract: A semiconductor device includes a gate electrode formed on a semiconductor region via a gate insulative film and an extension high concentration diffusion layer of a first conductivity type formed in the semiconductor region beside the gate electrode. A dislocation loop defect layer is formed in a region of the semiconductor region beside the gate electrode and at a position shallower than an implantation projected range of the extension high concentration diffusion layer.

Abstract: In one embodiment, a plurality of gate structures including gate electrodes and insulating layers covering the gate electrodes are formed on a semiconductor substrate. Impurity ions at a low dose for forming a source/drain region are implanted into the semiconductor substrate, using the gate structures as a mask. First insulating spacers are formed on the sidewalls of the gate structures and second insulating spacers are formed on the first insulating spacers. Thereafter, impurity ions at a high dose are implanted into the semiconductor substrate, using the first and second insulating spacers as a mask. Then, the second insulating spacers are removed. Therefore, contact resistance and characteristics of the transistors can be improved by adjusting an effective channel length and contact areas.

Abstract: In a method of fabricating an LDMOS semiconductor device, a combined layer including a gate oxide film and a first nitride film is formed on a substrate within a first region. A mask body is formed on the combined layer within a second region that is inside of the first region. Then, first impurities are introduced into the substrate outside of the second region using the mask body as a mask. Next, second impurities are introduced into the substrate outside of the first region using the mask body and the combined layer as a mask. Finally, the introduced first and second impurities are diffused by a heat treatment so as to form a source/drain region and a well region.

Abstract: P wells (11, 12) having different impurity profiles are adjacently formed in a surface (50S) of a semiconductor substrate (50). A P-type layer (20) having lower resistivity than the P wells (11, 12) is formed in the surface (50S) across the P wells (11, 12), so that the P wells (11, 12) are electrically connected with each other through the P-type layer (20). Contacts (31, 32) fill in contact holes (70H1, 70H2) formed in an interlayer isolation film (70) respectively in contact with the P-type layer (20). The contacts (31, 32) are connected to a wire (40). The wire (70) is connected to a prescribed potential, thereby fixing the P wells (11, 12) to prescribed potentials through the contacts (31, 32) and the P-type layer (20). Thus, the potentials of the wells can be stably fixed and the layout area of elements for fixing the aforementioned potentials can be reduced.

Abstract: A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.

Abstract: The present invention relates to a method for forming an isolation film for semiconductor devices.

Abstract: Fabricating a semiconductor structure includes providing a semiconductor substrate, forming a silicide layer over the substrate, and removing a portion of the silicide layer by chemical mechanical polishing. The fabrication of the structure can also include forming a dielectric layer after forming the silicide layer, and removing a portion of the dielectric layer by chemical mechanical polishing before removing the portion of the silicide layer.

Abstract: A lateral doped channel. A first doping material is implanted substantially vertically into a region adjacent to a gate structure. A diffusion process diffuses the first doping material into a channel region beneath the gate structure. A second doping material is implanted substantially vertically into the region adjacent to a gate structure. The second implantation forms source/drain regions and may terminate the channel region. The channel region thus comprises a laterally non-uniform doping profile which beneficially mitigates the short channel effect and is highly advantageous as compensation for manufacturing process variations in channel length.

Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

Abstract: A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.

Abstract: When an opening diameter of a top end of a substantially column-shaped contact hole is S1, an opening diameter of a top end of a substantially column-shaped contact hole is T1, and a thickness of a silicon insulating layer is h, then contact holes are formed so as to satisfy the following conditional expression 1. T1/h<tan &thgr;1<S1/h (expression 1). With this formation method, a manufacturing method of a semiconductor device can be provided which does not need covering processing using a photolithography technique when impurity regions of different conductivity types are formed using contact holes.

Abstract: A method of forming a stable junction on a microelectronic structure on a semiconductor wafer having a silicon surface layer on a substrate includes the following steps: implanting dopant ions into the surface layer; cleaning and oxidizing the surface layer, and twice annealing the wafer to recover a damaged silicon crystal structure of the surface layer resulting from the low energy ion implantation. The first annealing process uses a temperature range of 800° C. to 1200° C. for a duration from about a fraction of a second to less than about 1000 seconds, with a ramp-up rate of about 50° C./second to about 1000° C./second. The second annealing process uses a temperature range of 400° C. to 650° C. for a time period of from about 1 second to about 10 hours, and more preferably, from about 60 seconds to about 1 hour. Both annealing processes include cooling processes.

Abstract: High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the drain side of the analog transistors (144, 146) to provide a flat channel doping profile on the drain side. Second pocket regions (200) may be formed in the analog transistors. The flat channel doping profile provides high early voltage and higher gain.

Abstract: A method of manufacturing a low-leakage, high-performance device. A substrate having a gate electrode thereon is provided. A lightly doped, high-energy implantation is conducted to form a lightly doped source/drain terminal in the substrate. An offset spacer is formed on each sidewall of the gate electrode. A heavily doped implantation is conducted to form a heavily doped source/drain terminal in the substrate. The heavily doped source/drain terminal has a depth smaller than the lightly doped source/drain terminal. A protective spacer structure is formed on each sidewall of the gate electrode. A deep-penetration source/drain implantation is carried out to form a deep source/drain terminal in the substrate.

Abstract: A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages in a common substrate. The method includes: (a) introducing an impurity of a second conductivity type in a specified region of a semiconductor substrate of a first conductivity type to form a first impurity layer and a second impurity layer; (b) further introducing an impurity of the second conductivity type in a region of the second impurity layer to form a third impurity layer; and (c) conducting a heat treatment to diffuse impurities of the first impurity layer and the third impurity layer to form a first well of the second conductivity type and a second well of the second conductivity type having an impurity concentration higher than the first well.

Abstract: A gate oxide film and a first layer of a multi-layered gate electrode are stacked on a substrate and by a gate prefabrication technique, an oxide layer of an element isolation region is formed in a self-alignment manner using the first layer of the gate electrode as a mask, impurities for a transistor channel control are doped by ion implantation via the first layer of the gate electrode and the gate oxide film, and the doped impurities are activated by a heating step, whereby an impurity profile at the transistor channel portion is precisely formed.

Abstract: A process for activating a doped region (80) or amorphized doped region (34) in a semiconductor substrate (10). The process includes the steps of doping a region of the semiconductor substrate, wherein the region is crystalline or previously amorphized. The next step is forming a conformal layer (40) atop the upper surface (11) of the substrate. The next step is performing at least one of front-side and backside irradiation of the substrate to activate the doped region. The activation may be achieved by heating the doped region to just below the melting point of the doped region, or by melting the doped region but not the crystalline substrate. An alternative process includes the additional step of forming the doped region (amorphized or unamorphized) within or adjacent a deep dopant region (60) and providing sufficient heat to the deep dopant region through at least one of front-side and backside irradiation so that the doped region is activated through explosive recrystallization.

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

Abstract: The present invention discloses an electro-optical device support on a substrate. The electro-optical device includes a sacrificial layer disposed on the substrate having a chamber-wall region surrounding and defining an optical chamber. The electro-optical device further includes a membrane layer disposed on top of the sacrificial layer having a chamber-removal opening surrounding and defining an electric tunable membrane for transmitting an optical signal therethrough. The electrically tunable membrane disposed on top of the optical chamber surrounded by the chamber wall regions. The chamber-wall region is doped with ion-dopants for maintaining the chamber-wall region for removal-resistance under a chamber-forming process performed through the chamber-removal opening. In a preferred embodiment, the chamber-wall region is a doped silicon dioxide region with carbon or nitrogen. In another preferred embodiment, the chamber-wall region is a nitrogen ion-doped SiNxOy region.

Abstract: A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.

Abstract: A gate electrode is formed in a partial area of the surface of a semiconductor substrate. Impurities of a first conductive type are implanted into the semiconductor substrate in areas on both sides of the gate electrode, by using the gate electrode as a mask. The implanted impurities are activated by applying a laser beam to the surface of the semiconductor substrate. Impurities to be used for threshold voltage control are implanted into the surface layer of the semiconductor substrate under the gate electrode, after the laser beam is applied. The impurities for threshold voltage control are activated by heating the semiconductor substrate. A semiconductor device is provided having a low parasitic resistance of source/drain regions and a desired threshold voltage hard to be lowered.

Abstract: An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

Abstract: A zener diode is formed in a bipolar or BiCMOS fabrication process by modifying the existing masks that are used in the bipolar or BiCMOS fabrication process, thereby eliminating the need for a separate doping step. In addition, the reverse breakdown voltage of the zener diode is set to a desired value within a range of values by modifying the area of a new opening in one of existing masks.

Abstract: A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well regio

Abstract: A method of forming a metal gate integrated with a salicide process on the source and drain regions. A gate dielectric layer and polysilicon/silicon dioxide/silicon nitride dummy gate layers are formed over a substrate structure and patterned to form dummy structures, comprising at least one dummy gate structure. Lightly doped source and drain regions, sidewall spacers, and source and drain regions are formed adjacent to the dummy gate structure. A silicide layer is formed on the source and drain regions by depositing titanium/titanium nitride, performing a rapid thermal anneal, selectively removing unreacted titanium/titanium nitride using NH4OH, and performing a second rapid thermal anneal. A blanket dielectric layer is formed over the dummy structures. The blanket dielectric layer, the spacers and the silicon nitride layer of the dummy structures are planarized using a chemical mechanical polishing process. The silicon nitride layer and the silicon dioxide layer of the dummy structures are removed.

Abstract: A method of fabricating lightly doped drains (LDD) of different resistance values starts by providing a semiconductor wafer, the semiconductor wafer having a first active area and a second active area positioned on the substrate. Secondly, a first gate and a second gate are formed on the first active area and the second active area, respectively. A first ion implantation process is then performed to implant dopants of a first electric type on a surface of portions of the substrate within the second active area, followed by performing a second ion implantation process to implant dopants of a second electric type on a surface of portions of the substrate within the first active area and second active area. Finally, the dopants of each electric type are activated to form a first LDD and a second LDD adjacent to the first gate and the second gate, respectively, the first LDD and the second LDD being of different resistance values.

Abstract: A method of fabricating a MOS transistor having shallow source/drain junction regions is provided. A diffusion source layer is formed on a semiconductor substrate on which gate patterns are formed. Same type or different type of impurities are implanted into the diffusion source layer several times in different directions. As a result, dislocation does not occur and the impurity concentration of the diffusion source layer can be nonuniformly controlled so that damage to the crystal structure of the semiconductor substrate does not occur. Also, the impurities nonuniformly contained in the diffusion source layer are diffused into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD regions and highly doped source/drain regions by a self-alignment method.

Abstract: A method of forming a graded junction in silicon includes implanting a first impurity specie into a silicon substrate, annealing the silicon to drive the implanted first specie deeper into the silicon, implanting a second impurity specie into the silicon substrate, and annealing the silicon to drive the second specie deeper into the silicon. Both first and second species, which can be the same or different species, have low silicon diffusion coefficient(s), such as Arsenic or Antimony. At least some of the implanted first specie is driven further into the silicon than any of the implanted second specie. The first specie has a lower dosage and greater implant energy to help form a graded junction, and the second specie has a greater dosage and lower implant energy for creating a high impurity concentration at the surface of the substrate.

Abstract: In a method of manufacturing a solid-state image pickup device having a virtual gate structure, in a process of forming a profile of a sensor portion, when ion implantation to form a p+ type layer at a substrate surface side is carried out while the ion implantation direction is tilted with respect to the substrate surface, the ion implantation is divisively carried out at plural times and from multiple ion implantation directions so that the total dose amount is matched, whereby impurities can be implanted into any area of the sensor portion and thus no impurities-unformed area occurs.

Abstract: A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy VSS connection implant such that the intrinsic source defect density is reduced and the VSs resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the VSS regions are implanted with a high energy, high dosage dopant ions.

Abstract: A nonvolatile semiconductor memory device featuring a reducing operating voltage while maintaining a good disturbance characteristic and high speed in a write operation, including a gate insulating film and gate electrode stacked on a channel forming region of a semiconductor provided on the surface of a substrate and planarly dispersed charge storing means such as carrier traps in a nitride film or near the interface with the top insulating film, provided in the gate insulating film, the gate insulating film including an FN tunnel film having a dielectric constant larger than that of a silicon oxide film and exhibiting an FN electroconductivity, whereby the thickness of the gate insulating film, converted to that of a silicon oxide film, can be reduced and the voltage can be reduced.

Abstract: A method for fabricating a low temperature polysilicon thin film transistor incorporating a channel passivation step is described. The method achieves dopant ion activation in a polysilicon gate by using laser irradiation, however, with an additional insulating material layer such as SiOx or SixNy overlying and protecting the channel portion of the polysilicon gate. Any possible contamination by residual photoresist material after a photoresist removal step on the channel portion of the polysilicon gate can thus be avoided. Furthermore, deficiencies such as dopant ions out-diffusion and lateral diffusion can be avoided. The leakage current of the thin film transistors formed by the present invention method is significantly reduced when compared to those formed by a conventional method.

Abstract: The present invention provides a semiconductor device production method that eliminates the risk of the occurrence of residual resist in the production process, and as a result, allows the electrical characteristics and reliability of the device to be improved. In this semiconductor device production method comprising steps of: subsequently laminating a first resist layer and a second resist layer having desired patterns on a semiconductor substrate, forming a first conductive region on the semiconductor substrate by injecting a first ion into the semiconductor substrate using the first and second resist layers as masks, removing the second resist layer, forming a second conductive region on the semiconductor substrate by injecting a second ion into the semiconductor substrate using the remaining first resist layer as a mask, and removing the first resist layer.

Abstract: This invention prevents an end portion of the LOCOS region having a large number of defects of an MOS sensor from depletion and thereby reduces the leak current that occurs in the defects in the end portion of the LOCOS region. An n-type layer region is formed in a surface area of a p-type substrate for constituting a photodiode with the p-type layer. A LOCOS region is formed on a p+-type layer in a surface area of the silicon substrate as device separation region by oxidizing part of the silicon substrate. The n-type layer region and the LOCOS region are separated from each other by a predetermined distance. A contact region is formed and separated from the n-type layer region by a distance equal to the size of the gate electrode of the read-out transistor of the MOS sensor. A wiring layer is connected to the contact region. Then, a planarizing layer is formed to cover the n-type layer region, the LOCOS region, the gate electrode and the wiring layer.

Abstract: A high voltage MOSFET device (100) has an nwell region (113) with a p-top layer (108) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.

Abstract: A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. A second epitaxial layer is formed on the first epitaxial layer and the implant process repeated to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A MOS transistor includes a substrate, an insulation layer, a gate and a dielectric layer. The substrate includes a drain and a source separately positioned on the surface of the substrate. The insulation layer is positioned on the surface of the substrate between the drain and the source. The gate includes a conducting layer positioned on the insulation layer having a bottom side, a top side, a left side and a right side, and a metallic silicide layer positioned on the top side of the conducting layer wherein the width of the metallic silicide layer is greater than that of the bottom side of the conducting layer. The dielectric layer covers the drain, the source and the metallic silicide layer. The transistor includes at least one empty side slot positioned between the dielectric layer and the left side or right side of the conducting layer below the metallic silicide layer.

Abstract: A method for suppressing silicidation retardation effects caused by high dopant concentrations, in particular high Arsenic concentrations, at the surface of a semiconductor substrate. The method includes implanting a preamorphization substance into the substrate to define the boundary of the source/drain, then implanting the dopant at high energy to establish a dopant concentration peak that is distanced from the surface of the substrate. The dopant is activated by rapid thermal annealing, with the relatively deep dopant concentration peak facilitating subsequent improved formation of silicide on the surface of the substrate.

Abstract: A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.

Abstract: After a first insulating film is formed only on the top surface or at least on the entire surface of a polysilicon gate electrode, first impurity ions are implanted into a semiconductor substrate from above the entire substrate to provide lightly doped source and drain regions. Then, after vertical layers are formed at the sides of the gate electrode and a second insulating film is formed at least on the top surface of the gate electrode, second impurity ions are implanted from above the entire semiconductor substrate to provide heavily doped source and drain regions.

Abstract: A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.

Abstract: A method for fabricating a wiring which runs at least piecewise in a substrate. At least one conductive connection runs in the semiconductor substrate and at least one conductive connection runs on the semiconductor substrate being provided. The semiconductor component enables applications in which high security against external manipulations is important.

Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: A method of forming a triple N well is described. A first pattern mask layer is formed on a substrate. A first ion implantation step is performed to form an annular longitudinal deep N well in the substrate. A second ion implantation step is performed to form an annular longitudinal shallow N well in the substrate. The annular longitudinal shallow N well lies above the annular longitudinal deep N well. The first mask layer is removed. A second patterned mask layer is formed on the substrate. A third ion implantation step is performed to form a transversal deep N well surrounded by the annular longitudinal deep N well. The transversal deep N well is connected with the annular longitudinal deep N well. Thus a triple N well is formed. A fourth ion implantation step is performed to form a cell well surrounded by the annular longitudinal deep N well. The cell well lies above the transversal deep N well. The second mask layer is removed.