Glassy Source Or Doped Oxide Patents (Class 438/563)
  • Patent number: 10593090
    Abstract: A method is described comprising: applying a random pattern to specified regions of an object; tracking the movement of the random pattern during a motion capture session; and generating motion data representing the movement of the object using the tracked movement of the random pattern.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 17, 2020
    Assignee: Rearden Mova, LLC
    Inventors: Timothy Cotter, Stephen G. Perlman, John Speck, Roger van der Laan, Kenneth A. Pearce, Greg LaSalle
  • Patent number: 9799522
    Abstract: The present application provides effective and efficient structures and methods for the formation of solar cell base and emitter regions and passivation layers using laser processing. Laser absorbent passivation materials are formed on a solar cell substrate and patterned using laser ablation to form base and emitter regions. Laser damage to the solar cell substrate is removed using an etch.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 24, 2017
    Assignee: OB REALTY, LLC
    Inventors: Pawan Kapur, Anand Deshpande, Sean M. Seutter, Heather Deshazer, Virendra V. Rana, Solene Coutant, Swaroop Kommera, Mehrdad M. Moslehi
  • Patent number: 9412830
    Abstract: A semiconductor device includes a first semiconductor layer made of a nitride semiconductor and formed on a substrate, a second semiconductor layer made of a material including InAlN and formed on the first semiconductor layer, an insulator layer formed by an oxidized surface part of the second semiconductor layer, a gate electrode formed on the insulator layer, and a source electrode and a drain electrode respectively formed on the first or second semiconductor layer.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: August 9, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Shirou Ozaki
  • Patent number: 9346989
    Abstract: A diffusing agent composition of an aspect of the invention contains: a condensation product (A) made from a starting material that is an alkoxysilane represented by the following general formula (1): [Chemical Formula 1] R1mSi(OR2)4-m ??(1) where R1 and R2 are an organic group, a plurality of R1s and R2s included in condensation product are identical or different, and m is 0, 1 or 2, the condensation product including an alkoxysilane where m=0 also including at least one alkoxysilane where m is 1 or 2; an impurity diffusion component (C); and an organic solvent (D).
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: May 24, 2016
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Toshiro Morita, Takashi Kamizono
  • Patent number: 9166079
    Abstract: Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: October 20, 2015
    Assignee: SunPower Corporation
    Inventor: Jane Manning
  • Publication number: 20150099352
    Abstract: A composition for forming an n-type diffusion layer includes a glass powder containing P2O5, SiO2 and CaO and a dispersion medium. An n-type diffusion layer and a photovoltaic cell element having an n-type diffusion layer are produced by applying the composition for forming an n-type diffusion layer on a semiconductor substrate and by subjecting the substrate to a thermal diffusion treatment.
    Type: Application
    Filed: July 17, 2012
    Publication date: April 9, 2015
    Inventors: Yoichi Machii, Masato Yoshida, Takeshi Nojiri, Mitsunori Iwamuro, Akihiro Orita, Shuichiro Adachi, Tetsuya Saito
  • Publication number: 20150017754
    Abstract: The invention provides composition for forming an n-type diffusion layer, the composition comprising a compound containing a donor element, a dispersing medium, and an organic filler; a method for producing a semiconductor substrate having an n-type diffusion layer; and a method for producing a photovoltaic cell element.
    Type: Application
    Filed: January 10, 2013
    Publication date: January 15, 2015
    Inventors: Tetsuya Sato, Masato Yoshida, Takeshi Nojiri, Toranosuke Ashizawa, Yasushi Kurata, Yoichi Machii, Mitsunori Iwamuro, Akihiro Orita, Mari Shimizu
  • Patent number: 8912083
    Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: December 16, 2014
    Assignee: NanoGram Corporation
    Inventors: Guojun Liu, Uma Srinivasan, Shivkumar Chiruvolu
  • Publication number: 20140361407
    Abstract: A method for forming a boron doped region within a silicon material substrate, and the resulting silicon material substrate that includes the boron doped region, each use a boron doped aluminum oxide material layer as a boron dopant source layer. The method provides the boron doped region with a sheet resistance in a range from about 15 to about 300 ohms per square. The method is also applicable, in general, to forming an n doped region, a p doped region or an n and p co-doped region within a silicon material substrate.
    Type: Application
    Filed: June 5, 2013
    Publication date: December 11, 2014
    Applicants: SCHMID Group, University of Central Florida Research Foundation Inc.
    Inventors: Kristopher O. Davis, Winston V. Schoenfeld, Kaiyun Jiang, Dirk Habermann
  • Patent number: 8835264
    Abstract: A substrate having thereon an epitaxial layer is provided. A hard mask having an opening is formed on the epitaxial layer. A sidewall spacer is formed within the opening. A first trench is etched into the epitaxial layer through the opening. A dopant source layer is formed on the surface of the first trench. The dopants are driven into the epitaxial layer to form a doped region within the first trench. The doped region includes a first region adjacent to the surface of the first trench and a second region farther from the surface. The entire dopant source layer and the spacer are removed. A sacrificial layer is then filled into the first trench. The sacrificial layer and the epitaxial layer within the first region are etched away to form a second trench.
    Type: Grant
    Filed: May 26, 2013
    Date of Patent: September 16, 2014
    Assignee: Anpec Electronics Corporation
    Inventor: Yung-Fa Lin
  • Patent number: 8796125
    Abstract: A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: August 5, 2014
    Assignee: Kovio, Inc.
    Inventors: Joerg Rockenberger, James Montague Cleeves, Arvind Kamath
  • Patent number: 8778787
    Abstract: Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: July 15, 2014
    Assignee: SunPower Corporation
    Inventor: Jane Manning
  • Publication number: 20140162445
    Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.
    Type: Application
    Filed: February 14, 2014
    Publication date: June 12, 2014
    Applicant: NanoGram Corporation
    Inventors: Guojun Liu, Uma Srinivasan, Shivkumar Chiruvolu
  • Patent number: 8728922
    Abstract: A method for producing monocrystalline n-silicon solar cells having a rear-side passivated p+ emitter and rear-side, spatially separate heavily doped n++-base regions near the surface, as well as an interdigitated rear-side contact finger structure, which is in conductive connection with the p+-emitter regions and the n++-base regions. An aluminum thin layer or an aluminum-containing thin layer is first deposited on the rear side of the n-silicon wafer, and the thin layer is subsequently structured so that openings are obtained in the region of the future base contacts. In a further process step, the aluminum is then diffused into the n-silicon wafer in order to form a structured emitter layer.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: May 20, 2014
    Assignee: SolarWorld Industries-Thueringen GmbH
    Inventors: Hans-Joachim Krokoszinski, Jan Lossen
  • Patent number: 8722545
    Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: May 13, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Hong-Gap Chua, Yee-Chung Chan, Mei-Yu Muk
  • Patent number: 8669169
    Abstract: Methods for selectively diffusing dopants into a substrate wafer are provided. A liquid precursor is doped with dopants. The liquid precursor is selected from a group comprising monomers, polymers, and oligomers of silicon and hydrogen. The doped liquid precursor is deposited on a surface of the substrate wafer to create a doped film. The doped film is heated on the substrate wafer for diffusing the dopants from the doped film into the substrate wafer at different diffusion rates to create a heavily diffused region and a lightly diffused region in the substrate wafer. The method disclosed herein further comprises selective curing of the doped film on the surface of the substrate wafer. The selectively cured doped film acts as a diffusion source for selectively diffusing the dopants into the substrate wafer.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: March 11, 2014
    Assignee: Piquant Research LLC
    Inventor: Daniel Inns
  • Patent number: 8653665
    Abstract: There is provided a film forming method for forming a film on a target object having thereon an insulating layer 1 that is made of a low-k film and having a recess 2 whose bottom surface is exposed to a metallic layer 3. The film forming method includes forming a first-metal-containing film containing a first metal such as ruthenium (Ru); and after forming the first-metal-containing film, forming a second-metal-containing film containing a second metal such as a manganese (Mn) having a barrier property against a filling metal to be filled in the recess.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: February 18, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Hidenori Miyoshi
  • Patent number: 8513104
    Abstract: A method of forming a floating junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front surface and a rear surface. The method also includes depositing a set of masking particles on the rear surface in a set of patterns; and heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a particle masking layer. The method further includes exposing the substrate to a phosphorous deposition ambient at a second temperature and for a second time period, wherein a front surface PSG layer, a front surface phosphorous diffusion, a rear surface PSG layer, and a rear surface phosphorous diffusion are formed, and wherein a first phosphorous dopant surface concentration in the substrate proximate to the set of patterns is less than a second dopant surface concentration in the substrate not proximate to the set of patterns.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: August 20, 2013
    Assignee: Innovalight, Inc.
    Inventors: Malcolm Abbott, Maxim Kelman, Eric Rosenfeld, Elena Rogojina, Giuseppe Scardera
  • Patent number: 8492253
    Abstract: Methods of forming contacts for back-contact solar cells are described. In one embodiment, a method includes forming a thin dielectric layer on a substrate, forming a polysilicon layer on the thin dielectric layer, forming and patterning a solid-state p-type dopant source on the polysilicon layer, forming an n-type dopant source layer over exposed regions of the polysilicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped polysilicon regions among a plurality of p-type doped polysilicon regions.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: July 23, 2013
    Assignee: SunPower Corporation
    Inventor: Jane Manning
  • Patent number: 8440552
    Abstract: A method includes providing an ETSOI wafer having a semiconductor layer having a top surface with at least one gate structure having on sidewalls thereof a layer of dielectric material. A portion of the layer of dielectric material extends away from the gate structure on the surface of the semiconductor layer. The method further includes faulting a raised S/D on the semiconductor layer adjacent to the portion of the layer of dielectric material, removing the portion of the layer of dielectric material to expose an underlying portion of the surface of the semiconductor layer and applying a layer of glass containing a dopant to cover at least the exposed portion of the surface of the semiconductor layer. The method further includes diffusing the dopant through the exposed portion of the surface of the semiconductor layer to form a source extension region and a drain extension region.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: May 14, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Chen, Bruce B. Doris, Balasubramanian S. Haran, Amlan Majumdar, Sanjay Mehta
  • Publication number: 20130112260
    Abstract: The present invention relates to a method for preparing, on a silicon wafer, an n+pp+ or p+nn+ structure which includes the following consecutive steps: a) on a p or n silicon wafer (1), which includes a front surface (8) and a rear surface (9), a layer of boron-doped silicon oxide (BSG) (2) is formed on the rear surface (9) by PECVD, followed by a SiOx diffusion barrier (3); b) a source of phosphorus is diffused such that the phosphorus and the boron co-diffuse and in order also to form: on the front surface (8) of the wafer obtained at the end of step a), a layer of phosphorus-doped silicon oxide (PSG) (4) and an n+ doped area (5); and on the rear surface of the wafer obtained at the end of step a), a boron-rich area (BRL) (6), as well as a p+ doped area (7); c) the layers of BSG (2) and PSG (4) oxides and SiOx (3) are removed, the BRL (6) is oxidised and the layer resulting from said oxidation is removed.
    Type: Application
    Filed: April 26, 2011
    Publication date: May 9, 2013
    Applicants: PHOTOWATT INTERNATIONAL, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON, SYNERGIES POUR EQUIPEMENTS MICRO-ELECTRONIQUE COMMUNICATION OPTIQUE SA
    Inventors: Barbara Bazer-Bachi, Mustapha Lemiti, Nam Le Quang, Yvon Pellegrin
  • Patent number: 8399343
    Abstract: A method for the selective doping of silicon of a silicon substrate (1) for producing a pn-junction in the silicon is characterized by the following steps: a) Providing the surface of the silicon substrate (1) with a doping agent (2) based on phosphorous, b) heating the silicon substrate (1) for creating a phosphorous silicate glass (2) on the surface of the silicon, wherein phosphorous diffuses into the silicon as a first doping (3), c) applying a mask (4) on the phosphorous silicate glass (2), covering the regions (5) that are later highly doped, d) removing the phosphorous silicate glass (2) in the non-masked regions, e) removing the mask (4) from the phosphorous silicate glass (2), f) again heating for the further diffusion of phosphorous from the phosphorous silicate glass (2) into the silicon as a second doping for creating the highly doped regions (5), g); complete removal of the phosphorous silicate glass (2) from the silicon.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: March 19, 2013
    Assignee: Gebr. Schmid GmbH & Co.
    Inventor: Dirk Habermann
  • Patent number: 8377738
    Abstract: A solar cell fabrication process includes printing of dopant sources over a polysilicon layer over backside of a solar cell substrate. The dopant sources are cured to diffuse dopants from the dopant sources into the polysilicon layer to form diffusion regions, and to crosslink the dopant sources to make them resistant to a subsequently performed texturing process. To prevent counter doping, dopants from one of the dopant sources are prevented from outgassing and diffusing into the other dopant source. For example, phosphorus from an N-type dopant source is prevented from diffusing to a P-type dopant source comprising boron.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: February 19, 2013
    Assignee: SunPower Corporation
    Inventors: Timothy D. Dennis, Bo Li, Peter John Cousins
  • Patent number: 8324089
    Abstract: Compositions for forming doped regions in semiconductor substrates, methods for fabricating such compositions, and methods for forming doped regions using such compositions are provided. In one embodiment, a dopant-comprising composition comprises a conductivity-determining type impurity dopant, a silicate carrier, a solvent, and a moisture adsorption-minimizing component. In another embodiment, a dopant-comprising composition comprises a conductivity-determining type impurity dopant, a silicate carrier, a solvent, and a high boiling point material selected from the group consisting of glycol ethers, alcohols, and combinations thereof. The high boiling point material has a boiling point of at least about 150° C.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: December 4, 2012
    Assignee: Honeywell International Inc.
    Inventors: Roger Yu-Kwan Leung, Wenya Fan, Jan Nedbal
  • Patent number: 8293553
    Abstract: In a method for producing at least at least one area (8) with reduced electrical conductivity within an electrically conductive III-V semiconductor layer (3), a ZnO layer (1) is applied to the area (8) of the semiconductor layer (3) and subsequently annealed at a temperature preferably between 300° C. and 500° C. The ZnO layer (1) is preferably deposited on the III-V semiconductor layer (3) at a temperature of less than 150° C., preferably at a temperature greater than or equal to 25° C. and less than or equal to 120° C. The area (8) with reduced electrical conductivity is preferably located in a radiation emitting optoelectronic device between the active zone (4) and a connecting contact (7) in order to reduce current injection into the areas of the active zone (4) located opposite to the connecting contact (7).
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: October 23, 2012
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Stefan Illek, Wilhelm Stein, Robert Walter, Ralph Wirth
  • Publication number: 20120193769
    Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.
    Type: Application
    Filed: May 23, 2011
    Publication date: August 2, 2012
    Inventors: Guojun Liu, Uma Srinivasan, Shivkumar Chiruvolu
  • Publication number: 20120184062
    Abstract: The composition for forming an n-type diffusion layer in accordance with the present invention contains a donor element-containing glass powder and a dispersion medium. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Application
    Filed: March 22, 2012
    Publication date: July 19, 2012
    Inventors: YOUICHI MACHII, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuuichirou Adachi, Takuya Aoyagi
  • Publication number: 20120178201
    Abstract: The composition for forming an n-type diffusion layer in accordance with the present invention contains a donor element-containing glass powder and a dispersion medium. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Application
    Filed: March 23, 2012
    Publication date: July 12, 2012
    Inventors: YOUICHI MACHII, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuuichirou Adachi, Takuya Aoyagi
  • Patent number: 8163639
    Abstract: A method of fabricating a photo diode includes sequentially forming a buried layer of a first conductivity type, a first epitaxial layer of the first conductivity type, and a second epitaxial layer of a second conductivity type on a semiconductor substrate; forming a doped oxide film, including impurities of the second conductivity type, on the second epitaxial layer; forming a silicon nitride film on the oxide film; and patterning the oxide film and the silicon nitride film to sequentially form an oxide film pattern of the second conductivity type and a silicon nitride film pattern, respectively. The second conductivity type impurities are diffused from the oxide film pattern into the second epitaxial layer using a heat diffusion process to form a doped shallow junction layer of the second conductivity type, which converts the oxide film pattern into a non-conductive oxide film pattern.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kye-wong Maeng, Sung-ryoul Bae
  • Patent number: 8124502
    Abstract: A semiconductor device manufacturing method is provided, including: providing a semiconductor substrate, forming on the semiconductor substrate a layer including a semiconductor compound and a dope additive, and thereafter forming an emitter region and gettering impurities by annealing the semiconductor substrate including the layer.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: February 28, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Rafel Ferre i Tomas
  • Patent number: 8114761
    Abstract: Methods for doping a non-planar structure by forming a conformal doped silicon glass layer on the non-planar structure are disclosed. A substrate having the non-planar structure formed thereon is positioned in chemical vapor deposition process chamber to deposit a conformal SACVD layer of doped glass (e.g. BSG or PSG). The substrate is then exposed to RTP or laser anneal step to diffuse the dopant into the non-planar structure and the doped glass layer is then removed by etching.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: February 14, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Tushar V. Mandrekar, Shankar Venkataraman, Zhong Qiang Hua, Manuel A. Hernandez
  • Patent number: 8058159
    Abstract: A method for fabricating a component is disclosed. The method includes: providing a member having an effective work function of an initial value, disposing a sacrificial layer on a surface of the member, disposing a first agent within the member to obtain a predetermined concentration of the agent at said surface of the member, annealing the member, and removing the sacrificial layer to expose said surface of the member, wherein said surface has a post-process effective work function that is different from the initial value.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: November 15, 2011
    Assignee: General Electric Company
    Inventors: Vance Robinson, Stanton Earl Weaver, Joseph Darryl Michael
  • Patent number: 7999268
    Abstract: The method described herein enables the introduction of external impurities into Silicon Carbide (SiC) to be conducted at a temperature between 1150-1400° C. Advantages include: a) low temperature diffusion procedure with greater control of the doping process, b) prevent roughness of SiC surface, c) less surface defects and d) better device performance and higher yield. The method described herein involves depositing a ceramic layer that contains the desired impurity and a certain element such as oxygen (in the form of oxide), or other elements/compounds that draw out the silicon and carbon atoms from the surface region of the SiC leaving behind carbon and silicon vacancies which then allow the external impurity to diffuse into the SiC more easily. In another embodiment, the deposited layer also has carbon atoms that discourage carbon from escaping from the SiC, thus generating a surface region of excess carbon in addition to the silicon vacancies.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: August 16, 2011
    Assignee: Auburn University
    Inventors: Chin-Che Tin, Adetayo Victor Adedeji, Ilkham Gafurovich Atabayev, Bakhtiyar Gafurovich Atabaev, Tojiddin Mutalovich Saliev, Erkin Nurovich Bakhranov, Mingyu Li, Balapuwaduge Suwan Pathum Mendis, Ayayi Claude Ahyi
  • Patent number: 7998823
    Abstract: By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: August 16, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Carsten Peters, Kai Frohberg, Ralf Richter
  • Patent number: 7851339
    Abstract: Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating containing easily diffusible atoms that can form negatively charged ions and can diffuse deep into the substrate. In one embodiment, the easily diffusible atoms comprise at least 5% by atomic concentration of chlorine atoms in the sacrificial oxide coating and the nitrogen releasing atmosphere includes NO. The high temperature anneal is carried out for less than 10 hours at a temperature less than 1100° C.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: December 14, 2010
    Assignee: Promos Technologies Pte. Ltd.
    Inventors: Zhong Dong, Ching-Hwa Chen
  • Patent number: 7799650
    Abstract: A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: September 21, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiangzheng Bo, Venkat R. Kolagunta, Konstantin V. Loiko
  • Patent number: 7785945
    Abstract: A method for fabricating a PMOS transistor is disclosed herein. In one embodiment, the method can include forming a gate insulation layer and a polysilicon layer over a semiconductor substrate; asymmetrically etching the polysilicon layer; doping the asymmetrically etched polysilicon layer with a P-type dopant; diffusing the dopant in the asymmetrically etched polysilicon layer towards the semiconductor substrate; planarizing the asymmetrically etched polysilicon layer; forming a gate metal layer over the planarized polysilicon layer; forming a hard mask, which delimits a region to be formed with a gate of the PMOS transistor, over the gate metal layer; forming a gate stack by patterning the gate metal layer, the planarized polysilicon layer, and the gate insulation layer; and forming a source/drain in the semiconductor substrate at both sides of the gate stack.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: August 31, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyoung Bong Rouh
  • Patent number: 7767541
    Abstract: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Brian Joseph Greene, Jack Allan Mandelman
  • Patent number: 7615393
    Abstract: A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron, the substrate including a first substrate surface with a first surface region and a second surface region. The method also includes depositing a first set of nanoparticles on the first surface region, the first set of nanoparticles including a first dopant. The method further includes heating the substrate in an inert ambient to a first temperature and for a first time period creating a first densified film, and further creating a first diffused region with a first diffusion depth in the substrate beneath the first surface region.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: November 10, 2009
    Assignee: Innovalight, Inc.
    Inventors: Sunil Shah, Malcolm Abbott
  • Patent number: 7611977
    Abstract: This invention discloses a process of phosphorus diffusion for manufacturing solar cell, comprising annealing a mono-crystalline silicon wafer in a nitrogen atmosphere at 900-950° C. for twenty to thirty minutes, carrying oxidation treatment in a hydrogen chloride atmosphere at 850-1050° C. to form a 10 to 30 nm thick oxide layer on the surface of said silicon wafer, diffusing from a phosphorus source at 850-900° C., until a block resistance of a material surface is controlled at 40 to 50 ohms, and the junction depth is at 0.2 to 1.0 microns, and annealing in a nitrogen atmosphere at 700-750° C. for thirty to sixty minutes to complete the phosphorus diffusion of said mono-crystalline silicon wafer. This invention allows the use of 4 N˜5 N mono-crystalline silicon as the material for manufacturing solar cells, so, the low purity material such as metallurgical silicon can be used, which greatly reduces the cost of materials.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: November 3, 2009
    Assignee: CSI Cells Co. Ltd.
    Inventors: Lingjun Zhang, Yunxiang Zuo
  • Patent number: 7566600
    Abstract: A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: July 28, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Chandra V. Mouli
  • Patent number: 7524743
    Abstract: A method of doping includes depositing a layer of dopant material on nonplanar and planar features of a substrate. Inert ions are generated from an inert feed gas. The inert ions are extracted towards the substrate where they physically knock the dopant material into both the planar and nonplanar features of the substrate.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: April 28, 2009
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Atul Gupta, Vikram Singh, Timothy Miller, Edmund Jacques Winder
  • Publication number: 20080248639
    Abstract: An undoped GaN layer having a thickness of 3 ?m is formed by MOVPE on a sapphire substrate with a buffer layer composed of aluminum nitride (AlN) therebetween. A GaN layer doped with 5×1019/cm3 of Mg and having a thickness of 100 nm is formed thereon. An ITO film having a thickness of 300 nm is formed by vacuum evaporation (EB). The wafer is kept in nitrogen at 700° C. for 5 minutes so as to reduce the resistance of the GaN layer doped with 5×1019/cm3 of Mg and having a thickness of 100 nm, so that a p-GaN layer is obtained. A FeCl3 aqueous solution is prepared, and the ITO film is removed. In this manner, a surface of the p-GaN layer having reduced resistance is exposed. The hole concentration is 4.3×1017/cm3. The resistivity is 3.0 ?cm.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 9, 2008
    Applicant: TOYODA GOSEI CO., LTD.
    Inventor: Miki Moriyama
  • Patent number: 7235468
    Abstract: FinFET devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and methods for producing the same. The methods involve dopant implants into the insulator layer, thereby creating borophosphosilicate glass (BPSG) diffusion sources within the insulation layer underlying the active regions of the SOI wafer. Backend high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the active regions, thereby forming a retrograde dopant profile extending towards the channel region. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: June 26, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Chandra V. Mouli
  • Patent number: 7144751
    Abstract: Methods for fabrication of emitter wrap through (EWT) back-contact solar cells and cells made by such methods. Certain methods provide for higher concentration of dopant in conductive vias compared to the average dopant concentration on front or rear surfaces, and provided increased efficiency. Certain methods provide for selective doping to holes for forming conductive vias by use of printed dopant pastes. Other methods provide for use of spin-on glass substrates including dopant.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: December 5, 2006
    Assignee: Advent Solar, Inc.
    Inventors: James M. Gee, Peter Hacke
  • Patent number: 7115476
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a semiconductor pillar, doping an impurity into the semiconductor substrate, thereby forming a first source/drain region in part of the semiconductor substrate, which is located under the semiconductor pillar, forming a gate insulating film on the semiconductor substrate, which contacts a side surface of the semiconductor pillar, forming a gate electrode on a side surface of the gate insulating film, forming a first insulating layer on the gate electrode, which contacts a side surface of the semiconductor pillar, and doping the impurity into the first insulating layer, thereby forming a second source/drain region in part of the semiconductor pillar, which is located on a side surface of the first insulating layer.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: October 3, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Izumida
  • Patent number: 7105411
    Abstract: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: September 12, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Akram Ditali
  • Patent number: 7078315
    Abstract: The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The shallow trench surrounds an active area. A non-doped silicate glass (NSG) layer is deposited to fill the shallow trench, and is then etched back to a depth of the shallow trench, thereby exposing a portion of the semiconductor substrate at an upper portion of the shallow trench. A doped dielectric layer is deposited over the remaining NSG layer to cover the exposed semiconductor substrate. A thermal process is then carried out to diffuse dopants of the doped dielectric layer into the semiconductor substrate, thereby forming a doped region at the periphery of the active area in a channel width direction.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: July 18, 2006
    Assignee: Nanya Technology Corp.
    Inventors: Ming-Cheng Chang, Tieh-Chiang Wu, Yinan Chen
  • Patent number: 7022576
    Abstract: The present invention relates to a method of manufacturing a semiconductor device. According to the present invention, a sidewall layer containing impurities is formed on a part of gate electrode, thereby forming a low concentration source/drain electrode for a lightly doped drain (LDD) structure not by conventional ion implanting process but by out diffusion of impurities contained in the sidewall. Thus, it is made possible to minimizes damages of substrate due to ion implanting process, since the number of process of ion implantation may be naturally minimized through the above mentioned ion implantation process according to the present invention. Also, it is made possible for gate electrode to maintain its size independently, regardless of distance between source electrode and drain electrode, by excluding a role of ion implanting mask which has been performed by gate electrode.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: April 4, 2006
    Assignee: DongbuAnam Semiconductor Inc.
    Inventor: Yong Soo Cho
  • Patent number: 6995061
    Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: February 7, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Ching-Nan Hsiao, Chi-Hui Lin, Ying-Cheng Chuang