Abstract: The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The shallow trench surrounds an active area. A non-doped silicate glass (NSG) layer is deposited to fill the shallow trench, and is then etched back to a depth of the shallow trench, thereby exposing a portion of the semiconductor substrate at an upper portion of the shallow trench. A doped dielectric layer is deposited over the remaining NSG layer to cover the exposed semiconductor substrate. A thermal process is then carried out to diffuse dopants of the doped dielectric layer into the semiconductor substrate, thereby forming a doped region at the periphery of the active area in a channel width direction.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. According to the present invention, a sidewall layer containing impurities is formed on a part of gate electrode, thereby forming a low concentration source/drain electrode for a lightly doped drain (LDD) structure not by conventional ion implanting process but by out diffusion of impurities contained in the sidewall. Thus, it is made possible to minimizes damages of substrate due to ion implanting process, since the number of process of ion implantation may be naturally minimized through the above mentioned ion implantation process according to the present invention. Also, it is made possible for gate electrode to maintain its size independently, regardless of distance between source electrode and drain electrode, by excluding a role of ion implanting mask which has been performed by gate electrode.

Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

Abstract: Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

Abstract: A method for fabricating a buried plate of a deep trench capacitor is described. A substrate having a deep trench therein is provided. A doped layer is formed on the surface of the deep trench and a material layer is formed on the doped layer. A passivation layer is formed on the sidewall of the deep trench that is not covered by the material layer. After removing the material layer, a thermal process is conducted to drive-in the dopants in the doped layer to the substrate to form a doped region, wherein the doped region serves as a buried plate of the deep trench capacitor. The doped layer also reacts with the substrate to form an oxide layer. After removing the oxide layer, a bottle-shaped deep trench is formed.

Abstract: A method of purging a semiconductor manufacturing apparatus comprises a step of etching a CVD-deposited film deposited in a chamber constituting a semiconductor manufacturing apparatus which has performed a process of forming a CVD film using a CVD process over a semiconductor wafer by using an etching gas containing at least a halogen gas, and a step of purging a cleaning gas remaining in the chamber by causing a gas containing hydrogen to flow into the chamber after the step of etching the CVD-deposited film by using the cleaning gas.

Abstract: An improved dopant application system and method for the manufacture of microelectronic devices accurately places dopant on and within a dielectric or semiconductor surface. Diffusing and activating p-type and n-type dopants in dielectric or semiconductor substrates is achieved by means of electron beam irradiation.

Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

Abstract: This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15′), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10′). This first substrate (10′) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.

Abstract: A method is proposed for producing semiconductor components, in which at least one doped region is introduced in a wafer, a solid glass layer provided with dopant being applied on at least one of the two sides of a semiconductor wafer, in another step, the wafer being heated to high temperatures so that the dopant from the glass layer penetrates deep into the wafer to produce the at least one doped region; and in a further step, the glass layer being removed. The method is used for producing homogeneous, heavily doped regions, it also being possible to introduce these regions in the wafer on both sides and for the regions to be of different doping type.

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric constant spacer layer. Anisotropic etching of the combined layers form spacers surrounding the gate oxide stack.

Abstract: One aspect of the invention relates to a method of forming P—N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.

Abstract: An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided.

Abstract: A method of forming a salicide. A metal layer is formed on a silicon-based substrate comprising a gate with a spacer on the side wall of the gate and a source/drain is provided. Next, a first thermal treatment is performed to make the portions of the metal layer react with the silicon in the gate and the source/drain to form a salicide. Then, any unreacted metal and the spacer are removed. An ion containing silicon is introduced into the source/drain. Finally, a second thermal treatment is performed.

Abstract: A method of writing data into a memory cell of a non-volatile semiconductor memory device includes setting a write voltage applied to portions of the memory cells depending upon a value of write data, and applying, to a gate electrode, a voltage by which an electric charge is allowed to tunnel through an insulating film on a lower side of a dialectric film that captures the electric charge corresponding to a data value. The amount of electric charge captured is easily and reliably adjusted in order to store desired multi-value digital data, while preventing occurrence of data corruption.

Abstract: A method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface, which does not result in deposition of silicon atoms over the entire surface of the silicon substrate and which does not require the silicon storage nodes to be comprised of amorphous silicon prior to being subjected to the surface-roughening treatment.

Abstract: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate.

Abstract: One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.

Abstract: A method of fabricating a MOS transistor having shallow source/drain junction regions is provided. A diffusion source layer is formed on a semiconductor substrate on which gate patterns are formed. Same type or different type of impurities are implanted into the diffusion source layer several times in different directions. As a result, dislocation does not occur and the impurity concentration of the diffusion source layer can be nonuniformly controlled so that damage to the crystal structure of the semiconductor substrate does not occur. Also, the impurities nonuniformly contained in the diffusion source layer are diffused into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD regions and highly doped source/drain regions by a self-alignment method.

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally annealed to drive dopants from the solid-phase impurity source into the source and drain regions. The dopants from the impurity source provide ultra-shallow source and drain extensions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract: A technique for fabricating a solar cell includes an n+ emitter region first being formed on a front surface of the cell, and then front and rear insulating layers being formed on both sides of the cell. P (Phosphorus)-source and B (Boron)-source are printed on the front and rear insulating layers, respectively, and then both dopants are diffused into the cell at high temperature. Therefore, n++ region in the front side of the cell and BSF (back surface field) region in the rear side of the cell is formed. Front and rear contact patterns are formed on the front and rear insulating layers, respectively. The n++ region and BSF region are exposed after front and rear contacts are formed on the front and rear insulating layers, respectively. The front and rear contacts contact the n++ region and BSF region, respectively.

Abstract: Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

Abstract: Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and the dopant is diffused through those layers. The polysilicon provides sacrificial silicon that serves to prevent the formation of boron silicon nitride on the substrate surface and also protects the oxide layer during etching of the silicon glass layer. The oxide layer then acts as an etch stop during removal of the polysilicon layer. In this way, no damage done to the substrate surface during the diffusion or subsequent etch steps and the need for expensive ion implanter steps is avoided.

Abstract: Test structures for a high voltage MOSFET are provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. A plurality of trenches are located in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches. The test structures allow the simultaneous optimization of the breakdown voltage and on-resistance of the device.

Abstract: A method for doping one side of a semiconductor substrate, such as in a silicon wafer, wherein an oxide layer is deposited on both the side to be doped and the non-doped side of the semiconductor substrate. A doping layer, containing a doping agent, is deposited onto the oxide layer on the side to be doped. The doping agent passes through the oxide layer on the side to be doped and into the semiconductor substrate. The oxide layer on the non-doped side serves as a protective layer, preventing diffusion of the doping agent into the undoped side of the substrate.

Abstract: There are included the steps of depositing a film that contains zinc oxide and silicon oxide to contain the zinc oxide by 70 wt % or more on compound semiconductor layer as a diffusion source, and diffusing zinc from the diffusion source into the compound semiconductor layer by annealing. Accordingly, there can be provided a compound semiconductor device manufacturing method containing the step of diffusing zinc into compound semiconductor layers, capable of deepening a Zn diffusion position from a ZnO/SiO2 film to such extent that COD endurance of laser end face window structures can be increased rather than the prior art.

Abstract: A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped source and drain regions in a field effect transistor so as to obtain a required gradual dopant concentration transition from the general region to the drain and source regions for avoiding the hot carrier effect. Advantageously, a diffusion of the dopant atoms is initiated during an oxidizing step in which the thickness of the gate insulation layer is increased at the edge portions thereof.

Abstract: For fabricating a vertical field effect transistor on a semiconductor substrate, a bottom layer of doped insulating material is deposited on the semiconductor substrate. A layer of dummy material is deposited on the bottom layer of doped insulating material. A top layer of doped insulating material is deposited on the layer of dummy material. An opening is etched through the top layer of doped insulating material, the layer of dummy material, and the bottom layer of doped insulating material. A semiconductor fill is contained within the opening. The semiconductor fill has at least one sidewall with a top portion of the sidewall abutting the top layer of doped insulating material, a middle portion of the sidewall abutting the layer of dummy material, and a bottom portion of the sidewall abutting the bottom layer of doped insulating material. The layer of dummy material is etched away such that the middle portion of the sidewall of the semiconductor fill is exposed.

Abstract: High integrity cobalt silicide contacts are formed with shallow source/drain junctions. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, followed by silicidation and diffusing impurities from a doped film during or after silicidation in an environment which discourages out-diffusion of the impurities to the environment. The resulting source/drain junctions are self-aligned to the cobalt silicide/silicon substrate interface, thereby preventing junction leakage while advantageously enabling forming the cobalt silicide contacts at optimum thickness to avoid parasitic series resistances. The formation of self-aligned source/drain junctions to the cobalt silicide/silicon substrate interface facilitates reliable device scaling, while the avoidance of unwanted diffusion of impurities to the environment assures adequate doping of the source/drain regions.

Abstract: A method of fabricating an integrated circuit (IC) with source and drain extension regions. Advantageously, the source and drain extension regions are formed without damage related to integrated circuit implant techniques. Damage is avoided by using solid phase doping to form extension regions. Generally, a doped material is provided adjacent to a transistor gate structure and the IC is annealed. During the annealing process, dopants from the doped material diffuse into the semiconductor substrate to form the source and drain extension regions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs).

Abstract: A method for doping crystals is disclosed. The method includes a receiver for receiving semiconductor spheres and doping powder. The semiconductor spheres and dopant powder are then directed to a chamber defined within an enclosure. The chamber maintains a heated, inert atmosphere with which to diffuse the dopant to the semiconductor spheres.

Abstract: A CMOS memory device includes source and drain regions diffused into a substrate, a polysilicon gate structure formed over a channel region located between the first and second diffusion regions, and a pre-metal dielectric structure formed over the polysilicon gate structure. The pre-metal dielectric structure is a triple layer structure including a lower Borophosphosilicate glass (BPSG) layer formed over the polysilicon gate structure, a Nitride layer formed on the lower BPSG layer, and an upper dielectric layer (e.g., BPSG or USG) formed on the Nitride layer. The Phosphorous concentration in the lower BPSG layer is greater than the Phosphorous concentration in the upper dielectric layer, thereby providing retention protection for the underlying memory structures while facilitating optimal chemical mechanical polishing (CMP) planarization characteristics.

Abstract: A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of a trench. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sensitive resist by substantially vertical implantation such that the ion-implanted-sensitive resist over the lower and upper horizontal surfaces is insoluble portions in a developer and the vertical surface is soluble in the developer. Subsequently, the vertical surface is removed by using the developer and then the doped dielectric layer attached on the vertical surface is also removed. Then, a CMP process is used to remove the ion-implanted-sensitive resist and the doped dielectric layer. Next, a thermal treatment is used to diffuse the dopants in the doped dielectric layer into the lower horizontal surface.

Abstract: A method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface, which does not result in deposition of silicon atoms over the entire surface of the silicon substrate and which does not require the silicon storage nodes to be comprised of amorphous silicon prior to being subjected to the surface-roughening treatment.

Abstract: The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.

Abstract: The invention relates to a method of manufacturing a (horizontal) MOST, as used, for example, in (BI)CMOS ICs. On either side of a gate electrode (2), the surface of a silicon substrate (10, 11) which is positioned above a gate oxide (IA) is provided with a dielectric layer (1B) at the location where a source (3) and drain (4) are to be formed, which dielectric layer includes a thermal oxide layer (1B) to be formed as the starting layer. The source (3) and/or drain (4) is/are provided with LDD regions (3A, 4A) and the remaining parts (3B, 4B) of the source (3) and drain (4) are provided by an ion implantation (I1) of doping atoms into the silicon substrate (10, 11). A MOST obtained in this way still suffers from so-called short-channel effects, resulting in a substantial dependence of the threshold voltage upon the length of the gate electrode (2), in particular in the case of very short lengths of the gate electrode (2).

Abstract: A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on corresponding portions (34, 37) of the major surface (31) of the substrate (30) overlying the amorphous region (32). The substrate (30) is then annealed. The annealing process melts the amorphous region (32) and allows the dopants precipitated on the major surface (31) to diffuse into the substrate (30). The annealing process also crystallizes the semiconductor material the amorphous region (32). The substrate (30) becomes a single crystal semiconductor substrate with multiple doped regions (54, 57) therein. The depth of the doped regions (54, 57) is substantially equal to the depth of the amorphous region (32) before annealing.

Abstract: A titanium oxide film containing a dopant element formed on a silicon substrate by supplying a titanium compound for forming the titanium oxide film and a compound of a dopant element for a silicon semiconductor in a gaseous state to a surface of the silicon substrate heated to a predetermined temperature, wherein the concentration of the dopant element in the titanium oxide film becomes progressively higher from the surface of the titanium oxide film to the surface of the silicon substrate.

Abstract: An opto-electronic device has a diffusion area of one conductive type formed in a semiconductor substrate of another conductive type, an ohmic contact layer making contact with the diffusion area, and an electrode making contact with the ohmic contact layer. The diffusion area is formed by solid-phase diffusion. The same mask is used to define the patterns of both the diffusion source layer and the ohmic contact layer, so that the ohmic contact layer is self-aligned with the diffusion area.

Abstract: The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the present invention comprising a step of physically contacting a semiconductor surface having a layer of a dopant/bandgap source material thereon such that upon said physical contact impurity atoms from the dopant/bandgap source material are driven into the semiconductor substrate.

Abstract: The method of the present invention includes the following steps. First, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped polysilicon layer. A photoresist layer is formed over the first dielectric layer. Next, the photoresist layer is patterned to define a gate region. An etching process is performed to the photoresist layer to narrow the gate region. Portions of the first dielectric layer are etched using the residual photoresist layer as a mask. The undoped polysilicon layer is etched using the residual photoresist layer and the residual first dielectric layer as a mask. Then, a PSG is layer deposited over the residual first dielectric layer and the substrate. Subsequently, the PSG layer is etched back to form side-wall spacers to serve as ion diffusion source. A noble or refractory metal layer is deposited on all areas of the substrate.

Abstract: A dual work function gate conductor with a self-aligned insulating cap and method for forming the same is provided. Two diffusion regions are formed in a substrate and a gate stack is formed over the substrate between the diffusion regions. The gate stack includes a gate insulating layer formed on the substrate and a layer of polysilicon on top of the gate insulating layer. The polysilicon layer may be doped n-type remain intrinsic. A barrier layer is formed on top of the polysilicon layer and a dopant source layer is formed on top of the barrier layer. The barrier layer contains a p-type dopant. The gate stack is enclosed by an insulating cap so that a diffusion contact can be formed borderless to the gate. Activation of the dopant source layer to dope a polysilicon layer can be delayed until a desired time.

Abstract: A method for forming very deep pn-junctions without using epitaxy or extensively high temperature processing is provided. At least two parallel deep trenches are etched into a silicon substrate. Then the sidewalls of these trenches are predeposited by dopants. After filling the deep trenches with insulating material, a diffusion process is done. This diffusion process performs in such a way that the formerly predeposited dopant is distributed rather uniformly in between the parallel deep trenches, e.g. is counterdoping the whole region with respect to the monocrystalline silicon substrate. The said lateral trench doped region, which preferably is more deep than wide, serves either as drain or collector region of high voltage transistors or other high voltage devices. Also other devices like hall sensors, which gain advantages from the more deep than wide counterdoped regions, are possible.

Abstract: A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region. and a base link-up region within the collector region between the intrinsic base region and the extrinsic base region. An emitter region is positioned within the intrinsic base region. A base electrode overlays and is in electrical communication with a portion of the extrinsic base region and the base link-up region, and a doped inter-polysilicon dielectric layer overlays a portion of the base electrode. A capping layer is positioned above the inter-polysilicon dielectric layer; and an emitter electrode overlays the inter-polysilicon dielectric layer and the emitter region. The doped inter-polysilicon dielectric layer is the dopant source for forming the extrinsic base region and the base link-up region.

Abstract: A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region including one edge of the gate electrode; a second gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a second portion including the other edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer; a first impurity region formed in a predetermined portion of the semiconductor substrate, placed on both sides of the gate electrode; and a second impurity region formed in a predetermined portion of the semiconductor substrate, placed under the second gate insulating layer.

Abstract: Semiconductor devices are fabricated by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a conductive-forming layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the conductive-forming layer; depositing a conductive material through the opening over the conductive layer; planarizing the second insulating layer and the conductive material; removing the second insulating layer, the conductive-forming layer and the first insulating layer except beneath the conductive material; and forming source/drain regions in the substrate; or by providing a substrate; forming isolation regions in the substrate; forming a first insulating laye

Abstract: A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.

Abstract: A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.

Abstract: A scavenger layer is provided to prevent the diffusion of an excess mobile specie from a metal oxide ceramic into unwanted parts of a device. The scavenger layer is provided above the metal oxide ceramic. As the excess mobile specie diffuses out of the metal oxide ceramic, it migrates toward the scavenger layer and reacts with it. The reaction consumes the excess mobile specie.