Gettering Of Substrate Patents (Class 438/58)
  • Patent number: 9735267
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a source structure at least partially in a semiconductor substrate. The semiconductor device structure also includes a channel structure over the semiconductor substrate. The source structure is partially covered by the channel structure. The semiconductor device structure further includes a drain structure covering the channel structure. The drain structure and the source structure have different conductivity types. A portion of the channel structure is sandwiched between the source structure and the drain structure. In addition, the semiconductor device structure includes a gate stack partially covering the channel structure.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: August 15, 2017
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Steve S. Chung, E-Ray Hsieh, Yi-Hsien Lin
  • Patent number: 9524872
    Abstract: A heterogeneous integrated circuit and method of making the same. An integrated circuit includes a surrogate substrate including a material selected from the group consisting of Group II, Group III, Group IV, Group V, and Group VI materials and their combinations; at least one active semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials; and at least one transferred semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials. The at least one active semiconductor device and the at least one transferred device are interconnected.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: December 20, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Peter D. Brewer, Andrew T. Hunter, Yakov Royter
  • Patent number: 9190556
    Abstract: A method of hydrogenation of a silicon photovoltaic junction device is provided, the silicon photovoltaic junction device comprising p-type silicon semiconductor material and n-type silicon semiconductor material forming at least one p-n junction. The method comprises: i) ensuring that any silicon surface phosphorus diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×1020 atoms/cm3 or less and silicon surface boron diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×1019 atoms/cm3 or less; ii) Providing one or more hydrogen sources accessible by each surface of the device; and iii) Heating the device, or a local region of the device to at least 40° C.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: November 17, 2015
    Assignee: NewSouth Innovations Pty Limited
    Inventors: Stuart Ross Wenham, Phillip George Hamer, Brett Jason Hallam, Adeline Sugianto, Catherine Emily Chan, Lihui Song, Pei Hsuan Lu, Alison Maree Wenham, Ly Mai, Chee Mun Chong, GuangQi Xu, Matthew Edwards
  • Patent number: 9129918
    Abstract: Systems and methods are provided for annealing a semiconductor structure. For example, a semiconductor structure is provided. An energy-converting material capable of increasing the semiconductor structure's absorption of microwave radiation is provided. A heat reflector is provided between the energy-converting material and the semiconductor structure, the heat reflector being capable of reflecting thermal radiation from the semiconductor structure. Microwave radiation is applied to the energy-converting material and the semiconductor structure to anneal the semiconductor structure for fabricating semiconductor devices.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Hsiung Tsai, Zi-Wei Fang, Chao-Hsiung Wang
  • Publication number: 20150136204
    Abstract: Disclosed is a solar cell structure for thermal insulation, which includes an intermediate support glass plate, a solar cell structure (A) provided at one side based on the support glass plate, and a vacuum glass panel structure (B) provided at the other side based on the support glass plate. The solar cell structure for thermal insulation may have an insulation function while generating power by using solar ray, thereby saving the energy consumed by a building while ensuring a lighting function.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 21, 2015
    Applicant: EAGON WINDOWS & DOORS CO., LTD.
    Inventors: Kye-Yong Yang, Jung-Hyuk Ahn, Jae-Yong Eom, Rho-Ho Park
  • Publication number: 20150132881
    Abstract: A method of hydrogenation of a silicon photovoltaic junction device is provided, the silicon photovoltaic junction device comprising p-type silicon semiconductor material and n-type silicon semiconductor material forming at least one p-n junction. The method comprises: i) ensuring that any silicon surface phosphorus diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×1020 atoms/cm3 or less and silicon surface boron diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×1019 atoms/cm3 or less; ii) Providing one or more hydrogen sources accessible by each surface of the device; and iii) Heating the device, or a local region of the device to at least 40° C.
    Type: Application
    Filed: December 4, 2014
    Publication date: May 14, 2015
    Inventors: STUART ROSS WENHAM, Phillip George Hamer, Brett Jason Hallam, Adeline Sugianto, Catherine Emily Chan, Lihui Song, Pei Hsuan Lu, Alison Maree Wenham, Ly Mai, Chee Mun Chong, GuangQi Xu, Matthew Edwards
  • Publication number: 20150125987
    Abstract: A method for chemically cleaning and passivating a chalcogenide layer is provided, wherein the method comprises bringing the chalcogenide layer into contact with an ammonium sulfide containing ambient, such as an ammonium sulfide liquid solution or an ammonium sulfide containing vapor. Further, a method for fabricating photovoltaic cells with a chalcogenide absorber layer is provided, wherein the method comprises: providing a chalcogenide semiconductor layer on a substrate; bringing the chalcogenide semiconductor layer into contact with an ammonium sulfide containing ambient, thereby removing impurities and passivating the chalcogenide semiconductor layer; and afterwards providing a buffer layer on the chalcogenide semiconductor layer.
    Type: Application
    Filed: September 29, 2014
    Publication date: May 7, 2015
    Inventors: Marie Buffiere, Marc Meuris, Guy Brammertz
  • Publication number: 20150111333
    Abstract: A method of hydrogenation of a silicon photovoltaic junction device is provided, the silicon photovoltaic junction device comprising p-type silicon semiconductor material and n-type silicon semiconductor material forming at least one p-n junction. The method comprises: i) ensuring that any silicon surface phosphorus diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×1020 atoms/cm3 or less and silicon surface boron diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×1019 atoms/cm3 or less; ii) Providing one or more hydrogen sources accessible by each surface of the device; and iii) Heating the device, or a local region of the device to at least 40° C.
    Type: Application
    Filed: May 20, 2013
    Publication date: April 23, 2015
    Applicant: NewSouth Innovations Pty Limited
    Inventors: Stuart Ross Wenham, Phillip George Hamer, Brett Jason Hallam, Adeline Sugianto, Catherine Emily Chan, Lihui Song, Pei Hsuan Lu, Alison Maree Wenham, Ly Mai, Chee Mun Chong, GuangQi Xu, Matthew Edwards
  • Patent number: 8999864
    Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: April 7, 2015
    Assignee: Global Wafers Japan Co., Ltd.
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
  • Publication number: 20150072460
    Abstract: The invention relates to a device for depositing a layer made of at least two components on an object, with a deposition chamber for disposing the object, at least one source with material to be deposited, as well as at least one device for controlling the deposition process, implemented such that the concentration of at least one component of the material to be deposited can be modified in its gas phase prior to deposition on the substrate by selective binding of a specified quantity of the at least one component, wherein the selectively bound quantity of the at least one component can be controlled by modifying at least one control parameter that is actively coupled to a binding rate or the component. It further relates to a device for depositing a layer made of at least two components on an object, wherein a device for controlling the deposition process has at least one gettering element made of a reactive material, wherein the reactive material includes copper and/or molybdenum.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 12, 2015
    Applicant: SAINT-GOBAIN GLASS FRANCE
    Inventors: Joerg PALM, Stephan POHLNER, Stefan JOST, Thomas HAPP
  • Patent number: 8963156
    Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gordon Haller, Paul D. Long
  • Patent number: 8933497
    Abstract: A semiconductor switch device and a method of manufacturing the semiconductor switch device are provided. The semiconductor switch device includes semiconductor elements on a single semiconductor substrate. At least one of the semiconductor elements constitutes a switch circuit and at least one other of the semiconductor elements constitutes a logic (connection) circuit. Each semiconductor element includes a recess, a gate electrode in the recess, a drain electrode, and a source electrode. In one representative aspect, the gate electrode in the switch circuit can have a rectangular external shape in section, and the gate electrode in the connection circuit has a shape in section other than rectangular.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: January 13, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tsunekazu Saimei, Kazuya Kobayashi, Koshi Himeda, Nobuyoshi Okuda
  • Publication number: 20140357011
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Application
    Filed: August 18, 2014
    Publication date: December 4, 2014
    Inventor: Shin Iwabuchi
  • Patent number: 8900907
    Abstract: A method for removing the growth substrate of a circuit of electromagnetic radiation detection, especially in the infrared or visible range, said detection circuit including a layer of detection of said radiation made of Hg(1-x)CdxTe obtained by liquid or vapor phase epitaxy or by molecular beam epitaxy, said detection circuit being hybridized on a read circuit. The method includes submitting the growth substrate to a mechanical or chem.-mech. polishing step or to a chemical etch step to decrease its thickness, all the way to an interface area between the material of the detection circuit and the growth substrate; and submitting the interface thus obtained to an iodine treatment.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 2, 2014
    Assignees: Societe Francaise de Detecteurs Infrarouges-Sofradir, Centre National de la Recherche Scientifique
    Inventors: Christophe Pautet, Arnaud Etcheberry, Alexandre Causier, Isabelle Gerard
  • Patent number: 8889456
    Abstract: A method for fabricating a photovoltaic device includes performing a gettering process in a processing chamber which restricts formation of a layer of gettering materials on a substrate and forming a solder layer on the substrate. The solder layer is annealed to form uniformly distributed solder dots which grow on the substrate. The substrate is etched using the solder dots to protect portions of the substrate and form cones in the substrate such that the cones provide a three-dimensional radiation absorbing structure for the photovoltaic device.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Augustin J. Hong, Jeehwan Kim, Jae-Woong Nah, Devendra K. Sadana
  • Publication number: 20140332065
    Abstract: The present invention refers to a composite getter for thin-film photovoltaic panels which is made with a polymer having low H2O transmission containing one or more alkaline earth metal oxide, to a photovoltaic panel containing such composite getter and to a method for the manufacturing of photovoltaic panels.
    Type: Application
    Filed: July 29, 2014
    Publication date: November 13, 2014
    Inventors: Sergio RONDENA, Antonio BONUCCI, Giorgio LONGONI, Luca TOIA, Marco AMIOTTI
  • Patent number: 8841158
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: September 23, 2014
    Assignee: Sony Corporation
    Inventor: Shin Iwabuchi
  • Publication number: 20140264695
    Abstract: An image sensor includes a semiconductor layer having a first surface and a second surface opposite to each other and including a photodiode and a hydrogen containing region adjacent the first surface. A crystalline anti-reflective layer is on the first surface of the semiconductor layer, and is configured to allow hydrogen atoms to penetrate into the first surface of the semiconductor layer. Driving transistors and wires are on the second surface of the semiconductor layer, and a color filter and a micro lens are on the anti-reflective layer. The hydrogen containing region contains hydrogen atoms that combine with defects at the first surface.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Inventors: Yun-Ki Lee, Chang-Rok Moon, Duck-Hyung Lee
  • Patent number: 8828780
    Abstract: This invention relates to a method of manufacturing a substrate for photoelectric conversion device including, on a substrate, a first electrode layer formed of a transparent conductive material. The method includes a first transparent conductive film forming step of forming a first transparent conductive film on the substrate, a second transparent conductive film forming step of forming a second transparent conductive film under a film forming condition that an etching rate is low compared with the first transparent conductive film at a later etching step, and an etching step of wet-etching the second and first transparent conductive films to form recesses that pierce through at least the second transparent conductive film, with the bottoms of the recesses being present in the first transparent conductive film.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: September 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsutomu Matsuura, Hiroya Yamarin, Yuki Tsuda
  • Publication number: 20140238490
    Abstract: A method (100) for decreasing an excess carrier induced degradation in a silicon substrate, includes providing (120, 130) a charged insulation layer capable of retaining charge on the silicon substrate for generating a potential difference between the charged insulation layer and the silicon substrate, and heat treating (140) the silicon substrate for enabling an impurity causing the excess carrier induced degradation and being in the silicon substrate to diffuse due to the potential difference into a boundary of the silicon substrate and the insulation layer.
    Type: Application
    Filed: October 1, 2012
    Publication date: August 28, 2014
    Applicant: AALTO-KORKEAKOULUSAATIO
    Inventors: Antti Haarahiltunen, Hele Savin, Marko Veli Yli-Koski
  • Patent number: 8809098
    Abstract: Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor also includes a radiation-detection device that is formed in the substrate. The radiation-detection device is operable to detect a radiation wave that enters the substrate through the back side. The image sensor further includes a recrystallized silicon layer. The recrystallized silicon layer is formed on the back side of the substrate. The recrystallized silicon layer has different photoluminescence intensity than the substrate.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Yeur-Luen Tu, Jen-Cheng Liu, Keng-Yu Chou, Chung Chien Wang
  • Publication number: 20140216535
    Abstract: A photovoltaic device including a protective layer between a window layer and an absorber layer, the protective layer inhibiting dissolving/intermixing of the window layer into the absorber layer during a device activation step, and methods of forming such photovoltaic devices.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 7, 2014
    Applicant: FIRST SOLAR, INC.
    Inventors: Daniel Damjanovic, Jing Guo, Sreenivas Jayaraman, Oleh P. Karpenko, Feng Liao, Chong Lim, Rick C. Powell, Jigish Trivedi, Zhibo Zhao
  • Publication number: 20140216542
    Abstract: A photovoltaic device and its method of manufacture are disclosed. The device is formed by forming a window layer over a substrate, forming an absorber layer over the window layer, and annealing the absorber layer using a laser beam to remove contaminants from the surface of the absorber layer and/or to reduce the thickness of the absorber layer.
    Type: Application
    Filed: February 6, 2014
    Publication date: August 7, 2014
    Applicant: First Solar, Inc.
    Inventors: RUI SHAO, Sudirukkuge Tharanga Jinasundera
  • Patent number: 8772068
    Abstract: A method of forming contacts on a surface emitter of a silicon solar cell is provided. In the method an n-type diffusion of a surface is performed to form a doped emitter surface layer that has a sheet resistance of 10-40 ?/?. The emitter surface layer is then etched back to increase the sheet resistance of the emitter surface layer. Finally the surface is selectively plated. A method of fabrication of a silicon solar cell includes performing a front surface emitter diffusion of n-type dopant and then performing a dielectric deposition on the front surface by PECVD. The dielectric deposition comprises: a. growth of a thin silicon oxide; b. PECVD deposition of silicon nitride to achieve a silicon nitride. The silicon is then annealed to drive hydrogen from the silicon nitride layer into the silicon to passivate the silicon.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: July 8, 2014
    Assignee: Newsouth Innovations PTY Limited
    Inventors: Stuart Ross Wenham, Budi Santoso Tjahjono, Nicole Bianca Kuepper, Alison Joan Lennon
  • Publication number: 20140162394
    Abstract: Provided is a method for manufacturing a solar cell with improved output characteristics. A hydrogen radical treatment, in which ions are not used, is performed on at least one of the first and second semiconductor layers (11, 13).
    Type: Application
    Filed: November 26, 2013
    Publication date: June 12, 2014
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Motohide Kai, Tomonori Ueyama, Masaki Shima
  • Publication number: 20140147956
    Abstract: To reduce degradation, by the LID effect, of the conversion efficiency of photovoltaic cells made of crystalline silicon, one or more steps of controlled introduction of voids into the silicon are carried out by one or more steps chosen from among: siliciding, nitriding, ion implantation, laser irradiation, mechanical bending stress applied on one face of the silicon substrate, in combination with a temperature promoting the formation of voids in the substrate. These voids make it possible to reduce the level of interstitial oxygen by an effect of diffusion of VO complexes and precipitation of oxygen. The introduction of voids has the other effect of reducing the level of autointerstitials, and therefore of limiting the formation of interstitial boron. The phenomena of LID by activation of BiOi2 complexes are thus limited. This applies notably to photovoltaic cells based on monocrystalline or polycrystalline silicon having a high concentration of boron and oxygen.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 29, 2014
    Applicant: Commissariat A L'Energie Atomique et Aux Energies Alternatives
    Inventors: Pascal Pochet, Sébastien Dubois
  • Patent number: 8735204
    Abstract: Methods for contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication are provided. In one embodiment, a method for fabricating an electrical semiconductor device comprises: a first step that includes gettering of impurities from a semiconductor wafer and forming a backsurface field; and a second step that includes forming a front contact for the semiconductor wafer, wherein the second step is performed after completion of the first step.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 27, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventor: Bhushan Sopori
  • Patent number: 8735203
    Abstract: The present invention relates to multicrystalline p-type silicon wafers with high lifetime. The silicon wafers contain 0.2-2.8 ppma boron and 0.06-2.8 ppma phosphorous and/or arsenic and have been subjected to phosphorous diffusion and phosphorous gettering at a temperature of above 925° C. The invention further relates to a method for production of such multicrystalline silicon wafers and to solar cells comprising such silicon wafers.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: May 27, 2014
    Assignee: Elkem Solar AS
    Inventors: Eric Enebakk, Kristian Peter, Bernd Raabe, Ragnar Tronstad
  • Publication number: 20140065752
    Abstract: A method for fabricating a photovoltaic device includes performing a gettering process in a processing chamber which restricts formation of a layer of gettering materials on a substrate and forming a solder layer on the substrate. The solder layer is annealed to form uniformly distributed solder dots which grow on the substrate. The substrate is etched using the solder dots to protect portions of the substrate and form cones in the substrate such that the cones provide a three-dimensional radiation absorbing structure for the photovoltaic device.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Augustin J. Hong, Jeehwan Kim, Jae-Woong Nah, Devendra K. Sadana
  • Patent number: 8658516
    Abstract: An object of the present invention is to provide a method of producing a silicon wafer and a method of producing an epitaxial wafer, which enable easily forming a gettering site in a relatively short period of time and effectively suppressing occurrence of dislocation induced by internal stresses. Specifically, the present invention provides a method of producing a silicon wafer, comprising: irradiating a first laser beam having a relatively long wavelength and a second laser beam having a relatively short wavelength onto a portion of a silicon wafer located at a predetermined depth measured from a surface of the silicon wafer, wherein the first laser beam is concentrated at a portion located at a predetermined depth of the wafer to form a process-affected layer for gettering heavy metals thereat, the second laser beam is concentrated at a beam-concentration portion in the vicinity of the surface of the wafer to melt the beam-concentration portion, the beam-concentration portion is then recrystallized.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: February 25, 2014
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Patent number: 8629044
    Abstract: An object of the present invention is to provide a method of producing a silicon wafer and a method of producing an epitaxial wafer, which enable easily forming a gettering site in a relatively short period of time and effectively suppressing occurrence of dislocation induced by internal stresses. Specifically, the present invention provides a method of producing a silicon wafer, comprising: irradiating a first laser beam having a relatively long wavelength and a second laser beam having a relatively short wavelength onto a portion of a silicon wafer located at a predetermined depth measured from a surface of the silicon wafer, wherein the first laser beam is concentrated at a portion located at a predetermined depth of the wafer to form a process-affected layer for gettering heavy metals thereat, the second laser beam is concentrated at a beam-concentration portion in the vicinity of the surface of the wafer to melt the beam-concentration portion, the beam-concentration portion is then recrystallized.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: January 14, 2014
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Publication number: 20140000675
    Abstract: A method for manufacturing a solar cell element is disclosed. The method includes two different etching processes followed by forming a semiconductor layer. A semiconductor substrate having a first conductor type is etched by using a first acid aqueous solution containing hydrofluoric acid, nitric acid, and sulfuric acid. Then, the semiconductor substrate is etched by using a second acid aqueous solution containing hydrofluoric acid and nitric acid with substantially no sulfuric acid to make an uneven surface. A semiconductor layer of second conductivity type different from the first conductivity type is formed on at least a part of the uneven surface of the semiconductor substrate.
    Type: Application
    Filed: January 27, 2012
    Publication date: January 2, 2014
    Applicant: KYOCERA CORPORATION
    Inventors: Manabu Komoda, Yasuhiro Okada, Yuusuke Nagou, Takeshi Ito, Hitohiko Nakamura
  • Patent number: 8614495
    Abstract: Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor also includes a radiation-detection device that is formed in the substrate. The radiation-detection device is operable to detect a radiation wave that enters the substrate through the back side. The image sensor further includes a recrystallized silicon layer. The recrystalized silicon layer is formed on the back side of the substrate. The recrystalized silicon layer has different photoluminescence intensity than the substrate.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: December 24, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Yeur-Luen Tu, Jen-Cheng Liu, Keng-Yu Chou, Chung Chien Wang
  • Patent number: 8609451
    Abstract: Fabrication of a single crystal silicon solar cell with an insitu epitaxially deposited very highly doped p-type silicon back surface field obviates the need for the conventional aluminum screen printing step, thus enabling a thinner silicon solar cell because of no aluminum induced bow in the cell. Furthermore, fabrication of a single crystal silicon solar cell with insitu epitaxial p-n junction formation and very highly doped n-type silicon front surface field completely avoids the conventional dopant diffusion step and one screen printing step, thus enabling a cheaper manufacturing process.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Crystal Solar Inc.
    Inventors: Tirunelveli S. Ravi, Ashish Asthana
  • Patent number: 8598547
    Abstract: Glitches during ion implantation of a workpiece, such as a solar cell, can be compensated for. In one instance, a workpiece is implanted during a first pass at a first speed. This first pass results in a region of uneven dose in the workpiece. The workpiece is then implanted during a second pass at a second speed. This second speed is different from the first speed. The second speed may correspond to the entire workpiece or just the region of uneven dose in the workpiece.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: December 3, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Russell J. Low, Atul Gupta, William T. Weaver
  • Patent number: 8575661
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: November 5, 2013
    Assignee: Sony Corporation
    Inventor: Shin Iwabuchi
  • Patent number: 8497150
    Abstract: This invention discloses a defect isolation method for thin-film solar cell having at least a defect therein. The thin-film solar cell comprises a substrate, a front electrode layer, an absorber layer and a back electrode layer stacked in such a sequence. The defect isolation method includes the steps of: detecting at least a defect formed in thin-film solar cell and acquiring the positions of the defects, and applying a laser light to scribe the outer circumference of the defects according to the positions of the defects so as to form at least an isolation groove having a closed-curve configuration.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: July 30, 2013
    Assignee: Nexpower Technology Corp.
    Inventors: Yung-Yuan Chang, Hui-Chu Lin
  • Patent number: 8492190
    Abstract: A method for manufacturing a display panel includes; formation of a lower gate line, disposal of a semiconductor on the lower gate line, disposal of a lower data line substantially perpendicular to the lower gate line, disposal of an insulating layer having a plurality of trenches exposing the lower gate line and the lower data line on the lower data line, disposal of an upper gate line directly on the lower gate line and within the plurality of trenches, and disposal of an upper data line directly on the lower data line and within the plurality of trenches.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: July 23, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joo-Ae Youn, Yang-Ho Bae, Chang-Oh Jeong, Chong-Chul Chai, Pil-Sang Yun, Honglong Ning, Byeong-Beom Kim
  • Patent number: 8470630
    Abstract: The invention relates to a method for capping a MEMS wafer (1), in particular a sensor and/or actuator wafer, with at least one mechanical functional element (10). According to the invention, it is provided that the movable mechanical functional element (10) is fixed by means of a sacrificial layer (14), and that a cap layer (19) is applied to, in particular epitaxially grown onto, the sacrificial layer (14) and/or to at least one intermediate layer (17) applied to the sacrificial layer (14). The invention also relates to a capped MEMS wafer (1).
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: June 25, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Joachim Rudhard, Thorsten Mueller
  • Patent number: 8460964
    Abstract: A method for producing a thin-film solar cell with a cell level integrated bypass diode includes forming at least three series-connected solar cells, each cell being a laminated structure including semiconducting material of first and second types, a front electrode in contact with the material of the first type, and a back electrode in contact with the material of the second type. The bypass diode is formed by total separation from a selected parent cell. The material of the first type of the diode is connected to the material of the second type of any one chosen solar cell in the array. The material of the second type of the diode is connected with the material of the first type of the one chosen solar cell in the array so that the diode is connected in parallel and in opposition to the one chosen solar cell.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: June 11, 2013
    Assignee: E I du Pont de Nemours and Company
    Inventors: Meijun Lu, Lap-Tak Andrew Cheng
  • Patent number: 8441032
    Abstract: A system and method providing for the detection of an input signal, either optical or electrical, by using a single independent discrete amplifier or by distributing the input signal into independent signal components that are independently amplified. The input signal can either be the result of photoabsorption process in the wavelengths greater than 950 nm or a low-level electrical signal. The discrete amplifier is an avalanche amplifier operable in a non-gated mode while biased in or above the breakdown region, and includes a composite dielectric feedback layer monolithically integrated with input signal detection and amplification semiconductor layers.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: May 14, 2013
    Assignee: Amplification Technologies, Inc.
    Inventor: Krishna Linga
  • Publication number: 20130109124
    Abstract: In one aspect of the present invention, a method is included. The method includes thermally processing an assembly to form at least one transparent layer. The assembly includes a first panel including a first layer disposed on a first support and a second panel including a second layer disposed on a second support, wherein the second panel faces the first panel, and wherein the first layer and the second layer include substantially amorphous cadmium tin oxide. Method of making a photovoltaic device is also included.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 2, 2013
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Hongying Peng, Juan Carlos Rojo, Hongbo Cao, George Theodore Dalakos, Holly Ann Blaydes, David William Vernooy, Mark Jeffrey Pavol, Jae Hyuk Her, Hong Piao, Robert Dwayne Gossman, Scott Daniel Feldman-Peabody, Yangang Andrew Xi
  • Publication number: 20130102102
    Abstract: A vacuum recycling apparatus for refining solar grade polysilicon is provided which contains a vacuum degassing (VD) device and a vacuum recycling (RH) device. By storing liquid silicon in a bucket in the VD device, controlling the pressure inside the VD and RH devices, and introducing inert gas into the apparatus, the liquid silicon is stirred for the removal of impurities. With the present invention, solar grade polysilicon can be directly produced with a specified purity, significantly reducing the production time and cost.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 25, 2013
    Inventors: Wen-Pin Sun, Hsiu-Min Huang
  • Patent number: 8399280
    Abstract: A method for protecting, against laser attacks, an integrated circuit chip formed inside and on top of a semiconductor substrate and including in the upper portion of the substrate an active portion in which are formed components, this method including the steps of: forming in the substrate a gettering area extending under the active portion, the upper limit of the area being at a depth ranging between 5 and 50 ?m from the upper surface of the substrate; and introducing diffusing metal impurities into the substrate.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: March 19, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Patent number: 8389999
    Abstract: A crystalline material structure with reduced dislocation density and method of producing same is provided. The crystalline material structure is annealed at temperatures above the brittle-to-ductile transition temperature of the crystalline material structure. One or more stress elements are formed on the crystalline material structure so as to annihilate dislocations or to move them into less harmful locations.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: March 5, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Anthony Buonassisi, Mariana Bertoni, Ali Argon, Sergio Castellanos, Alexandria Fecych, Douglas Powell, Michelle Vogl
  • Publication number: 20130019934
    Abstract: Methods are generally disclosed for forming a thin film photovoltaic device. According to one embodiment, a transparent conductive oxide layer and an oxygen getter layer can be formed on a transparent substrate. The transparent conductive oxide layer and the oxygen getter layer can then be annealed together such that oxygen atoms move from the transparent conductive oxide layer into the oxygen getter layer. A photovoltaic heterojunction can be formed on the TCO layer. Thin film photovoltaic devices are also generally disclosed.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 24, 2013
    Applicant: PRIMESTAR SOLAR, INC.
    Inventors: Robert Dwayne Gossman, Scott Daniel Feldman-Peabody, Jeffrey Todd Knapp
  • Publication number: 20120322192
    Abstract: An improved solar cell is disclosed. To create the internal p-n junction, one surface of the substrate is implanted with ions. After the implantation, the substrate is thermally treated. The thermal process distributes the dopant throughout the substrate, while repairing crystal damage caused by implantation. After the thermal process, residual crystal damage may remain, which adversely impacts solar cell efficiency. In order to further reduce the residual damage, the uppermost portion of the surface is then removed, thereby eliminating that portion of the substrate where most of the defects reside. The lower defect concentration reduces recombination and improves efficiency of the solar cell.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 20, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: John Graff, Nicholas Bateman
  • Patent number: 8329563
    Abstract: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: December 11, 2012
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadaharu Minato, Hidekazu Yamamoto
  • Patent number: 8316745
    Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: November 27, 2012
    Assignee: Calisolar Inc.
    Inventors: Fritz G. Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniaina, Dieter Linke
  • Patent number: 8309436
    Abstract: A method of producing an epitaxial substrate for a solid-state imaging device, comprising: forming a gettering sink by injecting laser beam to a semiconductor substrate through one surface thereof, condensing the laser beam to an arbitrarily selected portion of the semiconductor substrate, thereby causing multi-photon absorption process to occur in the portion, and forming a gettering sink having a modified crystal structure; and epitaxially growing at least two epitaxial layers on the semiconductor substrate in which the gettering sink is formed.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: November 13, 2012
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita