Gettering Of Substrate Patents (Class 438/58)
  • Patent number: 8257995
    Abstract: A cleave plane is defined in a semiconductor donor body by implanting ions into the wafer. A lamina is cleaved from the donor body, and a photovoltaic cell is formed which comprises the lamina. The implant may cause some damage to the crystal structure of the lamina. This damage can be repaired by annealing the lamina using microwave energy. If the lamina is bonded to a receiver element, the receiver element may be either transparent to microwaves, or may reflect microwaves, while the semiconductor material absorbs the microwaves. In this way the lamina can be annealed at high temperature while the receiver element remains cooler.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: September 4, 2012
    Assignee: Twin Creeks Technologies, Inc.
    Inventors: Mohamed M Hilali, Venkatesan Murali, Gopal Prabhu, Zhiyong Li
  • Patent number: 8241941
    Abstract: The invention relates to a method of purifying a crystalline silicon substrate and to a process for producing a photovoltaic cell. The method of purifying a crystalline silicon substrate according to the invention is of the type that includes a step of extracting impurities by external gettering and which includes, before said step of extracting the impurities by external gettering, at least one step of rapidly annealing the substrate at a temperature of between 750° C. and 1000° C. inclusive for a time of between 1 second and 10 minutes inclusive. The invention is particularly applicable in the photovoltaic cell field.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: August 14, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Sébastien Dubois, Nicolas Enjalbert, Rémi Monna
  • Patent number: 8232133
    Abstract: An image sensor includes a semiconductor layer that filters light of different wavelengths. For example, the semiconductor layer absorbs photons of shorter wavelengths and passes more photons of longer wavelengths such that the longer wavelength photons often pass through without being absorbed. An imaging pixel having a photodiode is formed near a front side of the semiconductor layer. A dopant layer is formed below the photodiode near a back side of the semiconductor layer. A mirror that primarily reflects photons of longer visible wavelengths is disposed on the back side of the semiconductor layer.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: July 31, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Howard E. Rhodes, Hidetoshi Nozaki
  • Patent number: 8207048
    Abstract: Method for producing nanostructures comprising: a step of providing a substrate (100) having a buried barrier layer (2) and above said barrier layer (2) a crystalline film (5) provided with a network of crystalline defects and/or stress fields (12) in a crystalline zone (13), one or several steps of attacking the substrate (100), of which a preferential attack either of the crystalline defects and/or the stress fields, or the crystalline zone (13) between the crystalline defects and/or the stress fields, said attack steps enabling the barrier layer (2) to be laid bared locally and protrusions (7) to be formed on a nanometric scale, separated from each other by hollows (7.1) having a base located in the barrier layer, the protrusions leading to nanostructures (7, 8).
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: June 26, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Franck Fournel, Hubert Moriceau, Chrystel Deguet
  • Publication number: 20120125431
    Abstract: An organic electronic device which does not deteriorate a device function over a long period of time and a method for its manufacture. The organic electronic device, containing: an organic semiconductor element (B) including a pair of electrodes; a layer (C) containing a scavenger, which absorbs at least one of moisture and oxygen; and a gas barrier film (D), in that order; and an anticorrosion layer (E) between the pair of electrodes and the layer (C), wherein the layer (E) has a film thickness of 20 ?m or more, and a water vapor transmission rate Pe (g/m2/day) of layer (E) at 40° C. and 90% RH is 15 g/m2/day?Pe>Pd relative to a water vapor transmission rate Pd of the film (D) at 40° C. and 90% RH, wherein Pd is 10?4?Pd?10?1 g/m2/day.
    Type: Application
    Filed: December 23, 2011
    Publication date: May 24, 2012
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Junichi OIZUMI, Katsuya Funayama, Takashi Fujiwara, Takahiro Yoneyama, Keishin Handa
  • Publication number: 20120126096
    Abstract: According to one embodiment, a semiconductor layer in which a photoelectric conversion unit is formed for each pixel, a readout circuit that is formed on a front side of the semiconductor layer and reads out a signal from the photoelectric conversion unit, a light incident surface provided on a back side of the photoelectric conversion unit, and a gettering layer provided on a front side of the photoelectric conversion unit are included.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 24, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuki SUGIURA, Takeo Nakayama
  • Patent number: 8143142
    Abstract: A method of fabricating an epi-wafer includes providing a wafer including boron by cutting a single crystal silicon ingot, growing an insulating layer on one surface of the wafer, performing thermal treatment of the wafer, removing the insulating layer formed on one surface of the wafer, mirror-surface-grinding one surface of the wafer, and growing an epitaxial layer on one surface of the wafer and forming a high-density boron layer within the wafer that corresponds to the interface between the wafer and the epitaxial layer.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 27, 2012
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Young-Soo Park, Gi-Jung Kim, Won-Je Park, Jae-Sik Bae
  • Publication number: 20120060925
    Abstract: Disclosed is a surface processing method of a crystalline silicon substrate for a solar cell, and a method for manufacturing a solar cell. The surface processing method of a substrate for a solar cell comprises first surface processing step for forming a plurality of first protrusions on surfaces of a substrate by etching the crystalline silicon substrate by using an aqueous solution, second surface processing step for forming a plurality of second protrusions smaller than the first protrusions by adhering etching residues onto an upper surface, a light receiving surface among the surfaces of the substrate, by using first etching gas, and residue removing step for removing etching residues adhered onto the upper surface of the substrate having undergone the second surface processing step.
    Type: Application
    Filed: December 20, 2010
    Publication date: March 15, 2012
    Inventor: Byung-Jun KIM
  • Patent number: 8124437
    Abstract: Disclosed herein is a method for manufacturing a solar cell. The method includes the following steps. A substrate is provided. An article having a plurality of protrusions touches the surface of the substrate and thereby forming a plurality of indentations thereon. Subsequently, a transparent conductive layer is formed on the indented surface of the substrate, a photovoltaic layer is formed on the transparent conductive layer, and then a back electrode is form above the photovoltaic layer.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 28, 2012
    Assignee: Du Pont Apollo Limited
    Inventors: Chu-Wan Huang, Ching-Yee Chak
  • Patent number: 8124502
    Abstract: A semiconductor device manufacturing method is provided, including: providing a semiconductor substrate, forming on the semiconductor substrate a layer including a semiconductor compound and a dope additive, and thereafter forming an emitter region and gettering impurities by annealing the semiconductor substrate including the layer.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: February 28, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Rafel Ferre i Tomas
  • Patent number: 8105860
    Abstract: The specification teaches a device for use in the manufacturing of microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In a preferred embodiment the invention includes a mechanical supporting base, and a layer of a gas absorbing or purifier material is deposited on the base by a variety of techniques and a layer for temporary protection of the purification material is placed on top of the purification material. The temporary protection material is compatible for use in the microdevice and can be removed during the manufacture of the microdevice.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: January 31, 2012
    Assignee: Saes Getters, S.p.A.
    Inventor: Marco Amiotti
  • Publication number: 20120006389
    Abstract: An embodiment of a method of manufacturing a photoelectric conversion device according to the present invention includes specifying a spot having an abnormal physical property in a structure comprising a photoelectric conversion member, including a semiconductor layer, between a pair of first and second electrodes, and isolating the spot having an abnormal physical property through mechanical scribing.
    Type: Application
    Filed: June 29, 2010
    Publication date: January 12, 2012
    Applicant: KYOCERA CORPORATION
    Inventors: Norihiko Matsushima, Daisuke Nishimura, Atsuo Hatate, Takeshi Ohkuma, Hisao Arimune, Yukari Hashimoto
  • Patent number: 8093089
    Abstract: Method of manufacturing image sensors having a plurality of gettering regions. In the method, a gate electrode may be formed on a semiconductor substrate. A source/drain region may be formed in the semiconductor substrate to be overlapped with the gate electrode. A gettering region may be formed in the semiconductor substrate to be adjacent to the source/drain region.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: January 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyun-Pil Noh
  • Patent number: 8087135
    Abstract: A piezoelectric vibrator manufacturing method includes a cavity forming step for forming depressions for a cavities on at least one of two wafers; a bonding electrode film forming step for forming bonding electrode films on bonded surfaces of the both wafers; a mount pattern forming step for forming a pair of mount patterns in the cavity; a through hole forming step for forming a pair of through holes in the cavity; a through electrode forming step for forming a pair of through electrodes electrically connected with the pattern in the cavity; a mount step for electrically connecting the pattern and a piezoelectric vibrating strip, a superimposing step for superimposing the both wafers and storing getter materials; a bonding step for anodically bonding the both wafers to fabricating a wafer member; a gettering step for adjusting the degree of vacuum in the interior of the cavity while measuring a series resonance resistance value; and a cutting step for cutting the wafer member into individual pieces.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: January 3, 2012
    Assignee: Seiko Instruments Inc.
    Inventors: Keiichi Ouchi, Yuki Hoshi
  • Patent number: 8084286
    Abstract: Producing a solid-state imaging device by (1) forming a structure including (a) a substrate having a first impurity with a first concentration, (b) a first conductive type Si layer and (c) a first conductive type impurity layer stacked on one another in that order, the first conductive type Si layer being formed on the substrate, the first conductive type impurity layer being formed in a boundary region including a boundary of the substrate and the Si layer, and a part of the substrate facing the boundary and a part of the first conductive type Si layer facing the boundary having a second impurity; and (2) forming in the Si layer a second conductive type region capable of storing in the Si layer a charge generated by a photoelectric conversion; and forming an interconnection layer on the Si layer.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: December 27, 2011
    Assignee: Sony Corporation
    Inventor: Hideo Kanbe
  • Publication number: 20110248372
    Abstract: A semiconductor wafer is set in a laser irradiation apparatus, and laser beam irradiation is performed while the semiconductor wafer is moved. At this time, a laser beam emitted from a laser generating apparatus is condensed by a condensing lens so that the condensing point (focal point) is positioned at a depth of several tens of gm or so from one surface of the semiconductor wafer. Thereby, the crystal structure of the semiconductor wafer in the position having such a depth is modified, and a gettering sink is formed.
    Type: Application
    Filed: October 16, 2009
    Publication date: October 13, 2011
    Applicant: SUMCO CORPORATION
    Inventor: Kazunari Kurita
  • Patent number: 8008107
    Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: August 30, 2011
    Assignee: Calisolar, Inc.
    Inventors: Fritz Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniana, Dieter Linke
  • Patent number: 8003423
    Abstract: A method for manufacturing a poly-crystal silicon photovoltaic device using horizontal metal induced crystallization comprises the steps of forming at least one layer of an amorphous silicon thin film on a substrate, forming at least one groove of which depth is less than or equal to that of the thin film on the amorphous silicon thin film, and horizontally crystallizing the amorphous silicon thin film by forming a metal layer on an upper portion of the groove. Since a crystal shape and a growth direction of the photovoltaic device can be adjusted by the method, a poly-crystal silicon thin film for improving current flow can be formed at a low-temperature.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: August 23, 2011
    Assignee: LG Electronics Inc.
    Inventors: Jung-Heum Yun, Kwy-Ro Lee, Don-Hee Lee, Heon-Min Lee
  • Publication number: 20110189805
    Abstract: An object of the present invention is to provide a method of producing a silicon wafer and a method of producing an epitaxial wafer, which enable easily forming a gettering site in a relatively short period of time and effectively suppressing occurrence of dislocation induced by internal stresses. Specifically, the present invention provides a method of producing a silicon wafer, comprising: irradiating a first laser beam having a relatively long wavelength and a second laser beam having a relatively short wavelength onto a portion of a silicon wafer located at a predetermined depth measured from a surface of the silicon wafer, wherein the first laser beam is concentrated at a portion located at a predetermined depth of the wafer to form a process-affected layer for gettering heavy metals thereat, the second laser beam is concentrated at a beam-concentration portion in the vicinity of the surface of the wafer to melt the beam-concentration portion, the beam-concentration portion is then recrystallized.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 4, 2011
    Applicant: SUMCO CORPORATION
    Inventor: Kazunari Kurita
  • Patent number: 7968987
    Abstract: A chip module assembly includes a CO2 getter exposed through a gas-permeable membrane to a chip cavity of a chip module. One or more chips is/are enclosed within the cavity. The CO2 getter comprises a liquid composition including 1,8-diaza-bicyclo-[5,4,0]-undec-7-ene (DBU) in a solvent that includes an alcohol, preferably, 1-hexanol. In one embodiment, a sheet of gas-permeable membrane is heat-welded to form a pillow-shaped bag in which the liquid composition is sealed. The pillow-shaped bag containing the liquid composition is preferably disposed in a recess of a heat sink and exposed to the cavity through a passage between the recess and the cavity. The CO2 getter can remove a relatively large amount of carbon dioxide from the cavity, and thus effectively prevents solder joint corrosion. For example, based on the formula weights and densities of the DBU and 1-hexanol, 200 g of the liquid composition can remove over 34 g of carbon dioxide.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventor: Joseph Kuczynski
  • Patent number: 7964430
    Abstract: Methods and apparatus for reducing defects on transparent conducting oxide (TCO) layer are provided. In one embodiment, a method for depositing a silicon layer on a transparent conducting oxide (TCO) layer may include providing a substrate having a TCO layer disposed thereon, wherein the TCO layer has a peripheral region and a cell integrated region, the cell integrated region having laser scribing patterns disposed thereon, positioning the substrate on a substrate support assembly disposed in a processing chamber, wherein the substrate support assembly has a roughened surface in contact with the substrate, contacting a shadow frame to the peripheral region of the TCO layer and to the substrate support assembly thereby creating an electrical ground path between the TCO layer and substrate support through the shadow frame, and depositing a silicon containing layer on the TCO layer through an aperture of the shadow frame.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: June 21, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Tae Kyung Won, Soo Young Choi, Yong Kee Chae, Liwei Li, Shuran Sheng
  • Publication number: 20110143480
    Abstract: A cleave plane is defined in a semiconductor donor body by implanting ions into the wafer. A lamina is cleaved from the donor body, and a photovoltaic cell is formed which comprises the lamina. The implant may cause some damage to the crystal structure of the lamina. This damage can be repaired by annealing the lamina using microwave energy. If the lamina is bonded to a receiver element, the receiver element may be either transparent to microwaves, or may reflect microwaves, while the semiconductor material absorbs the microwaves. In this way the lamina can be annealed at high temperature while the receiver element remains cooler.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 16, 2011
    Applicant: TWIN CREEKS TECHNOLOGIES, INC.
    Inventors: Mohamed M. Hilali, Murali Venkatesan, Gopal Prabhu, Zhiyong Li
  • Publication number: 20110136287
    Abstract: In a method of annealing a Cd1?xZnxTe sample/wafer, surface contamination is removed from the sample/wafer and the sample/wafer is then introduced into a chamber. The chamber is evacuated and Hydrogen or Deuterium gas is introduced into the evacuated chamber. The sample/wafer is heated to a suitable annealing temperature in the presence of the Hydrogen or Deuterium gas for a predetermined period of time.
    Type: Application
    Filed: June 2, 2009
    Publication date: June 9, 2011
    Applicant: II-VI INCORPORATED
    Inventors: Csaba Szeles, Michael Prokesch, Utpal Chakrabarti
  • Patent number: 7943414
    Abstract: An object of an embodiment of the present invention to be disclosed is to prevent oxygen from being taken in a single crystal semiconductor layer in laser irradiation even when crystallinity of the single crystal semiconductor layer is repaired by irradiation with a laser beam; and to make substantially equal or reduce an oxygen concentration in the semiconductor layer after the laser irradiation comparing before the laser irradiation. A single crystal semiconductor layer which is provided over a base substrate by bonding is irradiated with a laser beam, whereby the crystallinity of the single crystal semiconductor layer is repaired. The laser irradiation is performed under a reducing atmosphere or an inert atmosphere.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: May 17, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hideto Ohnuma, Junpei Momo, Shunpei Yamazaki
  • Patent number: 7923353
    Abstract: It is shown in the invention a method for manufacturing a semiconductor wafer structure with an active layer for impurity removal, which method comprises phases of depositing a first layer on a first wafer surface for providing an active layer, an optional phase of preparation for said first layer for next phase, growing thermal oxide layer on a second wafer, bonding said first and second wafers into a stack, annealing the stack for a crystalline formation in said thermal oxide layer as a second layer, and thinning said first wafer to a pre-determined thickness. The invention concerns also a wafer manufactured according to the method, chip that utilizes such a wafer structure and an electronic device utilizing such a chip.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: April 12, 2011
    Assignee: Okmetic Oyj
    Inventor: Jari Mäkinen
  • Patent number: 7923280
    Abstract: A method and apparatus for thermally processing a substrate is provided. A substrate is disposed within a processing chamber configured for thermal processing by directing electromagnetic energy toward a surface of the substrate. An energy blocker is provided to block at least a portion of the energy directed toward the substrate. The blocker prevents damage to the substrate from thermal stresses as the incident energy approaches an edge of the substrate.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: April 12, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Blake Koelmel, Robert C. McIntosh, David D L Larmagnac, Alexander N. Lerner, Abhilash J. Mayur, Joseph Yudovsky
  • Patent number: 7923709
    Abstract: A system for shielding personnel and/or equipment from radiation particles. In one embodiment, a first substrate is connected to a first array or perpendicularly oriented metal-like fingers, and a second, electrically conducting substrate has an array of carbon nanostructure (CNS) fingers, coated with an electro-active polymer extending toward, but spaced apart from, the first substrate fingers. An electric current and electric charge discharge and dissipation system, connected to the second substrate, receives a current and/or voltage pulse initially generated when the first substrate receives incident radiation. In another embodiment, an array of CNSs is immersed in a first layer of hydrogen-rich polymers and in a second layer of metal-like material. In another embodiment, a one- or two-dimensional assembly of fibers containing CNSs embedded in a metal-like matrix serves as a radiation-protective fabric or body covering.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: April 12, 2011
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Bin Chen, Christoper P. McKay
  • Publication number: 20110073184
    Abstract: The present invention provides a method for manufacturing a monocrystalline film and a device formed by the above method, and according to the method mentioned above, lift-off of the monocrystalline silicon film is preferably performed and a high-purity monocrystalline silicon film can be obtained. A monocrystalline silicon substrate (template Si substrate) 201 is prepared, and on this monocrystalline silicon substrate 201, an epitaxial sacrificial layer 202 is formed. Subsequently, on this sacrificial layer 202, a monocrystalline silicon thin film 203 is rapidly epitaxially-grown using a RVD method, followed by etching of the sacrificial layer 202, whereby a monocrystalline silicon thin film 204 used as a photovoltaic layer of solar cells is formed.
    Type: Application
    Filed: December 8, 2010
    Publication date: March 31, 2011
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventor: Suguru Noda
  • Publication number: 20110073869
    Abstract: A crystalline material structure with reduced dislocation density and method of producing same is provided. The crystalline material structure is annealed at temperatures above the brittle-to-ductile transition temperature of the crystalline material structure. One or more stress elements are formed on the crystalline material structure so as to annihilate dislocations or to move them into less harmful locations.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 31, 2011
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Anthony Buonassisi, Mariana Bertoni, Ali Argon, Sergio Castellanos, Alexandria Fecych, Douglas Powell, Michelle Vogl
  • Patent number: 7910391
    Abstract: The present disclosure relates to methods of treating a silicon substrate with an ultra-fast laser to create a getter material for example in a substantially enclosed MEMS package. In an embodiment, the laser treating comprises irradiating the silicon surface with a plurality of laser pulses adding gettering microstructure to the treated surface. Semiconductor based packaged devices, e.g. MEMS, are given as examples hereof.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: March 22, 2011
    Assignee: SiOnyx, Inc.
    Inventor: Susan Alie
  • Publication number: 20110053351
    Abstract: The present disclosure passivates solar cell defects. Plasma immersion ion implantation (PIII) is used to repair the defects during or after making the solar cell. Hydrogen ion is implanted into absorption layer with different sums of energy to fill gaps of defects or surface recombination centers. Thus, solar cell defects are diminished and carriers are transferred with improved photovoltaic conversion efficiency.
    Type: Application
    Filed: August 9, 2010
    Publication date: March 3, 2011
    Applicant: ATOMIC ENERGY COUNCIL-INSTITUTE OF NUCLEAR ENERGY RESEARCH
    Inventors: Wen-Fa Tsai, Jyong-Fong Liao, Yen-Yu Chen, Chee Wee Liu, Chi-Fong Ai
  • Publication number: 20110049664
    Abstract: Provided is an epitaxial substrate for a back-illuminated image sensor and a manufacturing method thereof that is capable of suppressing metal contaminations and reducing occurrence of a white spot defect of the image sensor, by maintaining a sufficient gettering performance in a device process. The present invention includes forming a gettering sink immediately below a surface of a high-oxygen silicon substrate, forming a first epitaxial layer on the surface of the high-oxygen silicon substrate, and forming a second epitaxial layer on the first epitaxial layer, in which the step of forming the gettering sink includes forming an oxygen precipitate region by applying a long-time heat treatment at a temperature of 650-1150° C. to the high-oxygen silicon substrate.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 3, 2011
    Applicant: SUMCO CORPORATION
    Inventor: Kazunari Kurita
  • Publication number: 20110053305
    Abstract: Producing a solid-state imaging device by (1) forming a structure including (a) a substrate having a first impurity with a first concentration, (b) a first conductive type Si layer and (c) a first conductive type impurity layer stacked on one another in that order, the first conductive type Si layer being formed on the substrate, the first conductive type impurity layer being formed in a boundary region including a boundary of the substrate and the Si layer, and a part of the substrate facing the boundary and a part of the first conductive type Si layer facing the boundary having a second impurity; and (2) forming in the Si layer a second conductive type region capable of storing in the Si layer a charge generated by a photoelectric conversion; and forming an interconnection layer on the Si layer.
    Type: Application
    Filed: November 10, 2010
    Publication date: March 3, 2011
    Applicant: SONY CORPORATION
    Inventor: Hideo Kanbe
  • Patent number: 7882482
    Abstract: A layout method that enables a high power switch mode voltage regulator integrated circuit to generate a large output current and achieve substantially low switching loss is disclosed. The layout method includes forming an array of switching elements on a semiconductor die, each switching element including a plurality of discrete transistors configured to have a substantially reduced ON resistance; and forming a plurality of gate driver circuits on the same die among the switching elements, all using a single metal process. Each gate driver circuit placed substantially close to and dedicated to drive only one switching element so that the gate coupling capacitance resistance product is substantially reduced.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: February 1, 2011
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Paul Ueunten
  • Patent number: 7863075
    Abstract: A manufacturing method of a polycrystalline solar cell is disclosed. A polycrystalline silicon solar cell in accordance with the present invention performs crystallization-annealing amorphous silicon with a metal catalyst so as to reduce a crystallization temperature. The manufacturing method of a solar cell in accordance with the present invention includes the steps of (a) forming a first amorphous silicon layer on a substrate; (b) forming a second amorphous silicon layer on the first amorphous silicon layer; (c) forming a metal layer on the second amorphous silicon layer; (d) performing crystallization-annealing the second amorphous silicon layer; and (e) forming a third amorphous silicon layer on a resulting crystalline silicon layer of the step (d).
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: January 4, 2011
    Assignee: TG Solar Corporation
    Inventors: Taek Yong Jang, Byung Il Lee
  • Publication number: 20100308262
    Abstract: The present invention refers to a composite getter for thin-film photovoltaic panels which is made with a polymer having low H2O transmission containing one or more alkaline earth metal oxide, to a photovoltaic panel containing such a composite getter and to a method for the manufacturing of photovoltaic panels.
    Type: Application
    Filed: September 24, 2008
    Publication date: December 9, 2010
    Inventors: Sergio Rondena, Antonio Bonucci, Giorgio Longoni, Luca Toia, Marco Amiotti
  • Publication number: 20100311199
    Abstract: A method of producing an epitaxial substrate for a solid-state imaging device, comprising: forming a gettering sink by injecting laser beam to a semiconductor substrate through one surface thereof, condensing the laser beam to an arbitrarily selected portion of the semiconductor substrate, thereby causing multi-photon absorption process to occur in the portion, and forming a gettering sink having a modified crystal structure; and epitaxially growing at least two epitaxial layers on the semiconductor substrate in which the gettering sink is formed.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 9, 2010
    Applicant: SUMCO CORPORATION
    Inventor: Kazunari KURITA
  • Publication number: 20100267184
    Abstract: Method of manufacturing image sensors having a plurality of gettering regions. In the method, a gate electrode may be formed on a semiconductor substrate. A source/drain region may be formed in the semiconductor substrate to be overlapped with the gate electrode. A gettering region may be formed in the semiconductor substrate to be adjacent to the source/drain region.
    Type: Application
    Filed: April 19, 2010
    Publication date: October 21, 2010
    Inventor: Hyun-Pil Noh
  • Publication number: 20100261302
    Abstract: A method and apparatus for cleaning layers of solar cell substrates is disclosed. The substrate is exposed to a reactive gas that may comprise neutral radicals comprising nitrogen and fluorine, or that may comprise anhydrous HF and water, alcohol, or a mixture of water and alcohol. The reactive gas may further comprise a carrier gas. The reactive gas etches the solar cell substrate surface, removing oxygen and other impurities. When exposed to the neutral radicals, the substrate grows a thin film containing ammonium hexafluorosilicate, which is subsequently removed by heat treatment.
    Type: Application
    Filed: June 28, 2010
    Publication date: October 14, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: VIRENDRA V. S. RANA, Michael P. Stewart
  • Patent number: 7808091
    Abstract: The specification teaches a system for manufacturing microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In an embodiment, a system for manufacturing the devices includes efficiently integrating a getter material in multiple microdevices.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: October 5, 2010
    Assignee: SAES Getters S.p.A.
    Inventor: Marco Amiotti
  • Publication number: 20100240165
    Abstract: A manufacturing method of a polycrystalline solar cell is disclosed. A polycrystalline silicon solar cell in accordance with the present invention performs crystallization-annealing amorphous silicon with a metal catalyst so as to reduce a crystallization temperature. The manufacturing method of a solar cell in accordance with the present invention includes the steps of (a) forming a first amorphous silicon layer on a substrate; (b) forming a second amorphous silicon layer on the first amorphous silicon layer; (c) forming a metal layer on the second amorphous silicon layer; (d) performing crystallization-annealing the second amorphous silicon layer; and (e) forming a third amorphous silicon layer on a resulting crystalline silicon layer of the step (d).
    Type: Application
    Filed: October 29, 2008
    Publication date: September 23, 2010
    Applicant: TG SOLAR CORPORATION
    Inventors: Taek Yong Jang, Byung Il Lee
  • Patent number: 7795065
    Abstract: Provided is an image sensor. The image sensor can include a first substrate comprising a pixel portion in which a readout circuitry is provided and a peripheral portion in which a peripheral circuitry is provided. An interlayer dielectric including lines can be formed on the first substrate to connect with the readout circuitry and the peripheral circuitry. A crystalline semiconductor layer can be provided on a portion of the interlayer dielectric corresponding to the pixel portion through a bonding process. The crystalline semiconductor layer can include a first photodiode and second photodiode. The first and second photodiodes can be defined by device isolation trenches in the crystalline semiconductor layer. A device isolation layer can be formed on the crystalline semiconductor layer comprising the device isolation trenches. An upper electrode layer passes through the device isolation layer to connect with a portion of the first photodiode.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: September 14, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Joon Hwang
  • Patent number: 7794798
    Abstract: A method for depositing material on a substrate is described. The method comprises maintaining a reduced-pressure environment around a substrate holder for holding a substrate having a surface, and holding the substrate securely within the reduced-pressure environment. Additionally, the method comprises providing to the reduced-pressure environment a gas cluster ion beam (GCIB) from a pressurized gas mixture, accelerating the GCIB, and irradiating the accelerated GCIB onto at least a portion of the surface of the substrate to form a thin film. In one embodiment, the pressurized gas mixture comprises a silicon-containing specie and at least one of a nitrogen-containing specie or a carbon-containing specie for forming a thin film containing silicon and at least one of nitrogen or carbon. In another embodiment, the gas mixture comprises a metal-containing specie for forming a thin metal-containing film.
    Type: Grant
    Filed: September 29, 2007
    Date of Patent: September 14, 2010
    Assignee: TEL Epion Inc.
    Inventor: John J. Hautala
  • Publication number: 20100216274
    Abstract: A method for making a tandem solar cell includes the steps of providing a ceramic substrate, providing a titanium-based layer on the ceramic substrate, providing an n+-p?-p+ laminate on the titanium-based layer, passivating the n+-p?-p+ laminate, providing an n-i-p laminate on the n+-p?-p+ laminate, providing a p-type ohmic contact, providing an n-type ohmic contact providing an anti-reflection layer of SiCN/SiO2 on the n-i-p laminate.
    Type: Application
    Filed: October 31, 2007
    Publication date: August 26, 2010
    Applicant: ATOMIC ENERGY COUNCIL - INSTITUTE OF NUCLEAR ENERGY RESEARCH
    Inventors: Tsun-Neng Yang, Lan Shan-Ming, Chiang Chin-Chen, Ma Wei-Yang, Ku Chien-Te, Huang Yu-Hsiang
  • Publication number: 20100201854
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Application
    Filed: January 28, 2010
    Publication date: August 12, 2010
    Applicant: SONY CORPORATION
    Inventor: Shin Iwabuchi
  • Patent number: 7767506
    Abstract: An exposure mask is provided, which includes: a light blocking opaque area blocking incident light; a translucent area; and a transparent area passing the most of incident light, wherein the translucent area generates the phase differences in the range of about ?70° to about +70°.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: August 3, 2010
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Jong-An Kim, Ji-Haeng Han, Young-Bae Jung, Bae-Hyoun Jung
  • Publication number: 20100186803
    Abstract: The present invention relates to methods and apparatuses for providing a buried insulator isolation for solar cell contacts. According to certain aspects, the invention places a buried oxide under the emitter of a polysilicon emitter solar cell. The oxide provides an excellent passivation layer over most of the surface. Holes in the oxide provide contact areas, increasing the current density to enhance efficiency. The oxide isolates the contacts from the substrate, achieving the advantage of a selective emitter structure without requiring deep diffusions. The oxide further enables use of screen printing on advanced shallow emitter cells. Positioning of the grid lines close to the openings also enables use of a very thin emitter to maximize blue response.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 29, 2010
    Inventors: PETER BORDEN, Li Xu
  • Patent number: 7763500
    Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: July 27, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Takashi Arao, Kenichi Koyanagi, Kenji Komeda, Naruhiko Nakanishi, Hideki Gomi
  • Patent number: 7759218
    Abstract: A method for providing improved gettering in a vacuum encapsulated device is described. The method includes forming a plurality of small indentation features in a device cavity formed in a lid wafer. The gettering material is then deposited over the indentation features. The indentation features increase the surface area of the getter material, thereby increasing the volume of gas that the getter material can absorb. This may improve the vacuum maintained within the vacuum cavity over the lifetime of the vacuum encapsulated device.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: July 20, 2010
    Assignee: Innovative Micro Technology
    Inventor: Jeffery F. Summers
  • Patent number: 7754518
    Abstract: A method and apparatus for thermally processing a substrate is provided. A substrate is disposed within a processing chamber configured for thermal processing by directing electromagnetic energy toward a surface of the substrate. An energy blocker is provided to block at least a portion of the energy directed toward the substrate. The blocker prevents damage to the substrate from thermal stresses as the incident energy approaches an edge of the substrate.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: July 13, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Blake Koelmel, Robert C. McIntosh, David D L Larmagnac, Alexander N. Lerner, Abhilash J. Mayur, Joseph Yudovsky