Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).

Abstract: By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low resistance can be produced, and a highly reliable semiconductor device can be produces as well.

Abstract: A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N+type source layer 11 and the height gap h2 between the gate electrode 10 and the N+type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.

Abstract: In accordance with the invention there is provided a semiconductor capacitor having a first semiconductor layer which forms a first capacitor electrode and which includes silicon, a second capacitor electrode and a capacitor dielectric including praseodymium oxide between the capacitor electrodes, in which provided between the capacitor dielectric including praseodymium oxide and at least the first semiconductor layer including silicon is a first thin intermediate layer representing a diffusion barrier for oxygen. In particular the thin intermediate layer can include oxynitride.

Abstract: A method of forming a salicide pattern for measuring junction leakage current is disclosed. An example method forms device isolation structures on a silicon substrate, forms a well region between the device isolation structures, forms source and drain regions on the well region, and forms a salicide layer on the source and drain regions. The example method also removes some part of the salicide layer, deposits an interlayer dielectric layer on the salicide layer, and forms via holes in the interlayer dielectric layer and filling metal into the via holes to form a via. The example method further planarizes the interlayer dielectric layer and the via, and forms metal interconnects on the interlayer dielectric layer.

Abstract: A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

Abstract: In accordance with the invention the semiconductor capacitor includes a first capacitor electrode 1, a second capacitor electrode 3 and a capacitor dielectric 5 which is arranged between the two capacitor electrodes and which includes praseodymium oxide. It is distinguished in that the second capacitor electrode 3 includes praseodymium silicide.

Abstract: A schottky barrier transistor and a method of manufacturing the same are provided. The method includes forming a gate insulating layer and a gate on a substrate, forming a spacer on a sidewall of the gate, and growing a polycrystalline silicon layer and a monocrystalline silicon layer on the gate and the substrate, respectively, using a selective silicon growth. A metal is deposited on the polycrystalline silicon layer and the monocrystalline silicon layer. Then, the metal reacts with silicon of the polycrystalline silicon layer and the monocyrstalline silicon layer to form a self-aligned metal silicide layer. Therefore, selective wet etching for removing an unreacted metal after silicidation can be omitted. Furthermore, etching damage caused during the formation of the spacer can be decreased during the growth of the monocrystalline silicon layer, thereby improving the electrical characteristics of devices.

Abstract: A cobalt silicide fabrication process entails first depositing a cobalt layer (120) on a silicon-containing EPROM region. A titanium layer (130) is formed over the cobalt layer by ionized physical vapor deposition (“IPVD”) to protect the cobalt layer from contaminant gases. Cobalt of the cobalt layer is reacted with silicon of the EPROM region to form a cobalt silicide layer (210) after which the titanium layer and any unreacted cobalt are removed. Use of IPVD to form the titanium layer by improves the step coverage to produce a better cobalt silicide layer.

Abstract: A diffusion layer 3a of a silicon substrate, a polycrystalline silicon material 10, or a gate electrode 12 is connected to a conductive film 8 through a titanium silicide film 6 within a contact hole 5 provided in an insulating film 4. The titanium silicide film 6 is formed by the silicide reaction between a titanium film 7 and the silicon. The upper limit of the thickness of the titanium silicide film 6, and the upper limit of the titanium film 7 are specified by the internal stress within the conductive film 8.

Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.

Abstract: A cobalt-containing film on a silicon-containing conductive region, and a titanium-rich capping layer is formed on cobalt-containing film. The atomic % ratio of titanium to other elements (if any) in the titanium-rich capping layer is more than one (1). The resultant structure is annealed so that cobalt of the cobalt-containing film and silicon of the silicon-containing conductive region react with each other to form a cobalt silicide film. When the formation of the cobalt-containing film is carried out at a high temperature, a diffusion restraint interface film is also formed.

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of depositing a first insulating film over a first conductive layer, patterning the first insulating film by using a resist film as a mask to form a cap film, and removing the resist film. After which, a gate electrode of a MISFET is formed by etching the first conductive layer using the cap film as a mask. A second insulating film is deposited over the gate electrode and the cap film and a side wall spacer formed on side surfaces of the gate electrode by etching the second insulating film. After which, a salicide layer is selectively formed on the gate electrode. The cap film is removed by over-etching the first insulating film to etch the cap film.

Abstract: A semiconductor substrate has a memory region and a logic region isolated by an isolation insulating film. Plural memory transistors are provided in the form of a matrix in the memory region, and a logic transistor is provided in the logic region. Gate electrodes of memory transistors arranged along the word line direction out of the plural memory transistors are formed as a common gate electrode extending along the word line direction, and impurity diffusion layers working as source/drain regions of memory transistors arranged along the bit line direction are formed as a common impurity diffusion layer extending along the bit line direction. An inter-gate insulating film having its top face at a lower level than the gate electrodes is formed on the semiconductor substrate between the gate electrodes of the plural memory transistors. A sidewall insulating film is formed on the side face of a gate electrode of the logic transistor.

Abstract: A method of manufacturing a semiconductor device with a transistor comprising an LDD region and a silicide layer is disclosed. The method may include forming a gate electrode on a substrate, forming a first preliminary source/drain region with shallow junction through an ion implantation process using the gate electrode as a mask, and forming a ILD pattern with contact holes on the substrate including the gate electrode, the contact holes exposing the top of the gate electrode and some part of the first preliminary source/drain region. The method may also include forming an expanded source/drain region through an ion implantation process using the ILD pattern as a mask, forming a silicide layer on the top of the gate electrode and the expanded source/drain region, and forming contact plugs by filling the contact holes with metal.

Abstract: A fabrication process for a Schottky barrier structure includes forming a nitride layer directly on a surface of an epitaxial (“epi”) layer and subsequently forming a plurality of trenches in the epi layer. The interior walls of the trenches are then deposited with a final oxide layer without forming a sacrificial oxide layer to avoid formation of a beak bird at the tops of the interior trench walls. A termination trench is etched in the same process step for forming the plurality of trenches in the active area.

Abstract: A Schottky diode is adjusted by implanting an implant species by way of a titanium silicide Schottky contact and driving the implant species into the underlying silicon substrate by a rapid anneal. The implant is at a low energy, (e.g. about 10 keV) and at a low dose (e.g. less than about 9E12 atoms per cm2) such that the barrier height is slightly increased and the leakage current reduced without forming pn junction and retaining the peak boron concentration in the titanium silicide layer.

Abstract: In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.

Abstract: A process for manufacturing an integrated device comprises the steps of: forming, in a first wafer of semiconductor material, integrated structures including semiconductor regions and isolation regions; forming, on a second wafer of semiconductor material, interconnection structures of a metal material including plug elements having at least one bonding region of a metal material capable of reacting with the semiconductor regions of the first wafer; and bonding the first and second wafers together by causing the bonding regions of the plug elements to react directly with the semiconductor regions so as to form a metal silicide. Thereby, the metallurgical operations for forming the interconnection structures are completely independent of the operations required for processing silicon, so that there is no interference whatsoever between the two sets of operations.

Abstract: Methods of forming an electrically conductive line include providing a stress inducing material within or a compressive stress inducing layer operatively adjacent a crystalline material of a first crystalline phase. In addition, such methods include annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. Some methods also include providing stress inducing materials into a refractory metal layer. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials include Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.

Abstract: Gate wiring is formed serving as first gate wiring in a DRAM-forming area, and gate wiring 33 is formed as second gate wiring in a logic-forming area. Then, cobalt silicide layer 37 is formed over a source/drain diffused layer in the DRAM-forming area, and cobalt silicide layer is formed over a source/drain diffused layer and the gate wiring in the logic-forming area. Such formation of the cobalt silicide layer reduces the resistance of the gate wiring and the contact resistance, and thereby enables the high-speed operation of a semiconductor device even if the device is microfabricated.

Abstract: A Schottky diode structure and a method of making the same are disclosed. The method comprises following steps: firstly, a semiconductor substrate having a first conductive layer and an epi-layer doped with the same type impurities is provided. Then a first oxide layer is form on the epi layer. A patterning step to pattern first oxide layer and recess the epi layer (optional) is then followed to define guard rings. After stripping the photoresist pattern, a polycrystalline silicon layer formation is then followed. A boron and/or BF2+ ion implant is then performed. Subsequently, a high temperature drive in process and oxidation process to oxidize the polycrystalline silicon layer and drive ions is then carried out. A second mask and etch steps are then performed to open the active regions. A metallization process is then done. A third mask and etch steps are then implemented to define anode. Finally, a backside metal layer is then formed and serves as a cathode.

Abstract: A three-terminal semiconductor transistor device comprises a base region formed by a semiconductor material of a first conductivity type at a first concentration, the base region being in contact with a first electrical terminal via a semiconductor material of the second conductivity type at a second concentration, wherein the second concentration is lower than the first concentration. The three-terminal semiconductor transistor device also includes a conductive emitter region in contact with the semiconductor base region, forming a first Schottky barrier junction at the interface of the conductive emitter region and the semiconductor base region. The conductive emitter region is in contact with a second electrical terminal. The three-terminal semiconductor transistor device further includes a conductive collector region in contact with the semiconductor base region, which forms a second Schottky barrier junction at the interface of the conductive collector region and the semiconductor base region.

Abstract: A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

Abstract: A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.

Abstract: A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

Abstract: A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.

Abstract: Before deposition of a CVD titanium film on a cobalt silicide layer, an element which reacts with titanium is provided in the cobalt silicide layer in advance. Thereafter, the CVD titanium film is deposited on the cobalt silicide using a titanium tetrachloride gas.

Abstract: A method of ensuring against deterioration of an underlying silicide layer over which a refractory material layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is realized by first providing a continuous polysilicon layer prior to the refractory material deposition. The continuous polysilicon layer, preferably no thicker than 50 Å, serves a sacrificial purpose and prevents interaction between any fluorine that is released during the refractory material deposition step from interacting with the underlying silicide.

Abstract: A cobalt-containing film on a silicon-containing conductive region, and a titanium-rich capping layer is formed on cobalt-containing film. The atomic % ratio of titanium to other elements (if any) in the titanium-rich capping layer is more than one (1). The resultant structure is annealed so that cobalt of the cobalt-containing film and silicon of the silicon-containing conductive region react with each other to form a cobalt silicide film. When the formation of the cobalt-containing film is carried out at a high temperature, a diffusion restraint interface film is also formed.

Abstract: Direct focused ion beam (FIB) mixing is given as a method for patterning of metal silicide structures on a silicon surface. This technique allows the fabrication of submicron structures without the use of resist-based lithography methods. VLSI containing metal silicide connects, interconnects and structures may be prepared by the method. Fast semiconductor devices having good circuit speed and reduced RC time delay including the technologies MEMS, MOSFET, CMOS, pMOS, nMOS and BiCMOS result.

Abstract: A method for forming a metal salicide layer on a shallow junction is described. A substrate having a gate structure thereon and a shallow junction therein is provided. An atomic layer deposition (ALD) process is then performed to deposit a tungsten salicide layer on the shallow junction. In the ALD process, a gaseous silicon-containing compound and a gaseous metal-containing compound that react into metal silicide are introduced alternatively onto the substrate, wherein either compound can be introduced at first. When either compound is introduced at first, the flow rate thereof is controlled so that only a single layer of molecules are adsorbed, while the flow rate of the metal-containing compound is controlled in each case so that few silicon atoms in the substrate are consumed. By repeating the two gas introduction steps, a metal salicide layer constituted of many thin layers is formed on the shallow junction.

Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.

Abstract: Method for forming a Schottky contact in a semiconductor device includes a step of preparing an n type GaN group compound semiconductor layer, such as AlxGa1-xN and InxGa1-xN. At least one metal layer including a ruthenium component layer is formed on the n type GaN group compound semiconductor layer as a rectifying junction metal. The rectifying junction metal may be used as a gate of a field effect transistor, or an electrode of a Schottky diode. The ruthenium oxide has a low cost, is stable to heat and chemical, and has excellent electric characteristics. The application of the ruthenium oxide to the rectifying junction metal enhances performances, such as UV ray detection, of electronic devices and optical devices operable at an elevated temperature.

Abstract: A vertical bipolar transistor includes a semiconductor substrate, an extrinsic collector layer in the semiconductor substrate, an intrinsic collector on the extrinsic collector, a lateral isolating region surrounding an upper part of the intrinsic collector, an offset extrinsic collector well, a base including a semiconductor region above the intrinsic collector and above the lateral isolating region including at least one silicon layer, and a doped emitter surrounded by the base. The doped emitter may include first and second parts. The first part may be formed from single-crystal silicon and in direct contact with the upper surface of the semiconductor region in a predetermined window in the upper surface above the intrinsic collector. The second part may be formed from polycrystalline silicon. The two parts of the emitter may be separated by a separating oxide layer spaced apart from the emitter-base junction of the transistor.

Abstract: A semiconductor device and method for fabricating the same which improves reliability of the semiconductor device is disclosed. The semiconductor device includes: a first insulating film and a gate electrode sequentially formed on a part of a semiconductor substrate; a first insulating spacer formed at both sides above the gate electrode; a second insulating spacer formed at both sides below the gate electrode; and a cobalt silicide film formed on a surface of the gate electrode at a predetermined depth.

Abstract: Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.

Abstract: A semiconductor device with low contact resistance which can cope with the miniaturization of semiconductor devices as well as a manufacturing method thereof which is easy and inexpensive can be obtained. Impurity regions on an Si substrate, an interlayer insulation film, source and drain interconnections, a metal silicide layer larger in diameter than the lower edge of the contact holes around the impurity regions are provided and the metal silicide layer includes an interface making up a border between the upper metal silicide layer contacting with the bottom of the interlayer insulation film and the lower metal silicide layer contacting with the impurity region surface. Thus, the contact area between the source and drain lines and the impurity regions can be increased via the metal silicide layer so as to reduce the contact resistance.

Abstract: A first metal film of a first metal is deposited on a silicon-containing film containing silicon as a principal constituent, and a second metal film of a nitride of a second metal is deposited on the first metal film. Thereafter, a metal film with a high melting point is deposited on the second metal film, so as to form a multi-layer film of the silicon-containing film, the first metal film, the second metal film and the metal film with a high melting point. The multi-layer film is then subjected to annealing at a temperature of 750° C. or more. In this case, the first metal is nitrided to be changed into a nitride of the first metal and a silicide layer of the first metal is not formed in a surface portion of the silicon-containing film before the annealing.

Abstract: A method is provided, the method comprising forming a buffer layer above a structure layer, and forming a dielectric layer above the buffer layer. The method also comprises patterning the dielectric layer to form a salicide block above a portion of the structure layer protecting the portion from a subsequent salicidation. A device is also provided, the device comprising a buffer layer above a structure layer and a dielectric layer above the buffer layer. The dielectric layer is patterned to form a salicide block above a portion of the structure layer to protect the portion from a subsequent salicidation.

Abstract: A semiconductor memory has a buried bit line structure. One end of the bit line and one end of the diffused impurity layer are connected by being overlapped with each other, and the surface of the source/drain of the selection transistor and the surface of the diffused impurity layer including the connecting portion are silicidized by using metals having high melting points, Ti and Si in this case, thereby forming the titanium silicide layer thereon. This invention not only solves the various problems arising from the buried bit line structure but also realizes sure formation of the silicide, low resistance, greater fineness and high speed operation.

Abstract: Embodiments of the present invention generally relate to processes of making an improved salicide-gate. One embodiment of a method for forming a feature on a substrate comprises forming a gate structure on a substrate; forming spacers by the sidewalls of the gate; and depositing a relatively thin metal film, such as cobalt or titanium, over the gate at a high temperature.

Abstract: Techniques for forming gate dielectric layers (702) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions (604, 606) are formed prior to formation of structures included in the gate structure (804) of the semiconductor device, where the gate structures (804) are preferably formed using low temperature operations that allow the amorphous silicon regions (604, 606) to remain in an amorphous state. Source/drain regions (1004, 1006) are formed in the amorphous silicon regions (604, 606), and then the substrate is annealed to recrystallize the amorphous regions.

Abstract: By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low resistance can be produced, and a highly reliable semiconductor device can be produces as well.

Abstract: The present invention discloses a thin film transistor with sub-gates and Schottky source/drain and a method of manufacturing the same. Doping of source/drain, and the following annealing steps used conventionally are omitted and the complexity of process and process costs are reduced. The temperature of the process is also decreased. A thin film transistor with sub-gates and Schottky source/drain of the invention is able to operate in both the n type and p type channel modes on the same transistor element depending on the biased voltage of the sub-gate. Moreover, an electric junction is formed by induction, using bias voltage applied on the sub-gate, which takes the place of the conventional source/drain extensions. Consequently, the off-state leakage current is reduced.

Abstract: An electrical contact for a silicon carbide component comprises a material that is in thermodynamic equilibrium with silicon carbide. The electrical contact is typically formed of Ti3SiC2 that is deposited on the silicon carbide component.

Abstract: A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the surface of the channel region and forms a Schottky diode with the semiconductor substrate, and a ferroelectric layer and a gate electrode are disposed on its surface. The ferroelectric transistor is fabricated using steps appertaining to silicon process technology.

Abstract: A semiconductor device with dual gate electrodes and its method of formation is taught. A first metal/silicon gate stack and a first gate dielectric are formed over a first doped region. The metal/gate stack comprises a metal portion over the first gate dielectric and a first gate portion over the metal portion. A silicon gate and a second gate dielectric are formed over the second doped region. In one embodiment, the first and second gate portions are P+ doped silicon germanium and the metal portion is TaSiN. In another embodiment, the first and second gate portions are N+ doped polysilicon and the metal portion is TaSiN.

Abstract: A method for making a gate in an integrated circuit. A gate layer is formed on a substrate, and a blocking layer is formed on the gate layer. The blocking layer is masked with a photoresist layer, and the photoresist layer is developed to define an exposed gate area. The blocking layer is etched in the gate area to expose the gate layer in the gate area, and the photoresist layer is removed. A metal layer is formed on the blocking layer and on the gate layer in the gate area. The metal layer is selectively reacted with the gate layer in the gate area to form a hard mask over the gate layer in the gate area. The metal layer is removed from the blocking layer. The blocking layer is selectively etched without substantially etching the hard mask in the gate area, to expose the gate layer surrounding the gate area. The exposed gate layer is etched to define a gate in the gate area. The hard mask remains on the gate, and functions as an electrical contact to the gate.