Abstract: Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.

Abstract: A method for fabricating a Schottky diode using a shallow trench contact to reduce leakage current in the fabrication of an integrated circuit device is described. The method provides a simple and effective method for decreasing the possibility of forming a bad Schottky diode.

Abstract: A gate electrode rectangular in section is formed by patterning on a GaAs substrate as a compound substrate having a channel layer. Subsequently, a specific metal, e.g., Ti is deposited. A solid-phase reaction layer to serve as source/drain is formed in a self-alignment manner with the gate electrode by a thermal treatment. The part of the Ti film which has not been reacted is then removed. Thus the source/drain (or at least one of them) are very easily formed to a shallow junction depth without using any ion implantation process. Realized is a semiconductor device showing an excellent device characteristics, capable of suppressing occurrence of short-channel effect even in its shortened gate length for reducing the device size.

Abstract: A method for producing a Schottky diode formed of a doped guard ring in an edge area of the Schottky contact is described. The guard ring is produced by depositing a high barrier material, especially made of platinum, on the surface of the semiconductor layer. The surface is provided with a structured masking layer beforehand, and which is subsequently etch-backing.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Abstract: A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

Abstract: A method to enhance the formation of nucleation sites on at least one narrow silicon structure comprises the step: forming at least one nucleation region (206/208): masking the at least one narrow silicon structure (202) with a mask (302); treating the at least one nucleation region (206/208) to enhance an ability of said region to form C54 nucleation sites; and removing the mask from the at least one narrow silicon structure (202).

Abstract: A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is formed by a plasma CVD process with a reduced plasma power such that the H2O content in the oxide film is less than about 2.4 wt %.

Abstract: Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.

Abstract: Methods are provided that selectively provide various contact resistances based on each individual transistor's influence on an overall chip speed during the formation of active regions and silicide layers. In order to provide lower contact resistance to devices which have a critical influence on overall device speed, the active regions of such critical devices are formed with a lower impurity concentration and thicker silicide layers are provided on the active regions. Likewise, for the normal devices which have less or no influence on overall chip speed, thinner silicide layers are provided on the active regions having a higher impurity concentration than the critical devices.

Abstract: A method for forming a thermally stable cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the silicon regions to be silicided. A capping layer is deposited overlying the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. A titanium layer is deposited overlying the cobalt monosilicide layer. Thereafter the substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide. The titanium layer provides titanium atoms which diffuse into the cobalt disilicide thereby increasing its thermal stability.

Abstract: A method for making a flexible metal silicide local interconnect structure. The method includes forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon layer, removing a portion of the silicon nitride layer, oxidizing the exposed portion of the silicon layer, removing the remaining portion of the silicon nitride layer, optionally removing the oxidized silicon layer, forming a metal layer over the resulting structure, annealing the metal layer in an atmosphere comprising nitrogen, and removing any metal nitride regions. The local metal silicide interconnect structure may overlie the at least one gate structure. The methods better protect underlying silicon regions (e.g., substrate), as well as form TiSix local interconnects with good step coverage. Intermediate and resulting structures are also disclosed.

Abstract: A method for manufacturing a miniaturized semiconductor device having a conductive portion with a silicide structure. The manufacturing method includes depositing metal on the surface of a patterned semiconductor film to form the conductive portion, heat treating the semiconductor film on which the metal is deposited, removing the residual metal that did not react during the heat treatment, and repeating the depositing step, the heat treating step, and the removing step once or a number of times.

Abstract: Self-aligning photolithography method and a method of fabricating a semiconductor device using the same, in which the photolithography method is performed using a lower pattern without employing a separate mask. The self-aligning photolithography method includes the steps of forming a lower pattern layer on a semiconductor substrate, depositing a photoresist, and subjecting to exposure without a photomask such that the photoresist aligned with the lower pattern layer is not to be exposed by diffraction of light, and either removing or leaving only the photoresist aligned with the lower pattern layer by development.

Abstract: A process of forming a metal silicide layer, on a source/drain region of a MOSFET device, featuring ion implanted metal ions providing the metal component of the metal silicide layer, has been developed. After formation of a heavily doped source/drain region, in an area of a semiconductor region not covered by a insulator capped, gate structure, or by insulator spacers on the sides of the insulator capped gate structure, metal ions are implanted into the top surface of the heavily doped source/drain region. The metal ions are chosen from a group that includes titanium, tantalum, platinum, palladium, nickel and cobalt ions. An anneal procedure is then employed resulting in the formation of the metal silicide layer on the heavily doped source/drain region. Selective removal of unreacted metal ions is then accomplished via use wet etchant solutions.

Abstract: A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; forming nickel silicide layers disposed on the source/drain regions and the gate electrode, and two etching steps. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The first etch is performed with a sulfuric peroxide mix to remove unreacted nickel, and the second etch is performed with an ammonia peroxide mix to remove nickel silicide formed over the first and second sidewall spacers.

Abstract: A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and forming a first dielectric spacer adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD region. The method also includes introducing a dopant into a source/drain region of the structure and removing a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD region, and the first dielectric spacer. In addition, the method includes forming a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD region, and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

Abstract: A method for fabricating a semiconductor substrate includes forming a suicide layer at a predetermined portion of a semiconductor substrate, implanting two or more impurity ions before annealing, and forming an impurity region in the semiconductor substrate by annealing the silicide layer and by diffusing the impurity ions from the silicide layer into the semiconductor substrate. Accordingly, the present invention can improve reliability and performance of a semiconductor device by reducing dopant loss and leakage current of a PN junction in the substrate and by decreasing a sheet resistance of the silicide layer. The dose of the second implanter ions is about one hundred to one thousand times less than the dose of the first implanted ions.

Abstract: In producing a thin film transistor used for such devices as a large-sized liquid crystal display panel with a high pixel density, a leftover of an insulating film caused by insufficient etching and a loss of a semiconductor layer caused by overetching are prevented, and a reliable electrical contact between the source and drain electrodes and the semiconductor layer is achieved. These are achieved by (a) forming a contact hole region of a silicon film so that the region has a larger thickness, for example, by making the film to have a plurality of layers, and (b) providing a silicide layer between an electrode metal and the semiconductor layer.

Abstract: A method for manufacturing a salicide transistor, a semiconductor storage, and a semiconductor device that can solve both an increase in narrow-line resistance and an increase in P-N-junction leakage, and can give an optimized process as the total LSI device manufacturing process flow. After adding an impurity in the high-concentration source/drain region on a semiconductor substrate, a heat treatment is performed at a first temperature, then a heat treatment is performed for forming salicide at a second temperature higher than a predetermined temperature and lower than the first temperature for a first period of time, an interlayer insulating film is formed, and heat treatment is performed at a third temperature higher than the second temperature and lower than the first temperature. Since the crystallinity of the implanted layer 109 has been recovered before forming the silicide protecting film, salicide can be formed under the conditions where the crystallinity of the diffusion layer is good.

Abstract: The present invention Is a fabrication method for a short-channel Schottky-barrier field-effect transistor device. The method of the present invention includes introducing channel dopants into a semiconductor substrate such that the dopant concentration varies in the vertical direction and is generally constant in the lateral direction. A gate electrode is formed on the semiconductor substrate, and source and drain electrodes are formed on the substrate to form a Schottky or Schottky-like contact to the substrate.

Abstract: A method of forming an electrically conductive plug in an opening in a dielectric layer of a substrate. A layer of silicon is deposited on the walls of an opening. In one aspect, the opening is filled by depositing electrically conductive material directly over the silicon. In another aspect, the layer of silicon is exposed to a precursor gas that reacts with the silicon so as to (a) form a volatile material that consumes substantially all of the silicon and (b) deposit an electrically conductive material within the opening.

Abstract: A multiple step chemical vapor deposition process for depositing a tungsten silicide layer on a substrate. A first step of the deposition process includes a pretreatment step in which WF6 is introduced into a deposition chamber. Next, the introduction of WF6 is stopped and a silicon-containing gas, e.g., SiH4, is introduced into the chamber. Finally, during a third step, the SiH4 flow is stopped and DCS and WF6 are introduced into the chamber to deposit a tungsten silicide layer on the substrate.

Abstract: A schottky diode is formed of a sintered barrier metal layer which contacts a lightly doped silicon surface. The barrier metal layer is formed of palladium as well as a small quantity of another metal whose choice is determined by the desired value of the barrier height of the resulting schottky diode. A small quantity of platinum is selected to increase the barrier height, and a small quantity of nickel is selected to decrease the barrier height. A contact metal, which may include a tri-metal layer of titanium, nickel and silver, is formed atop the sintered schottky barrier layer. The resulting process also allows for control of reverse hot leakage current.

Abstract: A method for fabricating a semiconductor device according to the present invention can facilitate the device to be operated at a high speed by restricting an increase of a resistance of a gate electrode. The method for fabricating the semiconductor device includes a step of forming a gate insulation film on a semiconductor substrate, a step of forming a conductive film on the gate insulation film, a step of forming a conductive film post by patterning the conductive film, a step of forming a first silicide layer at sidewalls of the conductive film post, a step of forming a first impurity layer in the semiconductor substrate at both sides of the conductive film post, a step of forming a sidewall spacer beside the first silicide layer formed at the sidewalls of the conductive film post, and a step of forming a second impurity layer in the semiconductor substrate outside the sidewall spacer.

Abstract: A method of fabricating an integrated thin film solar cell includes the steps of: forming a transparent conductive electrode layer and an amorphous semiconductor photoelectric conversion layer successively on a light-transmitting substrate; forming a rear electrode on the amorphous semiconductor photoelectric conversion layer; and patterning the rear electrode layer by applying a beam of a fourth harmonic generation from an Nd-YAG laser onto the rear electrode layer to form a rear electrode.

Abstract: A method of forming a polycide structure in accordance with the present invention includes forming a polysilicon layer on a surface. A refractory metal silicide portion of the polycide structure is formed on the polysilicon layer and the polysilicon portion of the polycide line is formed after formation of the metal siticide portion. The formation of the metal silicide portion of the polycide structure may include forming an oxide hard mask over the polysilicon layer exposing line portions of the polysilicon layer. The exposed line portions of the polysilicon layer are silicided resulting in a refractory metal silicide portion and unreacted material over the oxide hard mask. The unreacted material and oxide hard mask are then removed. The refractory metal silicide portion may be formed by forming a refractory metal or metal silicide layer, such as cobalt or cobalt silicide, over the oxide hard mask and exposed portions of the polysilicon layer.

Abstract: A method for use in the fabrication of semiconductor devices includes forming a layer of nitridated cobalt on a surface including silicon. A film cap including titanium is formed over the layer of cobalt and a thermal treatment is performed to form cobalt silicide from the layer of cobalt and the silicon. Further, a layer of cobalt or nickel may be formed over a titanium film on a surface including silicon. The titanium film is formed in an atmosphere including at least one of nitrogen and oxygen and a thermal treatment is performed for reversal and silicidation of the titanium film and the layer of cobalt or nickel to form cobalt silicide or cobalt nickel. The methods may be used for silicidation of a contact area, in forming a polycide line, or in use for other metal silicidation applications.

Abstract: A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.

Abstract: A method of fabricating a gate having a barrier layer of titanium silicide is comprised of the steps of forming a layer of gate oxide. The gate oxide may be formed using a standard LOCOS process. A layer of doped polysilicon is deposited over the layer of gate oxide. A layer of titanium silicide is formed in a predetermined relationship with respect the layer of doped polysilicon, i.e., it may be deposited on top of the polysilicon or formed in a top surface of the polysilicon layer. A layer of tungsten silicide is deposited on top of the layer of titanium silicide. The layers of gate oxide, doped polysilicon, titanium silicide, and tungsten silicide are etched to form the gate. A gate thus fabricated is also disclosed.

Abstract: An improved method for forming a metal contact for a silicon sensor. First, platinum is deposited over a contact area. Then the platinum is sintered to form platinum silicide. Subsequently, titanium/tungsten (TiW) is deposited over the platinum silicide. Finally, gold is deposited over the TiW.

Abstract: High density, multi-metal layer semiconductor devices are formed with self-aligned vias and reliable interconnection patterns employing photolithography without the use of a photomask. Embodiments include modulating the amount of energy reflected into an overlying photoresist layer from underlying components to effect differential exposure of the photoresist layer.

Abstract: A method of manufacturing a MOS transistor begins with the provision of a semiconductor substrate. A gate oxide layer, a polysilicon layer and a silicon nitride layer are sequentially formed over the substrate. Next, the gate oxide layer, the polysilicon layer and the silicon nitride layer are patterned to form a gate structure. Subsequently, spacers are formed covering the sidewalls of the gate oxide layer, the polysilicon layer and the silicon nitride layer. Thereafter, a dielectric layer is formed, and covers the semiconductor substrate, the silicon nitride layer and the spacers. Next, a planarization operation is carried out to remove a portion of the dielectric layer. Planarization continues until the silicon nitride layer is exposed. After that, the silicon nitride layer is removed, exposing the polysilicon layer, and then a glue layer is formed over the dielectric layer and the polysilicon layer.

Abstract: A method of fabricating an oxidation barrier for a thin film is provided. The method may include forming a thin film (10) outwardly from a semiconductor substrate (12) and separated from the semiconductor substrate (12) by a primary insulator layer (14). A reactive layer (16) may be formed in-situ adjacent to the thin film (10). An oxidation barrier (20) may be formed by a chemical reaction between the thin film (10) and the reactive layer (16). The oxidation barrier (20) may comprise a silicide alloy that operates to reduce oxidation of the thin film (10).

Abstract: The method produces transistor structures with a smaller contact opening, without having to take multiple adjustment allowances into account. Moreover, the method provides two zones of a second conductivity type, which have different dopant concentrations, so that a more gentle transition in the drain doping is obtained. The gentler transition in drain doping effects a lowering in the peak field intensity that can release hot electrons. Thus a degradation of the first insulating layer (gate oxide) caused by hot electrons is prevented.

Abstract: A semiconductor fabrication method for fabricating a flash EEPROM (electrically erasable and programmable read-only memory) device uses STI (shallow-trench isolation) technique to form the field oxide isolation layers so as to make the EEPROM device suitable for fabrication at the submicron level of integration. By this method, the first step is to prepare a semiconductor substrate. Next, a plurality of field oxide isolation layers are formed through the STI technique to define active region in the substrate. After this, at least one gate structure is formed within the active region, which includes a tunnel oxide layer, a first conductive layer serving as a floating gate, a dielectric layer, a second conductive layer serving as a control gate, and a topping layer. Subsequently, an ion-implantation process is performed to form source/drain regions beside the gate structure. A sidewall spacer is then formed on the sidewall of the gate structure.

Abstract: There is provided a semiconductor device including a transistor, said transistor having (a) a semiconductor substrate, (b) source and drain regions formed in the semiconductor substrate, (c) a gate electrode formed on the semiconductor substrate between the source and drain regions, (d) a silicide layer formed partially on one of the source and drain regions, and (e) an electrode terminal making contact with the silicide layer. The silicide layer extends so that it covers at least an area through which the electrode terminal makes contact with the drain region. In the above mentioned semiconductor device, since the silicide layer is formed only in the vicinity of an area through which the electrode terminal makes contact with the silicide layer, it is possible to construct an output transistor in LDD structure. Thus, there can be obtained an output transistor having higher ESD immunity, higher driving ability, and higher integration.

Abstract: Problems with forming silicides on the surfaces of silicon structures using traditional oxide masks are overcome by utilizing a photoresist mask. Metal ions are selectively implanted at high dosage and low energy into unmasked surfaces of the silicon structures, where the metal ions react with the silicon to form the desired layer of metal silicide.

Abstract: A method for reducing the contact resistance of an overlying metal bit line structure, to underlying polycide gate structure, has been developed. A borderless, or non-fully landed contact hole, is opened in an insulator layer, to expose the top surface of the underlying polycide gate structure. The anisotropic, dry etching of the insulator is then continued, resulting in the exposure of a portion of the sides of the polycide gate structure. A subsequent bit line metal structure, now contacts both the top surface, as well as a portion of the sides, of the polycide gate structure, resulting in a contact resistance reduction, due to the increased contact area.