Abstract: In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes an isolation area formed on a semiconductor substrate to define NMOS and PMOS areas, a gate insulating layer and a gate formed on each of the NMOS and PMOS areas, a primary gate spacer formed at sides of the gate, LDD areas formed in the semiconductor substrate at sides of the gate, a secondary gate spacer formed at sides of the primary gate spacer, source and drain areas formed in the semiconductor substrate at sides of the gate of the PMOS area; and source and drain areas formed in the semiconductor substrate at sides of the gate of the NMOS area, wherein the source and drain areas of the NMOS area are deeper than the source and drain areas of the PMOS area.

Abstract: Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD.

Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a substrate including a dummy gate structure formed thereon, removing the dummy gate structure to form a trench, forming a first metal layer over the substrate to fill a portion of the trench, forming a protection layer in a remaining portion of the trench, removing a unprotected portion of the first metal layer, removing the protection layer from the trench, and forming a second metal layer over the substrate to fill the trench.

Abstract: A method of manufacturing a semiconductor device, comprising, forming a first gate electrode in a first region of a semiconductor substrate and forming a second gate electrode in a second region of the semiconductor substrate, forming a first sidewall along a lateral wall of the first gate electrode and forming a second sidewall along a lateral wall of the second gate electrode, forming an oxide film to cover the semiconductor substrate, the first gate electrode, the second gate electrode, the first sidewall and the second sidewall, forming a resist above the oxide film to cover the first region, removing the oxide film in the second region by etching the oxide film with the resist serving as a mask, removing the resist, and executing a plasma process by using a gas containing chlorine with respect to the semiconductor substrate and the oxide film in the first region.

Abstract: A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top.

Abstract: A gate insulating film is formed on a substrate. Next, a gate electrode film is formed on the gate insulating film. A mask film is formed on a portion of the gate electrode film. The gate electrode film is selectively removed by etching using the mask film as a mask. A gate sidewall film is formed so as to be in contact with the lateral surfaces of the mask film and the gate electrode film. The mask film is formed of a laminated film in which at least a first film, a second film and a third film are laminated in this order. The second film has a higher etching selectivity ratio than that of the third film with respect to the gate sidewall film. The third film has a higher etching selectivity ratio than that of the second film with respect to the gate electrode film.

Abstract: Methods of fabricating a semiconductor device are provided, the methods include forming a first dielectric layer, a data storage layer, and a second dielectric layer, which are sequentially stacked, on a semiconductor substrate. A mask having a first opening exposing a first region of the second dielectric layer is formed on the second dielectric layer. A gate electrode filling at least a portion of the first opening is formed. A second opening exposing a second region of the second dielectric layer is formed by etching the mask such that the second region is spaced apart from the first region. A second dielectric pattern and a data storage pattern are formed by sequentially etching the exposed second region of the second dielectric layer and the data storage layer. The second dielectric pattern is formed to have a greater width than a lower surface of the gate electrode.

Abstract: There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.

Abstract: Unintended full siliciding of a polysilicon gate electrode is prevented. The invention provides a method of manufacturing a semiconductor device, the method including: forming a stack structure by stacking a gate insulating film and a silicon layer in this order on a substrate; forming an offset spacer along the side surfaces of the stack structure, the offset spacer including a SiN film; cleaning an exposed region of an upper surface of the silicon layer with a chemical solution after the forming the offset spacer; forming a metal film after the cleaning, the metal film covering at least the exposed region; and performing siliciding through a heating process after the forming the metal film. The SiN film of the offset spacer is a SiN film formed by ALD at 450° C. equal to or higher, or a SiN film having a tensile/compressive stress of 1 Gpa or higher. The chemical solution is DHF having a ratio by weight of 1/100 or higher in HF/H2O or buffered hydrofluoric acid.

Abstract: An embodiment of the disclosure includes a method of forming metal gate structures. A substrate is provided. A first dummy gate electrode and a second dummy gate electrode are formed on the substrate. The first dummy gate electrode comprises first spacers on its sidewalls and the second dummy gate electrode comprises second spacers on its sidewalls. A hardmask layer is formed to covers both the first dummy gate electrode and the second dummy gate electrode. A patterned photoresist layer on the hardmask layer that covers a portion of the hardmask layer over the second dummy gate electrode and that leaves a portion of the hardmask layer over the first dummy gate electrode exposed. The portion of the exposed hardmask layer over the first dummy gate electrode is removed. The first spacers and the first dummy gate electrode is exposed to a first plasma environment comprising O2, HBr, and Cl2.

Abstract: The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.

Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

Abstract: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134).

Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.

Abstract: Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.

Abstract: A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.

Abstract: Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.

Abstract: To form a semiconductor device, an electrode layer is formed over a semiconductor body. The electrode layer includes an amorphous portion. A liner, e.g., a stress-inducing liner, is deposited over the electrode layer. The electrode layer is annealed to recrystallize the amorphous portion of the electrode layer. The liner can then be removed and an electronic component (e.g., a transistor) that includes a feature (e.g., a gate) formed from the electrode layer can be formed.

Abstract: A polysilicon electrode layer (103) (a first electrode layer) is formed by forming a polysilicon film on a gate oxide film (102) on a silicon wafer (101). A tungsten layer (105) (a second electrode layer) is formed on this polysilicon electrode layer (103). In addition, a barrier layer (104) is formed on the polysilicon electrode layer (103) before the formation of the tungsten layer (105). Etching is then conducted using a silicon nitride layer (106) as the etching mask. Next, an oxide insulating film (107) is formed on an exposed surface of the polysilicon layer (103) by plasma oxidation wherein a process gas containing oxygen gas and hydrogen gas is used at a process temperature not less than 300° C. With this method, a selective oxidation of the polysilicon electrode layer (103) can be carried out without oxidizing the tungsten layer (105).

Abstract: In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.

Abstract: Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.

Abstract: A method of removing a photoresist may include permeating supercritical carbon dioxide into the photoresist on a substrate having a conductive structure including a metal. The photoresist permeating the supercritical carbon dioxide may be easily removable. The photoresist permeating the supercritical carbon dioxide may be removed using a photoresist cleaning solution from the substrate. The photoresist cleaning solution may include an alkanolamine solution of about 8 percent by weight to about 20 percent by weight, a polar organic solution of about 25 percent by weight to about 40 percent by weight, a reducing agent of about 0.5 percent by weight to about 3 percent by weight with the remainder being water. The photoresist may be easily removed without damaging the conductive structure in a plasma process.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same.

Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.

Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

Abstract: A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).

Abstract: A manufacturing method of a photoelectric conversion device included a first step of forming a gate electrode, a second step of forming a semiconductor region of a first conductivity type, a third step of forming an insulation film, and a fourth step of forming a protection region of a second conductivity type, which is the opposite conductivity type to the first conductivity type, by implanting ions in the semiconductor region using the gate electrode of the transfer transistor and a portion covering a side face of the gate electrode of the transfer transistor of the insulation film as a mask in a state in which the semiconductor substrate and the gate electrode of the transfer transistor are covered by the insulation film, and causing a portion of the semiconductor region of the first conductivity type from which the protection region is removed to be the charge accumulation region.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

Abstract: A method of forming an integrated circuit device is disclosed. A polycrystalline silicon layer is formed in direct contact with a dielectric material so that the dielectric material induces a stress in the polycrystalline silicon layer as the polycrystalline silicon layer is formed. A MOS transistor that includes a gate comprising the polycrystalline silicon is then completed.

Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

Abstract: To provide a method for producing a solid-state imaging device enabling an improvement of a light sensitivity characteristic in a light receiving unit, a solid-state imaging device in which the light sensitivity characteristic is improved, and a camera provided with the solid-state imaging device. A shield film projected around the light receiving unit is formed on a substrate in which the light receiving unit is formed; an transparent insulation film is formed on the shield film; a sidewall insulation film is formed by etch-back of the insulation film, in a side wall of the shield film; a mask layer having an aperture at a position corresponding to the light receiving unit is formed on the shield film; and the shield film is etched by using the sidewall insulation film and the mask layer as a mask to form an aperture portion exposing the light receiving unit.

Abstract: A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.

Abstract: A method of making an integrally gated carbon nanotube field ionization device comprising forming a first insulator layer on a first side of a substrate, depositing a conductive gate layer on the first insulator layer, forming a cavity in the substrate by etching a second side of the substrate to near the first insulator layer, wherein the second side is opposite the first side and wherein a portion of the first insulator is over the cavity, etching an aperture in the portion of the first insulator layer and the conductive gate layer to form an aperture sidewall, depositing a second insulator layer removing the second insulator layer from the top surface, depositing a metallization layer over the second insulator layer, depositing a catalyst layer on the metallization layer and growing a carbon nanotube from the catalyst layer.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Trenches are formed in a semiconductor substrate at gate edges. Low-concentration impurity regions are then formed at the sidewalls and the bottoms of the trenches. High-concentration impurity regions are formed at the bottoms of the trenches in a depth shallower than the low-concentration impurity regions. Source/drain consisting of the low-concentration impurity regions and the high-concentration impurity regions are thus formed. Therefore, the size of the transistor can be reduced while securing a stabilized operating characteristic even at high voltage. It is thus possible to improve reliability of the circuit and the degree of integration in the device.

Abstract: In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Abstract: In a replacement gate approach, a top area of a gate opening may receive a superior cross-sectional shape after the deposition of a work function adjusting species on the basis of a polishing process, wherein a sacrificial material may protect the sensitive materials in the gate opening.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a gate electrode by shaping a semiconductor film formed above a semiconductor substrate; forming a protective film on a side face of the gate electrode by plasma discharge of a first gas or a second gas, the first gas containing at least one of HBr, Cl2, CF4, SF6, and NF3 in addition to O2 and a flow rate of O2 therein being greater than 80% of the total of the entire flow rate, and the second gas containing at least one of HBr, Cl2, CF4, SF6, and NF3 in addition to O2 and N2 and a flow rate of sum of O2 and N2 therein being greater than 80% of the total of the entire flow rate; and removing a residue of the semiconductor film above the semiconductor substrate after forming the protective film.

Abstract: A laser annealing method for manufacturing a semiconductor device is presented. The method includes at least two forming steps and one annealing step. The first forming steps includes forming gates on a semiconductor substrate. The second forming step includes forming an insulation layer on the semiconductor substrate and on the gates. The annealing step includes annealing the insulation layer using electromagnetic radiation emitted from a laser.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.

Abstract: In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.

Abstract: A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.

Abstract: In one embodiment, a method is provided for forming stress in a semiconductor device. The semiconductor device may include a gate structure on a substrate, wherein the gate structure includes at least one dummy material that is present on a gate conductor. A conformal dielectric layer is formed atop the semiconductor device, and an interlevel dielectric layer is formed on the conformal dielectric layer. The interlevel dielectric layer may be planarized to expose at least a portion of the conformal dielectric layer that is atop the gate structure, in which the exposed portion of the conformal dielectric layer may be removed to expose an upper surface of the gate structure. The upper surface of the gate structure may be removed to expose the gate conductor. A stress inducing material may then be formed atop the at least one gate conductor.

Abstract: A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a first horizontal dimension. One or more growth-stripping operations are performed to reduce a critical dimension of the gate electrode to a second horizontal dimension, where the second horizontal dimension is less than the first horizontal dimension.

Abstract: A method of manufacturing a flash memory device that may include forming a first oxide film pattern and a first polysilicon pattern on a semiconductor substrate; sequentially forming a dielectric film pattern and a second polysilicon pattern on the semiconductor substrate including the first oxide film pattern and the first polysilicon pattern; forming a second oxide film pattern on the second polysilicon pattern; forming a gate by etching to the semiconductor substrate using the second oxide film pattern as a mask, the gate including the first oxide film pattern, the first polysilicon pattern, the dielectric film pattern and the second polysilicon pattern; removing the second oxide film pattern; forming a spacer on sidewalls of the gate; and forming an interlayer dielectric film on the semiconductor substrate including the gate and the spacer.

Abstract: Provided is a manufacturing method of a semiconductor device, the manufacturing method including forming a first thin film on a substrate; forming a second thin film, which is different from the first thin film, on the first thin film; forming a sacrificial film, which is a film different from the second thin film, on the second thin film; forming a sacrificial film pattern by processing the sacrificial film into a pattern having desired intervals through etching; coating a silicon oxide film on the sacrificial film pattern by intermittently supplying a silicon-containing precursor and an oxygen-containing gas onto the substrate; forming sidewall spacers on the sidewalls of the sacrificial film by etching the silicon oxide film; removing the sacrificial film; and processing the first film and the second film by using the sidewall spacers as a mask.

Abstract: Methods for forming semiconductor structures using selectively-formed sidewall spacers are provided. One method comprises forming a first structure and a second structure. The second structure has a height that is greater than the first structure's height. A first sidewall spacer-forming material is deposited overlying the first structure and the second structure. A second sidewall spacer-forming material is deposited overlying the first sidewall spacer-forming material. A composite spacer is formed about the second structure, the composite spacer comprising the first sidewall spacer-forming material and the second sidewall spacer-forming material. The second sidewall spacer-forming material is removed from the first structure and the first sidewall spacer-forming material is removed from the first structure.