With Electrical Circuit Layout Patents (Class 438/599)
  • Patent number: 9991338
    Abstract: An electronic device can include a substrate and an insulating structure laterally surrounded by the substrate. In an aspect, the electronic device can include a first conductive structure or an active region that is laterally surrounded by the insulating structure and the substrate. In another aspect, the electronic device can include an inductor surrounded by the insulating structure. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a plurality of features, including a first feature and a second feature, within the trench; forming a first insulating layer within the trench; removing the first feature to create a first cavity; forming a second insulating layer to at least partly fill the first cavity; removing the second feature to create a second cavity; and forming a conductive or semiconductor structure within the second cavity.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 5, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 9793204
    Abstract: A method of manufacturing a semiconductor structure including a conductive structure, a dielectric layer, and a plurality of conductive features is disclosed. The dielectric layer is formed on the conductive structure. A plurality of through holes is formed in the dielectric layer using a metal hard mask, and at least one of the through holes exposes the conductive structure. The conductive features are formed in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Hung Lin, Chun-Hsien Huang, I-Tseng Chen
  • Patent number: 9754989
    Abstract: A stitched image sensor array on a semiconductor substrate with identical blocks that have wherein said first configuration includes enable inputs, which vary a function of the block depending on the connection to the enable inputs. The enable inputs can set an SRAM to receive different numbers of inputs.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: September 5, 2017
    Inventors: Steven Huang, Christophe Ca Basset, Sam Bagwell, Jonathan Bergey, Loc Truong
  • Patent number: 9547034
    Abstract: An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: January 17, 2017
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 9236267
    Abstract: A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ho Wei De, Kuei-Liang Lu, Ming-Feng Shieh, Ching-Yu Chang
  • Patent number: 9176622
    Abstract: A touch structure is disclosed. The touch structure includes an active region including a plurality of first conductive patterns, and an inactive region including a wiring. The first conductive patterns at an edge of the active region are electrically connected with each other and are electrically connected with the wiring of the inactive region to form a coil. A touch panel and a touch device including the touch structure are also disclosed.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: November 3, 2015
    Assignees: Shanghai Tianma Micro-Electronics Co., Ltd., Tianma Micro-Electronics Co., Ltd.
    Inventors: Songlin Jin, Feng Lu, Qijun Yao, Dunbo Wang
  • Patent number: 9117751
    Abstract: Methods and apparatus for spectrum-based endpointing. An endpointing method includes selecting a reference spectrum. The reference spectrum is a spectrum of white light reflected from a film of interest on a first substrate and has a thickness greater than a target thickness. The reference spectrum is empirically selected for particular spectrum-based endpoint determination logic so that the target thickness is achieved when endpoint is called by applying the particular spectrum-based endpoint logic. The method includes obtaining a current spectrum. The current spectrum is a spectrum of white light reflected from a film of interest on a second substrate when the film of interest is being subjected to a polishing step and has a current thickness that is greater than the target thickness. The method includes determining, for the second substrate, when an endpoint of the polishing step has been achieved. The determining is based on the reference and current spectra.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: August 25, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Dominic J. Benvegnu, Jeffrey Drue David, Boguslaw A. Swedek
  • Patent number: 9105643
    Abstract: An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof. Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: August 11, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Juhan Kim, Mahbub Rashed
  • Patent number: 9006880
    Abstract: The present invention relates to a surface mount package for a micro-electro-mechanical system (MEMS) microphone die and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components that simplifies manufacturing and lowers costs. The surface mount package features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the MEMS microphone die is mechanically attached, providing an interior surface for making electrical connections between the MEMS microphone die and the package, and providing an exterior surface for surface mounting the microphone package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The microphone package has a substrate with metal pads on its top and bottom surfaces, a sidewall spacer, and a lid.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: April 14, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9006100
    Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Yuansheng Ma, Irene Lin, Jason Stephens, Yunfei Deng, Yuan Lei, Jongwook Kye, Rod Augur, Shibly Ahmed, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8993429
    Abstract: To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in contact with landing areas on corresponding pads in the stack. Adjacent rows are separated from one another in a Y direction generally perpendicular to the X direction. The interlayer conductors in a row have a first pitch in the X direction. The interlayer conductors in adjacent rows are offset in the X direction by an amount less than the first pitch. Interconnect conductors are formed over and in contact with interlayer conductors. The interconnect conductors extend in the Y direction and have a second pitch less than the first pitch.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: March 31, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Shih-Hung Chen
  • Patent number: 8987128
    Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Marc Tarabbia, Chinh Nguyen, David Doman, Juhan Kim, Xiang Qi, Suresh Venkatesan
  • Patent number: 8987136
    Abstract: A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth.
    Type: Grant
    Filed: February 27, 2011
    Date of Patent: March 24, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang
  • Patent number: 8987787
    Abstract: A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Kuang-Yeu Hsieh, Cheng-Yuan Wang
  • Publication number: 20150054568
    Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: QUALCOMM INCORPORATED
    Inventors: Seid Hadi RASOULI, Michael Joseph BRUNOLLI, Christine Sung-An HAU-RIEGE, Mickael MALABRY, Sucheta Kumar HARISH, Prathiba BALASUBRAMANIAN, Kamesh MEDISETTI, Nikolay BOMSHTEIN, Animesh DATTA, Ohsang KWON
  • Publication number: 20150054567
    Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Seid Hadi RASOULI, Animesh DATTA, Ohsang KWON
  • Patent number: 8953314
    Abstract: A fully-passive, dynamically configurable directed cooling system for a microelectronic device is disclosed. In general, movable pins are suspended within a cooling plenum between an active layer and a second layer of the microelectronic device. In one embodiment, the second layer is another active layer of the microelectronic device. The movable pins are formed of a material that has a surface tension that decreases as temperature increases such that, in response to a temperature gradient on the surface of the active layer, the movable pins move by capillary flow in the directions of decreasing temperature. By moving in the direction of decreasing temperature, the movable pins move away from hot spots on the surface of the active layer, thereby opening a pathway for preferential flow of a coolant through the cooling plenum at a higher flow rate towards the hot spots.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: February 10, 2015
    Assignee: Georgia Tech Research Corporation
    Inventor: Andrei G. Fedorov
  • Patent number: 8935850
    Abstract: A method for manufacturing a printed wiring board includes forming a removable layer on a support substrate, forming an interlayer resin insulation layer on the removable layer, forming a penetrating hole in the interlayer resin insulation layer, forming a first conductive layer on the interlayer resin insulation layer and on a side wall of the penetrating hole, forming a conductive circuit on the interlayer resin insulation layer, forming a via conductor in the penetrating hole, removing the support substrate from the interlayer resin insulation layer by using the removable layer, forming a protruding portion of the via conductor protruding from a surface of the interlayer resin insulation layer, and forming a surface-treatment coating on a surface of the protruding portion of the via conductor.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: January 20, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Masahiro Kaneko, Satoru Kose, Hirokazu Higashi
  • Patent number: 8916939
    Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Hong Yu, Huang Liu
  • Patent number: 8900883
    Abstract: In one embodiment of the invention, there is provided a method for manufacturing a magnetic memory device, comprising: depositing a carbon layer comprising amorphous carbon on a substrate; annealing the carbon layer to activate dopants contained therein; and selectively etching portions of the carbon layer to forms lines of spaced apart carbon conductors.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: December 2, 2014
    Assignee: III Holdings 1, LLC
    Inventor: Krishnakumar Mani
  • Patent number: 8883625
    Abstract: A method for defining parallel lines extending along a first direction in a same level of an integrated circuit, among which at least first and second lines separated by an even number of lines are interconnected, a space having a width at least equal to the minimum space between two lines separated by one line being left free, in a second direction perpendicular to the first direction, on either side of a minimum rectangle containing the first and the second lines.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Vincent Farys, Emmanuelle Serret
  • Patent number: 8865583
    Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: October 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Yanagidaira, Chikaaki Kodama
  • Patent number: 8809180
    Abstract: A method for producing at least one semiconductor component group, in particular a SiC semiconductor component group, includes the step of producing a number of semiconductor components on a substrate, particularly on a wafer. The individual semiconductor components are tested for detecting operative semiconductor components. At least one semiconductor component group is assembled, which is formed of a number of operative semiconductor components and which forms a coherent flat structure. The operative semiconductor components of the semiconductor component group are electrically connecting in parallel.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: August 19, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventors: Karl Weidner, Robert Weinke
  • Publication number: 20140217473
    Abstract: A method for manufacturing of a device including a first substrate including a plurality of sets of nanostructures arranged on the first substrate, wherein each of the sets of nanostructures is individually electrically addressable, the method including the steps of: providing a substrate having a first face, the substrate having an insulating layer including an insulating material arranged on the first face of the substrate forming an interface between the insulating layer and the substrate; providing a plurality of stacks on the first substrate, wherein each stack includes a first conductive layer and a second conductive layer; heating the first substrate having the plurality of stacks arranged thereon in a reducing atmosphere to enable formation of nanostructures on the second conductive material; heating the first substrate having the plurality of stacks arranged thereon in an atmosphere such that nanostructures are formed on the second layer.
    Type: Application
    Filed: June 29, 2012
    Publication date: August 7, 2014
    Inventor: Waqas Khalid
  • Patent number: 8765530
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 1, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8741763
    Abstract: An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: June 3, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yuansheng Ma, Jongwook Kye, Harry Levinson, Hidekazu Yoshida, Mahbub Rashed
  • Patent number: 8704360
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 22, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8703597
    Abstract: A method for fabricating a device, the method including: providing a first layer including first transistors, where the first transistors include a mono-crystalline semiconductor; overlaying a second semiconductor layer over the first layer; fabricating a plurality of memory cell control lines where the control lines include a portion of the second layer; where the second layer includes second transistors, where the second transistors include a mono-crystalline semiconductor, and where the second transistors are configured to be memory cells.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: April 22, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • Patent number: 8689163
    Abstract: A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: April 1, 2014
    Assignees: Samsung Electronics Co., Ltd., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Dong-Yun Kim, Dong-Hoon Yeo, Hyun-Chul Shin, Kyung-Ho Kim, Byung-Tae Kang, Ju-Yong Shin, Sung-Chul Lee
  • Publication number: 20140078817
    Abstract: Integrated circuits that include SRAM cells having additional read stacks and methods for their fabrication are provided. In accordance with one embodiment a method for fabricating such an integrated circuit includes forming a plurality of SRAM cells in and on a semiconductor substrate, each of the plurality of SRAM cells including a read pull down transistor and a read pass gate transistor. First conductivity-determining impurity ions are implanted to establish a first threshold voltage in each of the read pull down transistors; and second conductivity-determining impurity ions are implanted to establish a second threshold voltage different than the first threshold voltage in each of the read pass gate transistors.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ralf van Bentum, Torsten Klick
  • Patent number: 8664759
    Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: March 4, 2014
    Assignee: Agere Systems LLC
    Inventor: Vivian Ryan
  • Patent number: 8652883
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 18, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Publication number: 20140027918
    Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Marc Tarabbia, Chinh Nguyen, David Doman, Juhan Kim, Xiang Qi, Suresh Venkatesan
  • Patent number: 8633064
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's sprinted circuit board.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 21, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8629005
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 14, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8629552
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: January 14, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8624387
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: January 7, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8623710
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 7, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8623709
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 7, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8624385
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: January 7, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8624384
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: January 7, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8624386
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: January 7, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8617934
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 31, 2013
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8614496
    Abstract: A method scales down an integrated circuit layout structure without substantially jeopardizing electronic characteristics of devices. First, a conductive line set includes a first conductive line and a second conductive line respectively passing through a first region and a second region. Second, a sizing-down operation is performed so that the first conductive line and the second conductive line respectively have a first region scaled-down line width, a first region scaled-down space and a first region scaled-down pitch in the first region as well as selectively have a second region original line width, a second region scaled-down space and a second region scaled-down pitch in the second region. The first region scaled-down line width and the second region original line width are substantially different from each other.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: December 24, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Hsien-Chang Chang
  • Patent number: 8598593
    Abstract: A chip includes an integrated circuit and a carbonic layer. The carbonic layer includes a graphite-like carbon, wherein a lateral conducting path through the graphite-like carbon electrically connects two circuit elements of the integrated circuit.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: December 3, 2013
    Assignee: Infineon Technologies AG
    Inventor: Uwe Hoeckele
  • Publication number: 20130295761
    Abstract: Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.
    Type: Application
    Filed: July 2, 2013
    Publication date: November 7, 2013
    Inventors: Sung-Min Hwang, Hansoo Kim, Wonseok Cho, Jaehoon Jang
  • Patent number: 8575025
    Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: November 5, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David Fitzpatrick, Kevin Dooley, Lorraine Byrne
  • Patent number: 8519482
    Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: August 27, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Hong Yu, Huang Liu
  • Patent number: 8502377
    Abstract: A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 ?m and 40 ?m and a length substantially between 70 ?m and 130 ?m, for example.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: August 6, 2013
    Assignee: Mediatek Inc.
    Inventors: Tzu-Hung Lin, Ching-Liou Huang, Thomas Matthew Gregorich
  • Patent number: 8471299
    Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
    Inventors: Guo Hua Zhong, Mei Yang