Selectively Interconnecting (e.g., Customization, Wafer Scale Integration, Etc.) Patents (Class 438/598)
  • Patent number: 9705165
    Abstract: The present invention provides a lithium-air battery air electrode, the air electrode comprises: a collector, an in-situ loading catalyst on collector. The invention also provides a preparation method of the air electrode for lithium-air batteries and the lithium-air batteries. The air electrode of the present invention can greatly improve the performance of the lithium-air battery.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: July 11, 2017
    Assignee: SHANGHAI INSTITUTE OF CERAMICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Zhaoyin Wen, Yanming Cui, Yu Liu, Xiangwei Wu, Jingchao Zhang
  • Patent number: 9431336
    Abstract: A semiconductor device includes a substrate including a memory cell region and a contact region, a string structure including conductive layers and first interlayer insulating layers alternately stacked over the substrate and protruded toward a lower layer from the memory cell region toward the contact region, barrier rib patterns spaced apart from one another over the conductive layers in the contact region and configured to open the layers of the conductive layers in the contact region through the spaced spaces, and first contact plugs filled into the space between barrier rib patterns adjacent to each other and coupled to the conductive layers in the contact region.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: August 30, 2016
    Assignee: SK Hynix Inc.
    Inventor: Yong Hyun Lim
  • Patent number: 9269669
    Abstract: A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: February 23, 2016
    Assignee: Infineon Technologies AG
    Inventors: Johann Helneder, Markus Schwerd, Thomas Goebel, Andrea Mitchell, Heinrich Koerner, Martina Hommel
  • Patent number: 9153482
    Abstract: Methods and apparatus for selective deposition of cobalt on copper lines in the presence of exposed dielectric in semiconductor processing are provided. Cobalt in its metallic form is selectively deposited onto copper in the presence of dielectric by contacting a prepared surface of the substrate with an organometallic cobalt compound in a presence of a reducing agent. Surface preparation involves H2 treatment with concurrent UV light irradiation. After the substrate surface is prepared, the substrate is contacted with an organometallic cobalt compound comprising a substituted or unsubstituted allyl ligand in a presence of a reducing agent to selectively deposit cobalt on copper. No plasma treatment during or after cobalt deposition is necessary, and the method can be used in a presence of a ULK dielectric without causing damage to dielectric. Deposited cobalt caps are used to reduce copper electromigration and to improve adhesion of copper to subsequently deposited layers.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: October 6, 2015
    Assignee: Lam Research Corporation
    Inventors: Thomas Joseph Knisley, Nagraj Shankar, Pramod Subramonium
  • Patent number: 9093642
    Abstract: According to one embodiment, dry etching is performed so that an upper-layer wiring material layer, a memory-layer constituting layer, and an interlayer insulating film are processed to form a pattern including a line-and-space pattern extending in a second direction and a dummy pattern connecting line patterns constituting the line-and-space pattern in a memory cell formation region and an upper-layer wiring hookup region. Then, the dummy pattern is removed.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: July 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mutsumi Okajima
  • Patent number: 9087885
    Abstract: Provided is a method of fabricating a semiconductor device. In one embodiment, the method includes forming at least one unit device in a substrate and on a front side of the substrate, forming a through-silicon via (TSV) structure apart from the at least one unit device to substantially vertically penetrate the substrate, the TSV structure having a back end including a concave portion, forming an internal circuit on the front side of the substrate and a front end of the TSV structure to be electrically connected to the at least one unit device and the front end of the TSV structure, forming a front side bump on the front side of the substrate to be electrically connected to the front end of the TSV structure, forming a redistribution layer on a back side of the substrate to be electrically connected to the back end of the TSV structure, and forming a back side bump to be electrically connected to the redistribution layer.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wook Ji, Yeong-Lyeol Park, Hyoung-Yol Mun, In-Kyum Lee
  • Publication number: 20150126026
    Abstract: A method of manufacturing an electrical component includes providing a substrate, applying an insulating layer on the substrate, applying a circuit layer on the insulating layer, irradiating the insulating layer with an electron beam to transform the insulating layer, and irradiating the circuit layer with an electron beam to transform the circuit layer. The substrate may be a metallic substrate that is highly thermally conductive. The insulating layer provides electrical isolation and effective heat transfer between the circuit layer and the substrate. The method may include coupling a light emitting diode module or other active circuits requiring thermal management to the circuit layer resident on the electrically insulating/thermally conducting layer.
    Type: Application
    Filed: January 5, 2015
    Publication date: May 7, 2015
    Inventors: Soenke Sachs, Helge Schmidt, Michael Leidner, Eva Henschel, Dominique Freckmann, Marjorie Myers
  • Patent number: 9012270
    Abstract: Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed self-assembly (DSA), forming a metal layer over the DSA pre-patterned transistor layout, including: forming a plurality of horizontal metal lines; and forming a plurality of vertical metal segments discontinuous from and between adjacent horizontal metal lines; and forming one or more bridging dots each connecting one of the plurality of horizontal metal lines to one of the plurality of vertical metal segments, wherein locations of the bridging dots determine logic functions of resulting transistor cells.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ji Xu, Vito Dai
  • Patent number: 8987923
    Abstract: Among other things, a semiconductor seal ring and method for forming the same are provided. The semiconductor seal ring comprises a plurality of dielectric layers formed over a semiconductor substrate upon which a semiconductor device is formed. A plurality of conductive layers is arranged among at least some of the plurality of dielectric layers. An upper conductive layer is formed over the plurality of dielectric layers. An upper passivation layer is formed over the upper conductive layer to isolate the upper conductive layer from conductive debris resulting from a die saw process along a die saw cut line. In an example, a first columnar region comprising a first portion of the conductive layers is electrically isolated from the semiconductor device because the first columnar region is disposed relatively close to the die saw cut line and thus can be exposed to conductive debris which can cause undesired short circuits.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Chih Chou, Huei-Ru Liou, Kong-Beng Thei
  • Publication number: 20150070073
    Abstract: An integrated circuit, including: at least three integrated circuit portions mutually spaced on a single electrically insulating die, the integrated circuit portions being mutually galvanically isolated; and signal coupling structures on the die to allow communication of signals between the integrated circuit portions while maintaining the galvanic isolation therebetween.
    Type: Application
    Filed: April 17, 2013
    Publication date: March 12, 2015
    Applicant: The Silanna Group Pty Ltd
    Inventors: Vijay Yashodhan Moghe, Andrew Terry
  • Patent number: 8928119
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: January 6, 2015
    Inventor: Glenn J. Leedy
  • Patent number: 8912088
    Abstract: The present invention provides a transfer substrate for transferring a metal wiring material to a transfer-receiving object, the transfer substrate comprising a substrate, at least one metal wiring material formed on the substrate and an underlying metal film formed between the substrate and the metal wiring material, wherein the metal wiring material is a molded article prepared by sintering, e.g., gold powder having a purity of 99.9% by weight or more and an average particle size of 0.01 ?m to 1.0 ?m and the underlying metal film is composed of a metal such as gold or an alloy. The transfer substrate is capable of transferring a metal wiring material to the transfer-receiving object even at a temperature for heating the transfer-receiving object of 80 to 300° C.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: December 16, 2014
    Assignee: Tanaka Kikinzoku Kogyo K.K.
    Inventors: Toshinori Ogashiwa, Masaaki Kurita, Takashi Nishimori, Yukio Kanehira
  • Patent number: 8900929
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: December 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Pandi Chelvam Marimuthu, Kang Chen
  • Patent number: 8877628
    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Micron Technologies, Inc.
    Inventors: Jun Liu, Kunal R. Parekh
  • Patent number: 8871627
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Tera Probe, Inc.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20140312504
    Abstract: A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration, and in subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.
    Type: Application
    Filed: June 30, 2014
    Publication date: October 23, 2014
    Inventor: John M. Drynan
  • Patent number: 8865585
    Abstract: A method of forming post passivation interconnects comprises forming a passivation layer over a substrate, wherein a metal pad is embedded in the passivation layer, depositing a first dielectric layer on the passivation layer, applying a first patterning process to the first dielectric layer to form a first opening, forming a first seed layer over the first opening, filling the first opening with a conductive material, depositing a second dielectric layer on the first dielectric layer, applying a second patterning process to the second dielectric layer to form a second opening, forming an under bump metallization structure over the second opening and mounting an interconnect bump over the under bump metallization structure.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Wei Chou, Hung-Jui Kuo, Ming-Che Ho, Chung-Shi Liu
  • Patent number: 8866193
    Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT).
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: October 21, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8865583
    Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: October 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Yanagidaira, Chikaaki Kodama
  • Patent number: 8846444
    Abstract: A semiconductor package includes a semiconductor chip having a first surface, on which an electrode pad is arranged, and a second surface which is the other side of the semiconductor chip, an insulation member formed on the second surface of the semiconductor chip, and comprising a via hole at a position spaced apart from the semiconductor chip, and a conductive filler filling the via hole.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: September 30, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jin Ho Bae
  • Publication number: 20140248764
    Abstract: One illustrative method disclosed herein includes forming a seed layer above a substrate that includes a conductive region, wherein the seed layer is comprised of a metal-containing material, forming a nucleation layer on the seed layer, wherein the nucleation layer is comprised of a transition metal oxide ceramic material, and performing a thermal treatment process at a temperature so as to generate a plurality of spaced-apart, vertically oriented alloy structures, wherein the alloy structures are comprised of at least one material from the seed layer and at least one material from the nucleation layer.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 4, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Manfred Heinrich Moert
  • Patent number: 8824114
    Abstract: A circuit comprises a first conductor, a second conductor, and a first detect and disconnect circuit. The first conductor is coupled to a first power supply voltage terminal. The second conductor is positioned a first predetermined distance from the first conductor. The first detect and disconnect circuit has a first terminal coupled to the second conductor and a second terminal coupled to a second power supply voltage terminal. The first detect and disconnect circuit detects a first electrical property change between the second conductor and the first conductor. In response to detecting the change in the first electrical property, the second conductor is disconnected from the second power supply voltage terminal. A method for manufacturing a semiconductor device comprising the circuit is also provided.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: September 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jason C. Perkey, Scott S. Roth, Tim J. Zoerner
  • Patent number: 8815729
    Abstract: One illustrative method disclosed herein includes forming a seed layer above a substrate that includes a conductive region, wherein the seed layer is comprised of a metal-containing material, forming a nucleation layer on the seed layer, wherein the nucleation layer is comprised of a transition metal oxide ceramic material, and performing a thermal treatment process at a temperature so as to generate a plurality of spaced-apart, vertically oriented alloy structures, wherein the alloy structures are comprised of at least one material from the seed layer and at least one material from the nucleation layer.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Manfred Heinrich Moert
  • Patent number: 8809180
    Abstract: A method for producing at least one semiconductor component group, in particular a SiC semiconductor component group, includes the step of producing a number of semiconductor components on a substrate, particularly on a wafer. The individual semiconductor components are tested for detecting operative semiconductor components. At least one semiconductor component group is assembled, which is formed of a number of operative semiconductor components and which forms a coherent flat structure. The operative semiconductor components of the semiconductor component group are electrically connecting in parallel.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: August 19, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventors: Karl Weidner, Robert Weinke
  • Patent number: 8803314
    Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 12, 2014
    Assignee: Raytheon Company
    Inventors: Premjeet Chahal, Francis J. Morris
  • Patent number: 8759207
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Mathias Vaupel, Rainer Steiner, Werner Robl, Jens Pohl, Joem Plagmann, Gottfried Beer
  • Patent number: 8741771
    Abstract: A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may also be incorporated in the damascene process as a final polish step to clean up surfaces that have been planarized using a CMP step.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Anthony K. Stamper
  • Patent number: 8741737
    Abstract: Described are three-dimensional stacked semiconductor structures having one or more vertical interconnects. Vertical stacking relies on vertical interconnects and wafer bonding using a patternable polymer. The polymer is preferably lithographically patternable and photosensitive. Curing of the polymer is preselected from about 35% to up to about 100%, depending on a desired outcome. When fabricated, such vertically stacked structures include electrical interconnects provided by solder reflow. Solder reflow temperature is bounded by a curing and glass transition temperatures of a polymer used for bonding.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: June 3, 2014
    Assignee: Board of Regents, The University of Texas System
    Inventors: Dan O. Popa, Rachita Dewan, Praveen Pandojirao-Sunkojirao, Jung-Chih Chiao
  • Patent number: 8741762
    Abstract: A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: June 3, 2014
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Hao Liu, Yi Sheng Anthony Sun, Ravi Kanth Kolan, Chin Hock Toh
  • Patent number: 8704353
    Abstract: A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first plurality of electrically non-functional interconnects on a back side of the first semiconductor chip. Additional chips may be stacked on the first semiconductor chip.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 22, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Su, Bryan Black, Neil McLellan, Joe Siegel, Michael Alfano
  • Patent number: 8697563
    Abstract: A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance. The semiconductor device may include: a second active region including a silicon layer connected to a first active region of a semiconductor substrate; a gate formed over the second active region; a spacer formed on sidewalls of the gate; a source/drain region form at both sides of the spacer; and a metal silicide layer formed over the gate and the source/drain region.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: April 15, 2014
    Assignee: SK hynix Inc.
    Inventor: Yun Taek Hwang
  • Patent number: 8691682
    Abstract: Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tai-Soo Lim, HyunSeok Lim, Shin-Jae Kang, Kyung-Tae Jang
  • Patent number: 8689163
    Abstract: A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: April 1, 2014
    Assignees: Samsung Electronics Co., Ltd., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Dong-Yun Kim, Dong-Hoon Yeo, Hyun-Chul Shin, Kyung-Ho Kim, Byung-Tae Kang, Ju-Yong Shin, Sung-Chul Lee
  • Patent number: 8673725
    Abstract: A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: March 18, 2014
    Assignees: Tokyo Electron Limited, International Business Machines Corporation
    Inventors: David L. O'Meara, Anthony Dip, Aelan Mosden, Pao-Hwa Chou, Richard A Conti
  • Patent number: 8673760
    Abstract: One illustrative method disclosed herein includes forming a seed layer above a substrate that includes a conductive region, wherein the seed layer is comprised of a metal-containing material, forming a nucleation layer on the seed layer, wherein the nucleation layer is comprised of a transition metal oxide ceramic material, and performing a thermal treatment process at a temperature so as to generate a plurality of spaced-apart, vertically oriented alloy structures, wherein the alloy structures are comprised of at least one material from the seed layer and at least one material from the nucleation layer.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Manfred Heinrich Moert
  • Patent number: 8664125
    Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: March 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Angelique Denise Raley, Takuya Mori, Hiroto Ohtake
  • Patent number: 8664106
    Abstract: A method of manufacturing a semiconductor device, wherein a first substrate where first electrode pads are formed and a second substrate where second electrode pads are formed are stacked and the first electrode pads and the corresponding second electrode pads are electrically connected thereby forming the semiconductor device is disclosed. The method includes steps of performing a first hydrophilic treatment with respect to the first electrode pads; supplying liquid to a surface where the first electrode pads are formed in the first substrate; and placing the second substrate on the first substrate to which the liquid is supplied so that the surface where the first electrode pads are formed opposes a surface where the second electrode pads are formed, thereby aligning the first electrode pads and the second electrode pads by the liquid that gathers in the first electrode pads that have been subject to the first hydrophilic treatment.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: March 4, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Haruo Iwatsu
  • Patent number: 8664759
    Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: March 4, 2014
    Assignee: Agere Systems LLC
    Inventor: Vivian Ryan
  • Patent number: 8658526
    Abstract: A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: February 25, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Huiwen Xu, Yung-Tin Chen, Steven J. Radigan
  • Patent number: 8642460
    Abstract: A switching device including a first dielectric layer having a first top surface, two conductive features embedded in the first dielectric layer, each conductive feature having a second top surface that is substantially coplanar with the first top surface of the first dielectric layer, and a set of discrete islands of a low diffusion mobility metal between the two conductive features. The discrete islands of the low diffusion mobility metal may be either on the first top surface or embedded in the first dielectric layer. The electric conductivity across the two conductive features of the switching device increases when a prescribed voltage is applied to the two conductive features. A method of forming such a switching device is also provided.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephen A Cohen, Baozhen Li
  • Publication number: 20140024146
    Abstract: A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.
    Type: Application
    Filed: August 3, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diego Anzola, Evan G. Colgan, Kevin K. Dezfulian, Daniel C. Edelstein, Mark C. H. Lamorey, Sampath Purushothaman, Thomas M. Shaw, Roy R. Yu
  • Patent number: 8633104
    Abstract: According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: January 21, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myungjung Pyo, Hyo-Jung Kim, JongHeun Lim, Kyunghyun Kim, Byoungmoon Yoon, JaHyung Han
  • Patent number: 8633099
    Abstract: A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N?1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W?1 contact openings to create extended contact openings extending to W?1 conductive layers; 2n?1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: January 21, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Shih-Hung Chen, Teng-Hao Yeh, Chih-Wei Hu, Feng-Nien Tsai, Lo-Yueh Lin
  • Publication number: 20140015143
    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jun Liu, Kunal R. Parekh
  • Patent number: 8629542
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: January 14, 2014
    Inventor: Glenn J. Leedy
  • Patent number: 8629066
    Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Lo, Hung-Jung Tu, Hai-Ching Chen, Tien-I Bao, Wen-Chih Chiou, Chen-Hua Yu
  • Publication number: 20130328205
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Applicants: Globalfoundries Inc., STMircoelectronics Inc., International Business Machines Corporation
    Inventors: Globalfoundries Inc., International Business Machines Corporation, STMircoelectronics Inc.
  • Patent number: 8592303
    Abstract: There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: November 26, 2013
    Assignees: Renesas Electronics Corporation, NEC Corporation
    Inventors: Munehiro Tada, Yoshihiro Hayashi, Yoshimichi Harada, Fuminori Ito, Hiroto Ohtake, Tatsuya Usami
  • Patent number: 8592993
    Abstract: A monolithic integrated electronic device includes a substrate having a surface region and one or more integrated micro electro-mechanical systems and electronic devices provided on a first region overlying the surface region. Each of the integrated micro electro-mechanical systems and electronic devices has one or more contact regions. The first region has a first surface region. One or more trench structures are disposed within one or more portions of the first region. A passivation material overlies the first region and the one or more trench structures. A conduction material overlies the passivation material, the one or more trench structures, and one or more of the contact regions. The device also has one or more edge bond pad structures within a vicinity of the one or more bond pad structures, which are formed by a singulation process within a vicinity of the one or more bond pad structures.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 26, 2013
    Assignee: mCube Inc.
    Inventor: Xiao (Charles) Yang
  • Patent number: 8587124
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the pump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: November 19, 2013
    Assignee: Teramikros, Inc.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara