Using Structure Alterable To Nonconductive State (i.e., Fuse) Patents (Class 438/601)
  • Patent number: 10643074
    Abstract: Techniques are described for a content rating system that allows for automatic assignment of maturity ratings for media content.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: May 5, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Emily Evon McAninly, Bojan Pepik, Benjamin Chung Yen Cheung, Vernon Germano, Kripa Kanchana Sivakumar, Eric Orme, Loris Bazzani, Prateek Ramesh Chandra Shah, Matthew J. Norman, Michael Donoser
  • Patent number: 10521537
    Abstract: A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shien-Yang Wu, Jye-Yen Cheng, Wei-Chang Kung
  • Patent number: 10475740
    Abstract: A fuse structure for dynamic random access memory (DRAM) includes: a shallow trench isolation (STI) in a substrate; a first select gate in the substrate and adjacent to one side of the STI; a second select gate in the substrate and adjacent to another side of the STI; and a gate structure on the STI, the first select gate, and the second select gate.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 9661752
    Abstract: A circuit arrangement has a populated circuit carrier and includes a flat insulation carrier having a top side and a patterned metallization layer on the top side and a first power semiconductor chip arranged on a first section of the metallization layer. The first power semiconductor chip has a first lower chip load terminal electrically conductively connected to the first section. A shunt resistor is arranged on a second section of the metallization layer. The shunt resistor has a lower main terminal electrically conductively connected to the second section. An electrically conductive connection is provided between the first section and the second section. The electrically conductive connection includes a constriction between the first section and the second section so that a current which flows between the first lower chip load terminal and the lower main terminal during operation of the circuit arrangement must pass through the constriction.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies AG
    Inventors: Tao Hong, Markus Thoben
  • Patent number: 9349700
    Abstract: A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A first insulating layer is formed over the substrate. A second insulating layer is formed over the first insulating layer. A second conductive layer is formed over the second insulating layer. The second insulating layer is formed to include a cylindrical shape. The second conductive layer is formed as an under bump metallization layer. A first opening is formed in the second insulating layer. A second opening is formed in the second insulating layer around the first opening in the second insulating layer. An opening is formed in the first insulating layer over the first conductive layer. An opening is formed in the second insulating layer over the first conductive layer with the opening of the first insulating layer being greater than the opening of the second insulating layer.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: May 24, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Ming-Che Hsieh, Chien Chen Lee
  • Patent number: 9263384
    Abstract: Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface of the link and at least one sidewall of the link. The programmable device includes at least one second contact coupled to a second end of the link. The at least one second contact is adjacent a portion of the top surface of the link and at least one sidewall of the link.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventor: Frank Huebinger
  • Patent number: 9257322
    Abstract: A method for manufacturing a through substrate via (TSV) structure, a TSV structure, and a control method of a TSV capacitance are provided. The method for manufacturing the TSV structure includes: providing a substrate having a first surface and a second surface; forming a trench in the first surface of the substrate; filling a low resistance material into the trench; forming an insulating layer on the first surface of the substrate; forming at least one opening in the first surface of the substrate, wherein the opening is located differently the trench; forming an oxide liner layer, a barrier layer and a conductive seed layer on a sidewall and a bottom of the opening and on the insulating layer of the first surface; and filling a conductive material into the opening, wherein the opening is used to form at least one via.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: February 9, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Erh-Hao Chen, Cha-Hsin Lin, Tzu-Kun Ku
  • Patent number: 9236344
    Abstract: A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: January 12, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Douglas M. Reber, Mehul D. Shroff, Edward O. Travis
  • Patent number: 9209045
    Abstract: An embodiment is a structure comprising a die having a pad on a surface and an encapsulant at least laterally encapsulating the die. The pad is exposed through the encapsulant. The structure further includes a first dielectric layer over the encapsulant and the die, a first conductive pattern over the first dielectric layer, and a second dielectric layer over the first conductive pattern and the first dielectric layer. The first dielectric layer and the second dielectric layer have a first opening to the pad of the die. The structure further includes a second conductive pattern over the second dielectric layer and in the first opening. The second conductive pattern adjoins a sidewall of the first dielectric layer in the first opening and a sidewall of the second dielectric layer in the first opening.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 9190235
    Abstract: The invention relates to a method of manufacturing a circuit protector and to a circuit protector. The method comprises the steps of providing a substrate having opposing end portions, coupling an element layer to the top surface of the substrate, and laser machining the element layer to shape the element layer into a predetermined geometry. The circuit protector comprises a substrate having opposing end portions, termination pads coupled to the top surface at opposing end portions of the substrate, a fuse element disposed across a space between the termination pads and electrically connecting the termination pads, the fuse element having a predetermined geometry; the predetermined geometry having the narrowest width of about 0.025 to about 0.050 millimeters, a cover coupling the top surface and suffusing the substrate, the fuse element and the termination pads, and end terminations in electrical contact with the termination pads at the opposing end portions.
    Type: Grant
    Filed: December 29, 2007
    Date of Patent: November 17, 2015
    Assignee: COOPER TECHNOLOGIES COMPANY
    Inventors: Sidharta Wiryana, Tianyu Zhu
  • Patent number: 9142506
    Abstract: E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: September 22, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9082769
    Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: July 14, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Satoshi Kageyama, Yuichi Nakao
  • Patent number: 9070687
    Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: June 30, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chung Lai, Kang-Min Kuo, Yen-Ming Peng, Gwo-Chyuan Kuoh, Han-Wei Yang, Yi-Ruei Lin, Chin-Chia Chang, Ying-Chieh Liao, Che-Chia Hsu, Bor-Zen Tien
  • Patent number: 9059173
    Abstract: An electronic fuse structure having an Mx level including an Mx dielectric, a fuse line, an Mx cap dielectric above at least a portion of the Mx dielectric, and a modified portion of the Mx cap dielectric directly above at least a portion of the fuse line, where the modified portion of the Mx cap dielectric is chemically different from the remainder of the Mx cap dielectric, an Mx+1 level including an Mx+1 dielectric, a first Mx+1 metal, an Mx+1 cap dielectric above of the Mx+1 dielectric and the first Mx+1 metal, where the Mx+1 level is above the Mx level, and a first via electrically connecting the fuse line to the first Mx+1 metal.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ronald G. Filippi, John A. Fitzsimmons, Erdem Kaltalioglu, Ping-Chuan Wang, Lijuan Zhang
  • Publication number: 20150130018
    Abstract: In an embodiment of the present invention, a semiconductor device comprises a non-fuse area that has a non-fuse via, a non-fuse line, and a non-fuse dielectric stack. The semiconductor device further comprises a fuse area that has a fuse via, a fuse line, and a fuse dielectric stack. The fuse dielectric stack comprises at least a first dielectric and a second dielectric material. The fuse via is at least partially embedded in the first dielectric material and the fuse line is embedded in the second dielectric material.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Applicant: International Business Machines Corporation
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Wai-Kin Li, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9024411
    Abstract: A three-dimensionally (3d) confined conductor advantageously used as an electronic fuse and self-aligned methods of forming the same. By non-conformal deposition of a dielectric film over raised structures, a 3d confined tube, which may be sub-lithographic, is formed between the raised structures. Etching holes which intersect the 3d confined region and subsequent metal deposition fills the 3d confined region and forms contacts. When the raised structures are gates, the fuse element may be located at the middle of the line (i.e. in pre-metal dielectric). Other methods for creating the structure are also described.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Junjun Li, Yan Zun Li, Chengwen Pei, Pinping Sun
  • Publication number: 20150099356
    Abstract: Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts.
    Type: Application
    Filed: December 17, 2014
    Publication date: April 9, 2015
    Inventors: Rajiv V. Joshi, Chih-Chao Yang
  • Patent number: 8981492
    Abstract: An integrated circuit product is disclosed that includes a resistor body and an e-fuse body positioned on a contact level dielectric material, wherein the resistor body and the e-fuse body are made of the same conductive material, a first plurality of conductive contact structures are coupled to the resistor body, conductive anode and cathode structures are conductively coupled to the e-fuse body, wherein the first plurality of conductive contact structures and the conductive anode and cathode structures are made of the same materials.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: March 17, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: O Sung Kwon, Xiaoqiang Zhang, Anurag Mittal
  • Patent number: 8962467
    Abstract: Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Junjing Bao
  • Publication number: 20150048479
    Abstract: A method including forming a first via opening in a substrate, the first via opening is self-aligned to a first trench in the substrate, forming a second via opening in the substrate, the second via opening is self-aligned to a second trench in the substrate, a portion of the second via opening overlaps a portion of the first via opening to form an overlap region, and the overlap region having a width (w) equal to or greater than a space (s) between the first trench and the second trench, and removing a portion of the substrate in the overlap region to form a bridge opening, the bridge opening is adjacent to the first and second via openings and extends between the first and second trenches.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Junjing Bao, Samuel S. Choi, Wai-Kin Li
  • Publication number: 20150041950
    Abstract: A three-dimensionally (3d) confined conductor advantageously used as an electronic fuse and self-aligned methods of forming the same. By non-conformal deposition of a dielectric film over raised structures, a 3d confined tube, which may be sub-lithographic, is formed between the raised structures. Etching holes which intersect the 3d confined region and subsequent metal deposition fills the 3d confined region and forms contacts. When the raised structures are gates, the fuse element may be located at the middle of the line (i.e. in pre-metal dielectric). Other methods for creating the structure are also described.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: International Business Machines Corporation
    Inventors: Junjun Li, Yan Zun Li, Chengwen Pei, Pinping Sun
  • Publication number: 20150028447
    Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 29, 2015
    Applicant: GLOBAL FOUNDRIES Inc.
    Inventors: Xiaoqiang Zhang, O Sung Kwon, Jianghu Yan, Wen-Hu Hung, Roderick Miller, HongLiang Shen
  • Patent number: 8927411
    Abstract: A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Felix P. Anderson, Timothy H. Daubenspeck, Jeffrey P. Gambino, Timothy S. Hayes, Donald R. Letourneau, Thomas L. McDevitt, Anthony K. Stamper
  • Publication number: 20150004781
    Abstract: In one embodiment, the invention provides a back-end-of-line (BEOL) line fuse structure. The BEOL line fuse structure includes: a line including a plurality of grains of conductive crystalline material; wherein the plurality of grains in a region between the first end and a second end include an average grain size that is smaller than a nominal grain size of the plurality of grains in a remaining portion of the line.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Inventors: Mukta G. Farooq, Emily R. Kinser
  • Patent number: 8921975
    Abstract: A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Felix P. Anderson, Timothy H. Daubenspeck, Jeffrey P. Gambino, Timothy S. Hayes, Donald R. Letourneau, Thomas L. McDevitt, Anthony K. Stamper
  • Patent number: 8916461
    Abstract: An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Daniel C. Edelstein, Ronald G. Filippi, Naftali Eliahu Lustig, Andrew H. Simon
  • Publication number: 20140367826
    Abstract: A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Inventors: Hsueh-Chung Chen, Chiahsun Tseng, Chun-Chen Yeh, Ailian Zhao
  • Publication number: 20140349474
    Abstract: A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Inventors: Jeong Youl KIM, Ki Soo CHOI
  • Publication number: 20140332922
    Abstract: In some examples, a programmable electrical fuse includes at least one structural feature that increases a thermal gradient between an anode and a cathode of the programmable electrical fuse. For example, a device may include a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and a programmable electrical fuse overlying a portion of the electrically insulating layer. The programmable electrical fuse may include a cathode, an anode, and a conductor link connecting the cathode and the anode. The electrically insulating layer may define a first thickness between the semiconductor substrate and the cathode and a second thickness between the semiconductor substrate and the anode, and the first thickness being less than the second thickness.
    Type: Application
    Filed: May 10, 2013
    Publication date: November 13, 2014
    Applicant: Honeywell International Inc.
    Inventors: Eric E. Vogt, Paul S. Fechner, Gordon A. Shaw
  • Publication number: 20140332924
    Abstract: A structure including a first interconnect including a first line overlying a first via and a second interconnect including a second line overlying a second via. The first line and the second line are co-planar. The first interconnect comprises a first conductor, the first conductor comprises a metal silicide including titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, molybdenum silicide, tantalum silicide, or some combination thereof. The second interconnect comprises a second conductor, the second conductor comprising copper.
    Type: Application
    Filed: May 30, 2014
    Publication date: November 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 8866171
    Abstract: To provide a light-emitting element or a light-emitting device in which power is not consumed wastefully even if a short-circuit failure occurs. The present invention focuses on heat generated due to a short-circuit failure which occurs in a light-emitting element. A fusible alloy which is melted at temperature T2 by heat generated due to the short-circuit failure when the short-circuit failure occurs is used for at least one of a pair of electrodes in a light-emitting element, and a layer containing an organic composition which is melted at temperature T1 is formed on a surface of the electrode opposite to a surface facing the other electrode. The present inventors have reached a structure in which the temperature T2 is lower than temperature T3 at which the light-emitting element is damaged and the temperature T1 is lower than the temperature T2, and this structure can achieve the objects.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuo Nakamura, Satoshi Seo, Masaaki Hiroki
  • Patent number: 8865592
    Abstract: A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventors: Jiang Yan, Henning Haffner, Frank Huebinger, SunOo Kim, Richard Lindsay, Klaus Schruefer
  • Patent number: 8866256
    Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a first conductive fuse bus having a triangular-shaped portion with a bottom surface aligned along a plane substantially parallel to a surface of the semiconductor substrate. The apparatus can include a second conductive fuse bus having a bottom surface aligned along the plane, and a plurality of fuse links coupled between the triangular-shaped portion of the first conductive fuse bus and the second conductive fuse bus.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 21, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: William R. Newberry
  • Patent number: 8841208
    Abstract: An electronic fuse structure including a first Mx metal comprising a conductive cap, an Mx+1 metal located above the Mx metal, wherein the Mx+1 metal does not comprise a conductive cap, and a via, wherein the via electrically connects the Mx metal to the Mx+1 metal in a vertical orientation.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Junjing Bao, Elbert Emin Huang, Yan Zun Li, Dan Moy
  • Publication number: 20140252538
    Abstract: A method of forming an electronic fuse including forming an Mx level including a first and a second Mx metal, forming a first Mx+1 dielectric above the Mx level, forming a conductive path on a portion of the first Mx+1 dielectric, forming a second Mx+1 dielectric above the first Mx+1 dielectric and above the conductive path, the first and second Mx+1 dielectrics together form an Mx+1 level, forming a first and a second via in the Mx+1 level, the conductive path extending from the first via to the second via and partially encircling the first via, and forming a first and second Mx+1 metal in the Mx+1 level, the first via extending vertically and electrically connecting the first Mx metal to the first Mx+1 metal, and the second via extending vertically and electrically connecting the second Mx metal to the second Mx+1 metal.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Wai-Kin Li, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20140239440
    Abstract: A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Inventors: Douglas M. Reber, Mehul D. Shroff, Edward O. Travis
  • Publication number: 20140239441
    Abstract: A semiconductor device, includes: a first semiconductor layer having a first conductivity type; a pair of first electrodes arranged to be separated from each other in the first semiconductor layer; a second electrode provided on the first semiconductor layer between the pair of first electrodes with a dielectric film in between; and a pair of connection sections electrically connected to the pair of first electrodes, wherein one or both of the pair of first electrodes are divided into a first region and a second region, the first region and the second region being connected by a bridge section.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: Sony Corporation
    Inventors: Shoji Kobayashi, Yuki Yanagisawa
  • Patent number: 8803281
    Abstract: A semiconductor device has a field insulating film provided on a semiconductor substrate, and a fuse provided on the field insulating film and having a fuse trimming laser irradiation portion and fuse terminals. The semiconductor device further includes an intermediate insulating film covering the fuse, a first TEOS layer on the intermediate insulating film, an SOG layer for planarizing the first TEOS layer, a second TEOS layer on the SOG layer and on the first TEOS layer, a protective film on the second TEOS layer, and an opening portion above the fuse trimming laser irradiation portion in a region from the protective film to the first TEOS layer. A seal ring is provided on the intermediate insulating film so as to surround the opening portion. The seal ring is disposed over the fuse so as to overlap each of the fuse terminals in plan view.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 12, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Hisashi Hasegawa
  • Publication number: 20140210040
    Abstract: An electronic fuse structure having an Mx level including an Mx dielectric, a fuse line, an Mx cap dielectric above at least a portion of the Mx dielectric, and a modified portion of the Mx cap dielectric directly above at least a portion of the fuse line, where the modified portion of the Mx cap dielectric is chemically different from the remainder of the Mx cap dielectric, an Mx+1 level including an Mx+1 dielectric, a first Mx+1 metal, an Mx+1 cap dielectric above of the Mx+1 dielectric and the first Mx+1 metal, where the Mx+1 level is above the Mx level, and a first via electrically connecting the fuse line to the first Mx+1 metal.
    Type: Application
    Filed: January 28, 2013
    Publication date: July 31, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Publication number: 20140183688
    Abstract: An electronic fuse structure including an Mx level including a first Mx metal, a second Mx metal, and an Mx cap dielectric above of the first and second Mx metal, an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, and a nano-pillar located within the via and above the second Mx metal.
    Type: Application
    Filed: January 2, 2013
    Publication date: July 3, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20140127895
    Abstract: A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.
    Type: Application
    Filed: January 13, 2014
    Publication date: May 8, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gabriele Bettineschi, Uwe Seidel, Wolfgang Walter, Michael Schrenk, Hubert Werthmann
  • Publication number: 20140124891
    Abstract: A method of forming a device includes forming a silicon-containing line continuously extending between a first node and a second node. A first silicide-containing portion and a second silicide-containing portion are formed over the silicon-containing line. The first silicide-containing portion is separated from the second silicide-containing portion by a predetermined distance, and the predetermined distance is substantially equal to or less than a length of the silicon-containing line.
    Type: Application
    Filed: January 10, 2014
    Publication date: May 8, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jyun-Ying LIN, Chun-Yao KO, Ting-Chen HSU
  • Patent number: 8716071
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Li, Ping-Chuan Wang
  • Patent number: 8709931
    Abstract: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 29, 2014
    Assignee: SK Hynix Semiconductor, Inc.
    Inventor: Byung-Duk Lee
  • Publication number: 20140106559
    Abstract: A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.
    Type: Application
    Filed: December 27, 2013
    Publication date: April 17, 2014
    Applicant: International Business Machines Corporation
    Inventors: Felix P. Anderson, Timothy H. Daubenspeck, Jeffrey P. Gambino, Timothy S. Hayes, Donald R. Letourneau, Thomas L. McDevitt, Anthony K. Stamper
  • Publication number: 20140098448
    Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Brian M. Henderson, Chiew-Guan Tan, Gregory A. Uvieghara, Reza Jalilizeinali
  • Publication number: 20140091427
    Abstract: An electrical fuse is provided. The electrical fuse includes an anode formed on a substrate, a cathode formed on the substrate, a fuse link connecting the anode and the cathode to each other, a first contact formed on the anode, and a second contact formed on the cathode and arranged closer to the fuse link than the first contact.
    Type: Application
    Filed: June 25, 2013
    Publication date: April 3, 2014
    Inventors: SeongDo JEON, JinSeop SHIM, JaeWoon KIM, SungRyul BAEK, JongSoo KIM, YunHie CHOI, SuJin KIM, SungBum PARK
  • Patent number: 8689163
    Abstract: A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: April 1, 2014
    Assignees: Samsung Electronics Co., Ltd., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Dong-Yun Kim, Dong-Hoon Yeo, Hyun-Chul Shin, Kyung-Ho Kim, Byung-Tae Kang, Ju-Yong Shin, Sung-Chul Lee
  • Publication number: 20140077334
    Abstract: An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via.
    Type: Application
    Filed: September 20, 2012
    Publication date: March 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jinjing Bao, Griselda Bonilla, Samuel S. Choi, Daniel C. Edelstein, Ronald G. Filippi, Naftali Eliahu Lustig, Andrew H. Simon
  • Publication number: 20140070362
    Abstract: E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.
    Type: Application
    Filed: November 13, 2013
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda BONILLA, Kaushik CHANDA, Samuel S. CHOI, Ronald G. FILIPPI, Stephan GRUNOW, Naftali E. LUSTIG, Andrew H. SIMON