Abstract: Provided among other things is an electrical device comprising: a first component that is a semiconductor or an electrical conductor; a second component that is an electrical conductor; and a strong, heat stable junction there between including an intermetallic bond formed of: substantially (a) indium (In), tin (Sn) or a mixture thereof, and (b) substantially nickel (Ni). The junction can have an electrical contact resistance that is small compared to the resistance of the electrical device.

Abstract: Methods for etching a substrate are provided herein. In some embodiments, a method for etching a substrate disposed within a processing volume of a process chamber includes: (a) exposing a first layer disposed atop the substrate to a first gas comprising tungsten chloride (WClx) for a first period of time and at a first pressure, wherein x is 5 or 6; (b) purging the processing volume of the first gas using an inert gas for a second period of time; (c) exposing the substrate to a hydrogen-containing gas for a third period of time to etch the first layer after purging the processing volume of the first gas; and (d) purging the processing volume of the hydrogen-containing gas using the inert gas for a fourth period of time.

Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.

Abstract: A high frequency device includes: a capping layer formed on an epitaxial structure; source and drain electrodes formed on the capping layer; a multilayer insulating pattern formed on entire surfaces of the source and drain electrodes and the capping layer in a step shape; a T-shaped gate passing through the multilayer insulating pattern and the capping layer to be in contact with the epitaxial structure; and a passivation layer formed along entire surfaces of the T-shaped gate and the multilayer insulating pattern.

Abstract: A semiconductor device and a method of forming an airbridge extending from a conductive area of the semiconductor device are provided. The semiconductor device includes a device pattern formed on a semiconductor substrate, a seed layer formed on the device pattern, and an airbridge formed on the seed layer, where the airbridge includes a plated conductive material and defines an opening exposing a portion of the device pattern. The semiconductor device further includes an adhesion layer formed on the airbridge layer and extending over at least a portion of sidewalls of the opening defined by the airbridge, and an insulating layer formed on the adhesion layer, where the adhesion layer enhances adhesion of the insulating layer to the plated conductive material of the airbridge.

Abstract: A method of forming a semiconductor structure having a substrate is disclosed. The semiconductor structure includes a first layer formed in contact with the substrate. The first layer made of a first III-V semiconductor material selected from GaN, GaAs and InP. A second layer is formed on the first layer. The second layer made of a second III-V semiconductor material selected from AlGaN, AlGaAs and AlInP. An interface is between the first layer and the second layer forms a carrier channel. An insulating layer is formed on the second layer. Portions of the insulating layer and the second layer are removed to expose a top surface of the first layer. A metal feature is formed in contact with the carrier channel and the metal feature is annealed to form a corresponding intermetallic compound.

Abstract: A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.

Abstract: A method for forming a selective ohmic contact for a Group III-nitride heterojunction structured device may include forming a conductive layer and a capping layer on an epitaxial substrate including at least one Group III-nitride heterojunction layer and having a defined ohmic contact region, the capping layer being formed on the conductive layer or between the conductive layer and the Group III-nitride heterojunction layer in one of the ohmic contact region and non-ohmic contact region, and applying at least one of a laser annealing process and an induction annealing process on the substrate at a temperature of less than or equal to about 750° C. to complete the selective ohmic contact in the ohmic contact region.

Abstract: A method of producing a semiconductor transistor involving formation of an ohmic electrode on an active layer composed of a GaN-based semiconductor includes a process of forming a first layer 11 composed of tantalum nitride on an active layer 3 and a second layer 12 composed of Al layered on the first layer 11 and a process of forming ohmic electrodes 9s and 9d in ohmic contact with the active layer 3 by heat treating the first layer 11 and the second layer 12 at a temperature of from 520° C. to 600° C.

Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type first semiconductor layer, a p-type second semiconductor layer and a light emitting layer. The light emitting layer is provided between the first and second semiconductor layers, and includes a plurality of barrier layers including a nitride semiconductor and a well layer provided between the barrier layers and including a nitride semiconductor containing In. The barrier layers and the well layer are stacked in a first direction from the second semiconductor layer toward the first semiconductor layer. The well layer has a p-side interface part and an n-side interface part. Each of the p-side and the n-side interface part include an interface with one of the barrier layers. A variation in a concentration of In in a surface perpendicular to the first direction of the p-side interface part is not more than that of the n-side interface part.

Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer.

Abstract: A method for fabricating a vertical light-emitting diode (VLED) structure includes the steps of providing a carrier substrate, and forming a semiconductor structure on the carrier substrate having a p-type confinement layer, a multiple quantum well (MQW) layer in electrical contact with the p-type confinement layer configured to emit electromagnetic radiation, and an n-type confinement layer in electrical contact with the multiple quantum well (MQW) layer. The method also includes the steps of removing the carrier substrate using a laser pulse to expose an inverted surface of the n-type confinement layer, and forming a metal contact on the surface of the n-type confinement layer.

Abstract: Example embodiments are directed to a method of growing GaN single crystals on a silicon substrate, a method of manufacturing a GaN-based light emitting device using the silicon substrate, and a GaN-based light emitting device. The method of growing the GaN single crystals may include forming a buffer layer including a TiN group material or other like material on a silicon substrate, forming a nano-pattern including silicon oxide on the buffer layer, and growing GaN single crystals on the buffer layer and the nano-pattern.

Abstract: A method for fabricating a semiconductor device includes forming ohmic electrodes on a source region and a drain region of a nitride semiconductor layer, forming a low-resistance layer between an uppermost surface of the nitride semiconductor layer and the ohmic electrodes by annealing the nitride semiconductor layer, removing the ohmic electrodes from at least one of the source region and the drain region. after forming the low-resistance layer, and forming at least one of a source electrode and a drain electrode on the low-resistance layer, the at least one of a source electrode and a drain electrode having an edge, a distance between the edge and a gate electrode is longer than a distance between an edge of the low-resistance layer and the gate electrode.

Abstract: A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts.

Abstract: A method of manufacturing an optical semiconductor device includes: forming first and second optical semiconductor elements separated from each other by a separation groove on a semiconductor substrate; forming first and second electrodes containing Pt on top surfaces of the first and second optical semiconductor elements, respectively; forming a third electrode electrically connected to the first and second electrodes and preventing the third electrode from being formed in the separation groove; forming first and second Au plated layers on the first and second electrodes, respectively, by electrolytic plating, using the third electrode as a power supply layer; forming a resist covering the first and second Au plated layers by photolithography; and etching the third electrode, using the resist as a mask, to electrically separate the first electrode from the second electrode.

Abstract: Techniques for fabricating contacts on inverted configuration surfaces of GaN layers of semiconductor devices are provided. An n-doped GaN layer may be formed with a surface exposed by removing a substrate on which the n-doped GaN layer was formed. The crystal structure of such a surface may have a significantly different configuration than the surface of an as-deposited p-doped GaN layer.

Abstract: A semiconductor light-emitting element including a substrate, a laminated semiconductor layer including a light-emitting layer formed over the substrate, one electrode (111) formed over the upper face of the laminated semiconductor layer, and an other electrode formed over the exposed surface of the semiconductor layer, from which the laminated semiconductor layer is partially cut off. The one electrode (111) includes a junction layer (110) and a bonding pad electrode (120) formed to cover the junction layer. The bonding pad electrode has a maximum thickness larger than that of the junction layer, and is composed of one or two or more layers. Slopes (110c), (117c) and (119c), which are made gradually thinner toward the outer circumference, are formed in the outer circumference portions (110d) and (120d) of the junction layer and the bonding pad electrode. Also disclosed is a method for manufacturing the element and a lamp.

Abstract: A method for manufacturing a semiconductor device includes: forming a metal layer on a semiconductor layer; forming a plated layer having a pattern corresponding to a pattern of a gate bus line which couples each gate finger of a plurality of FETs on the metal layer, the pattern corresponding to the pattern of the gate bus line having a deficient part; forming a mask layer which covers the metal layer exposed in the deficient part; and patterning the metal layer by using the plated layer and the mask layer as a mask.

Abstract: An object of the present invention is to provide a light emitting device that shows high adhesion between a sealing member and a package member. A light emitting device 100 of the present invention comprises a package 20 with a recess 60 having a bottom face 20a and a side wall 20b, a light emitting element 10 mounted on the bottom face 20a of the recess 60 of the package 20, and a sealing member 40 filled in the recess 60 of the package 20, with which the light emitting element 10 is coated, wherein the package 20 contains, against the entire monomer component, from 5 to 70% by weight of potassium titanate fibers and/or wollastonite, from 10 to 50% by weight of titanium oxide, and from 15 to 85% by weight of a semiaromatic polyamide containing 20 mol % or more of an aromatic monomer, a part of the side wall 20b of the recess 60 of the package 20 has a thickness of 100 ?m or less, and the sealing member 40 is made of silicone.

Abstract: A low resistance electrode and a compound semiconductor light emitting device including the same are provided. The low resistance electrode deposited on a p-type semiconductor layer of a compound semiconductor light emitting device including an n-type semiconductor layer, an active layer, and the p-type semiconductor layer, including: a reflective electrode which is disposed on the p-type semiconductor layer and reflects light being emitted from the active layer; and an agglomeration preventing electrode which is disposed on the reflective electrode layer in order to prevent an agglomeration of the reflective electrode layer during an annealing process.

Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer.

Abstract: A method of producing a semiconductor transistor involving formation of an ohmic electrode on an active layer composed of a GaN-based semiconductor includes a process of forming a first layer 11 composed of tantalum nitride on an active layer 3 and a second layer 12 composed of Al layered on the first layer 11 and a process of forming ohmic electrodes 9s and 9d in ohmic contact with the active layer 3 by heat treating the first layer 11 and the second layer 12 at a temperature of from 520° C. to 600° C.

Abstract: A first patterned etch stop layer and a first patterned conductor layer are laminated by a dielectric material to a second patterned etch stop layer and a second patterned conductor layer. As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers, the first and second patterned etch stop layers provide an etch stop for substrate formation etch processes. In this manner, etching of the first and second patterned conductor layers is avoided insuring that impedance is controlled to within tight tolerance.

Abstract: A nitride semiconductor light emitting device includes a light emitting structure having n-type and p-type nitride semiconductor layers and an active layer formed therebetween. N-type and p-type electrodes are electrically connected to the n-type and p-type nitride semiconductors, respectively. An n-type ohmic contact layer is formed between the n-type nitride semiconductor layer and the n-type electrode and has a first layer of a material In and a second layer formed on the first layer and of a material containing W. The nitride semiconductor light emitting device has thermal stability and excellent electrical characteristics without heat treatment.

Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg alloy layer 32 which is formed of Mg and a metal selected from a group consisting of Pt, Mo, and Pd. The Mg alloy layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: A nitride-based semiconductor light-emitting device 100 includes: a GaN substrate 10 with an m-plane surface 12; a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN substrate 10; and an electrode 30 provided on the semiconductor multilayer structure 20. The electrode 30 includes a Zn layer 32 and an Ag layer 34 provided on the Zn layer 32. The Zn layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: A method for forming a silicon film may be performed using a microheater including a substrate and a metal pattern spaced apart from the substrate. The silicon film may be formed on the metal pattern by applying a voltage to the metal pattern of the microheater to heat the metal pattern and by exposing the microheater to a source gas containing silicon. The silicon film may be made of polycrystalline silicon. A method for forming a pn junction may be performed using a microheater including a substrate, a conductive layer on the substrate, and a metal pattern spaced apart from the substrate. The pn junction may be formed between the metal pattern and the conductive layer by applying a voltage to the metal pattern of the microheater to heat the metal pattern. The pn junction may be made of polycrystalline silicon.

Abstract: A nitride-based semiconductor light-emitting device 100 includes: a GaN substrate 10 with an m-plane surface 12; a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN substrate 10; and an electrode 30 provided on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: In a semiconductor device including a carbon-containing electrode and a method for fabricating the same, an electrode has a high work function due to a carbon-containing TiN layer contained therein. It is possible to provide a dielectric layer having a high permittivity and thus to reduce the leakage current by forming an electrode having a high work function. Also, sufficient capacitance of a capacitor can be secured by employing an electrode having a high work function and a dielectric layer having a high permittivity.

Abstract: Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. Here, the lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel. Thus, the use of the multi-layered transparent conductive layer can ensure transparency and conductivity, overcome a problem of contact resistance between the source and drain electrodes and a semiconductor, and improve processibility by patterning the multi-layered transparent conductive layer all at once, while deposition is performed layer by layer.

Abstract: A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer.

Abstract: To provide a method for manufacturing a semiconductor light emitting device capable of providing sufficiently low operating voltage. The method for manufacturing a semiconductor light emitting device of the present invention includes: a semiconductor laminating step of laminating a plurality of nitride semiconductor layers of to form a semiconductor laminating structure; and an electrode forming step of forming n-side electrode and p-side electrodes on the n-type and p-type semiconductor layers. In the electrode forming step, after a first metallic layer including a Ni layer constituting a part of the n-side electrode is formed on a surface of a forming region of the n-side electrode, the first metallic layer is annealed in an atmosphere containing nitrogen and oxygen.

Abstract: There are provided an ohmic electrode, which includes a contact layer made of an Al alloy and formed on a nitride-based semiconductor layer functioning as a light emitting layer, a reflective layer made of Ag metal, formed on the contact layer and having some particles in-diffused to the semiconductor layer, and a protective layer formed on the reflective layer to restrain out-diffusion of the reflective layer; a method of forming the ohmic electrode; and a semiconductor light emitting element having the ohmic electrode. The present invention has strong adhesive strength and low contact resistance since the reflective layer and the light emitting layer directly form an ohmic contact due to the interface reaction during heat treatment, and the present invention has high light reflectance and excellent thermal stability since the contact layer and the protective layer restrain out-diffusion of the reflective layer during heat treatment.

Abstract: A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.

Abstract: A semiconductor device comprising: a substrate; a terminal on the substrate's first surface; a first electrode on the first surface connected to the terminal; an electronic element on the substrate's second surface; a second electrode connected to the electronic element; a groove on the second surface leading to the second electrode; a conductive portion inside the grove connected to the second electrode's rear face; a first wiring on the first surface connected to the first electrode; a second wiring connecting the first wiring and the terminal; a stress-absorbing layer between the substrate and terminal; a land connecting the first wiring and the second wiring, the land opening a part of the stress-absorbing layer and exposing the first wiring, the land being in a region surrounded by terminals, and the land being along a straight line connecting the centers of diagonal terminals, with the region between the terminals.

Abstract: Disclosed is a method of manufacturing a through-via. The through-via manufacturing method includes forming a core-via hole in a wafer, forming a suction-via hole adjacent to the core-via hole in the wafer, forming a via core in the core-via hole, forming a polymer-via hole connected to the suction-via hole in the wafer, filling the polymer-via hole with polymer solution by creating a vacuum inside the polymer-via hole by drawing air out of the suction-via hole, and polishing the wafer such that the via core formed in the core-via hole is exposed.

Abstract: A low resistance electrode and a compound semiconductor light emitting device including the same are provided. The low resistance electrode deposited on a p-type semiconductor layer of a compound semiconductor light emitting device including an n-type semiconductor layer, an active layer, and the p-type semiconductor layer, including: a reflective electrode which is disposed on the p-type semiconductor layer and reflects light being emitted from the active layer; and an agglomeration preventing electrode which is disposed on the reflective electrode layer in order to prevent an agglomeration of the reflective electrode layer during an annealing process.

Abstract: A method for forming an electrode for Group-III nitride compound semiconductor light-emitting devices includes a step of forming a first electrode layer having an average thickness of less than 1 nm on a Group-III nitride compound semiconductor layer, the first electrode layer being made of a material having high adhesion to the Group-III nitride compound semiconductor layer or low contact resistance with the Group-III nitride compound semiconductor layer and also includes a step of forming a second electrode layer made of a highly reflective metal material on the first electrode layer.

Abstract: The present invention provides a production method for a nitride semiconductor light emitting device, which warps less after removing the substrate, and which can emit light from the side thereof; specifically, the present invention provides a production method for a nitride semiconductor light emitting device comprising: forming stacked layers by stacking at least an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a substrate in this order; forming grooves which divide the stacked layers so as to correspond to nitride semiconductor light emitting devices to be produced; filling the grooves with a sacrifice layer; and forming a plate layer on the p-type semiconductor layer and the sacrifice layer by plating.

Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.

Abstract: A manufacturing method of a semiconductor device wherein a metal pad is etched to form a trench in which a central part is concave in form, or to form a trench in the shape of a cylinder or a parallelepiped on the edge part of a metal pad. Accordingly, the contact area between a polymide isoindro quirazorindione (PIQ) or similar curable layer and the metal pad is increased and the bondability is improved. Accordingly, the technology of improving the characteristic of device by preventing the problem that the metal pad is excessively opened in a subsequent curing process and the layer of a lower portion of the metal pad is attacked is disclosed.

Abstract: A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.

Abstract: A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane.

Abstract: A series-shunt switch is provided. The switch includes a PIN diode having an input electrical terminal, an output electrical terminal and a thermal terminal. The thermal terminal is configured to provide continuity of diode thermal ground with respect to a circuit thermal ground node.

Abstract: Provided is a method for preparing a substrate for growing gallium nitride and a gallium nitride substrate. The method includes performing thermal cleaning on a surface of a silicon substrate, forming a silicon nitride (Si3N4) micro-mask on the surface of the silicon substrate in an in situ manner, and growing a gallium nitride layer through epitaxial lateral overgrowth (ELO) using an opening in the micro-mask. According to the method, by improving the typical ELO, it is possible to simplify the method for preparing the substrate for growing gallium nitride and the gallium nitride substrate and reduce process cost.

Abstract: A method of manufacturing a semiconductor device provides a semiconductor device with a gallium-nitride-based semiconductor structure that allows long-term stable operation without degradation in device performance. After formation of an insulation film on a surface other than on a ridge surface, an oxygen-containing gas such as O2, O3, NO, N2O, or NO2 is supplied to oxidize a p-type GaN contact layer from the surface and to thereby form an oxide film on the surface of the p-type GaN contact layer. Then, a p-type electrode that establishes contact with the p-type GaN contact layer is formed by evaporation or sputtering on the oxide film and on the insulation film. Heat treatment is subsequently performed at temperatures between 400 and 700° C. in an atmosphere containing a nitrogen-containing gas such as N2 or NH3 or an inert gas such as Ar or He.

Abstract: An LED array chip (2), which is one type of a semiconductor light emitting device, includes an array of LEDs (6), a base substrate (4) supporting the array of the LEDs (6), and a phosphor film (48). The array of LEDs (6) is formed by dividing a multilayer epitaxial structure including a light emitting layer into a plurality of portions. The phosphor film (48) covers an upper surface of the array of the LEDs (6) and a part of every side surface of the array of LEDs (6). Here, the part extends from the upper surface to the light emitting layer.

Abstract: Disclosed are an apparatus and a method for manufacturing a semiconductor device. The apparatus comprises a transfer chamber for transferring a substrate, a first process chamber connected to the transfer chamber configured to form a TiSiN layer on the substrate, a second process chamber connected to the transfer chamber configured to form a tantalum layer on the TiSiN layer, and a third process chamber connected to the transfer chamber configured to form a copper seed layer on the tantalum layer. After forming the TiSiN layer, a portion of the TiSiN layer in contact with the lower metal interconnection is etched, the tantalum layer is formed on the TiSiN layer in contact with the exposed lower metal interconnection, the copper seed layer is formed on the tantalum layer, and then the copper interconnection is formed on the copper seed layer. In this way, the copper interconnection can be efficiently formed.

Abstract: A light emitting diode is disclosed. The diode includes a silicon carbide substrate having a first conductivity type, a first gallium nitride layer above the SiC substrate having the same conductivity type as the substrate, a superlattice on the GaN layer formed of a plurality of repeating sets of alternating layers selected from among GaN, InGaN, and AlInGaN, a second GaN layer on the superlattice having the same conductivity type as the first GaN layer, a multiple quantum well on the second GaN layer, a third GaN layer on the multiple quantum well, a contact structure on the third GaN layer having the opposite conductivity type from the substrate and the first GaN layer, an ohmic contact to the SiC substrate, and an ohmic contact to the contact structure.