Abstract: The nitride-based semiconductor device includes a carrier traveling layer 1 composed of non-doped AlxGa1-xN (0?X<1); a barrier layer 2 formed on the carrier traveling layer 1 and composed of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the carrier traveling layer 1; a threshold voltage control layer 3 formed on the barrier layer 2 and composed of a non-doped semiconductor having a lattice constant equal to that of the carrier traveling layer 1; and a carrier inducing layer 4 formed on the threshold voltage control layer 3 and composed of a non-doped or n-type semiconductor having a lattice constant smaller than that of the carrier traveling layer 1. The nitride-based semiconductor device further includes a gate electrode 5 formed in a recess structure, a source electrode 6 and a drain electrode 7.

Abstract: Methods for producing nanostructures, particularly Group III-V semiconductor nanostructures, are provided. The methods include use of novel Group III and/or Group V precursors, novel surfactants, oxide acceptors, high temperature, and/or stable co-products. Related compositions are also described. Methods and compositions for producing Group III inorganic compounds that can be used as precursors for nanostructure synthesis are provided. Methods for increasing the yield of nanostructures from a synthesis reaction by removal of a vaporous by-product are also described.

Abstract: A Ga source gas and a nitrogen source gas are supplied to form a GaN channel layer on a semiconductor substrate. Next, a temperature is lowered while supplying at least the nitrogen source gas. Next, the Ga source gas is not supplied and an Al source gas and the nitrogen source gas are supplied. Next, the temperature is raised while not supplying the Al source gas and the Ga source gas and supplying the nitrogen source gas. Next, the Al source gas and the nitrogen source gas are supplied and at least one of the Ga source gas and an In source gas is supplied to form a AlxGayInzN barrier layer (x+y+z=1, x>0, y?0, z?0, y+z>0).

Abstract: A surface treatment method for a semiconductor layer includes growing a first layer on a substrate in a growth reactor, the first layer consisting of one of gallium nitride, aluminum gallium nitride and indium aluminum nitride; growing a second layer of gallium nitride on a surface of the first layer, the gallium nitride of the second GaN layer having a composition ratio of gallium to nitrogen larger than 2; taking the substrate out of the growth reactor after growing the second layer; and removing the second layer after taking the substrate out of the growth reactor.

Abstract: A method for preparing semiconductor nanocrystals includes reacting one or more semiconductor nanocrystal precursors in a liquid medium in the presence of a boronic compound at a reaction temperature resulting in semiconductor nanocrystals. Semiconductor nanocrystals are also disclosed.

Abstract: A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having a top surface; (ii) refining the initial sub-assembly into a first trench-cut intermediate sub-assembly by removing material to form an upper tier of a trench extending downward from the top surface of the trench-defining layer, the upper tier of the trench including two lateral trench surfaces and a bottom trench surface; and (iii) refining the first trench-cut intermediate sub-assembly into a second trench-cut intermediate sub-assembly by selectively removing material in a downwards direction starting from the bottom surface of the trench to form a lower tier of the trench, with the selective removal of material leaving at least a first defect blocking member in the lower tier of the trench.

Abstract: A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer co-doped with silicon (Si) and germanium Ge and a method of making the same is disclosed. The HEMT device includes a substrate with epitaxial layers over the substrate. An n-type gallium nitride (GaN) layer is disposed on an interface surface of the epitaxial layers, wherein the n-type GaN layer is co-doped with silicon (Si) and germanium (Ge) that provide a carrier concentration of at least 1×1020 cm?3 and a root mean square (RMS) surface roughness that is no greater than 2 nm for a contact surface of the n-type GaN layer that is interfaced with the interface surface of the epitaxial layers.

Abstract: A method for fabrication a light emitting diode (LED) includes forming alternating material layers on an LED structure, formed on a substrate, to form a reflector on a back side opposite the substrate. A handle substrate is adhered to a stressor layer deposited on the reflector. The LED structure is separated from the substrate using a spalling process to expose a front side of the LED structure.

Abstract: Embodiments of the present disclosure generally relate to a semiconductor device including layers of group III-V semiconductor materials. In one embodiment, the semiconductor device includes a phosphorous containing layer deposited on a silicon substrate, wherein a lattice mismatch between the phosphorous containing layer and the silicon substrate is less than 5%, a group III-V compound nucleation layer deposited on the phosphorous containing layer at a first temperature, the group III-V compound nucleation layer having a first thickness, a group III-V compound transition layer deposited on the group III-V compound nucleation layer at a second temperature higher than the first temperature, the group III-V compound transition layer having a second thickness larger than the first thickness, and the group III-V compound nucleation layer is different from the group III-V compound transition layer, and an active layer deposited on the group III-V compound transition layer.

Abstract: Methods for producing nanostructures, particularly Group III-V semiconductor nanostructures, are provided. The methods include use of novel Group III and/or Group V precursors, novel surfactants, oxide acceptors, high temperature, and/or stable co-products. Related compositions are also described. Methods and compositions for producing Group III inorganic compounds that can be used as precursors for nanostructure synthesis are provided. Methods for increasing the yield of nanostructures from a synthesis reaction by removal of a vaporous by-product are also described.

Abstract: Semiconductor structures are fabricated to include strained epitaxial layers exceeding a predicted critical thickness thereof.

Abstract: A system for manufacturing semiconductor epitaxy structure includes a deposition apparatus, a curvature monitor system and a control unit. The deposition apparatus is configured for sequentially depositing a buffer layer, a first epitaxy layer, an insertion layer, a second epitaxy layer on a substrate. The curvature monitor system is configured for monitoring a curvature value of the semiconductor epitaxy structure. The control unit is configured for controlling the deposition apparatus to stop depositing the buffer layer, the first epitaxy layer, the insertion layer and the second epitaxy layer according to the curvature value of the semiconductor epitaxy structure measured by the curvature monitor system. The above-mentioned system for manufacturing semiconductor epitaxy structure is able to effectively control the strain of the semiconductor epitaxy structure during growth. A method for manufacturing semiconductor epitaxy structure is also disclosed.

Abstract: A nitride semiconductor light-emitting device is formed of an n-type nitride semiconductor layer, a trigger layer, a V-pit expanding layer, a light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The light-emitting layer has a V-pit formed therein. The trigger layer is made of a nitride semiconductor material having a lattice constant different from that of a material that forms an upper surface of the n-type nitride semiconductor layer. The V-pit expanding layer is made of a nitride semiconductor material having a lattice constant substantially identical to that of the material that forms the upper surface of the n-type nitride semiconductor layer, and the V-pit expanding layer has a thickness of 5 nm or more and 5000 nm or less.

Abstract: A nanostructure includes a highly conductive microcrystalline layer, a bipolar nanowire, and another layer (18, 30). The highly conductive microcrystalline layer includes a microcrystalline material and a metal. The bipolar nanowire has one end attached to the highly conductive microcrystalline layer and another end attached to the other layer.

Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a p-type layer, and a light emitting unit provided between the n-type layer and the p-type layer and including barrier layers and well layers. At least one of the barrier layers includes first and second portion layers. The first portion layer is disposed on a side of the n-type layer. The second portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the first portion layer. At least one of the well layers includes third and fourth portion layers. The third portion layer is disposed on a side of the n-type layer. The fourth portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the third portion layer.

Abstract: A Schottky barrier diode is provided with: an n-type semiconductor layer including Ga2O3-based compound semiconductors with n-type conductivity; and a Schottky electrode layer which is in Schottky-contact with the n-type semiconductor layer. An n? -type semiconductor layer, which has a relatively low electron carrier concentration and is brought into Schottky-contact with the Schottky electrode layer, and an n+ semiconductor layer, which has a higher electron carrier concentration than the n semiconductor layer, are formed in the n-type semiconductor layer.

Abstract: A method of making a semiconductor nanocrystal can include contacting an M-containing compound with an X donor having the formula X(Y(R)3)3, where X is a group V element and Y is a group IV element.

Abstract: According to one embodiment, an electronic component includes a device having a plurality of electrodes; a lead electrically connected to each of the plurality of electrodes; a first resin body sealing the device and a portion of the lead; and a first conductive body connected to the leads and contactable with a second conductive body.

Abstract: A device and a method of forming a continuous polycrystalline Ge film having crystalline Ge islands is provided that includes depositing an amorphous Ge (a-Ge) layer on a substrate, oxidizing the top surface of the a-Ge layer to form a GeOx layer, depositing a seed layer of Al on the GeOx layer and catalyzing the Al seed layer, where Ge mass transport is generated from the underlying a-Ge layer to the Al seed layer through the GeOx layer by thermal annealing, where a continuous polycrystalline Ge film having crystalline Ge islands is formed on the Al seed layer.

Abstract: A group III nitride semiconductor light-emitting element provided with: a semiconductor layer obtained by laminating a first semiconductor layer of a first conduction type, a light-emitting layer, and a second semiconductor layer of an opposite second conduction type; a first electrode connected to the first semiconductor layer; and a second electrode provided on the surface of the second semiconductor layer; the light-emitting layer including a first gallium indium nitride layer of a first indium composition, disposed on a side opposite the light extraction direction; a second gallium indium nitride layer of a second indium composition less than the first, disposed on the light extraction direction side from the first gallium indium nitride layer; and an intermediate layer containing a material of a smaller lattice constant than the materials constituting the first and second gallium indium nitride layers, provided between the first and second gallium indium nitride layers.

Abstract: A semiconductor device includes a substrate having a hexagonal crystalline structure and a (0001) surface, and conductive films on the surface of the substrate. The conductive films include a first conductive film and a second conductive film located above the first conductive film with respect to the surface, wherein the first conductive film has a crystalline structure which does not have a plane that has a symmetry equivalent to the symmetry of atomic arrangement in the surface of the substrate, the second conductive film has a crystalline structure having at least one plane that has a symmetry equivalent to the symmetry of atomic arrangement in the surface of the substrate, and the second conductive film is polycrystalline and has a grain size no larger than 15 ?m.

Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.

Abstract: The plant is suitable to produce a semiconductor film (8) having a desired thickness and consisting substantially of a compound including at least one element for each of the groups 11, 13, and 16 of the periodic classification of elements. The plant comprises an outer case (1) embedding a chamber (2) divided into one deposition zone (2a) and one evaporation zone (2b), which are separated by a screen (3) interrupted by at least one cylindrical transfer member provided with actuation means rotating about its axis (5). To the deposition zone (2a) a magnetron device (7) is associated, for the deposition by sputtering of at least one element for each of the groups 11 and 13 on the side surface (?) of the cylindrical member that is in the deposition zone (2a). To the evaporation zone (2b) a cell (10) for the evaporation of at least one element of the group 16 is associated, and such an evaporation zone (2b) houses a substrate (8a) on which the film (8) is produced.

Abstract: An AlGaN/GaN.HEMT includes, a compound semiconductor lamination structure; a p-type semiconductor layer formed on the compound semiconductor lamination structure; and a gate electrode formed on the p-type semiconductor layer, in which Mg being an inert element of p-GaN is introduced into both sides of the gate electrode at the p-type semiconductor layer, and introduced portions of Mg are inactivated.

Abstract: A nitride-based semiconductor device of the present invention includes: a nitride-based semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5°; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x?0, y?0, and z?0) layer 26. The electrode 30 includes a Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: A method of manufacturing a photo-semiconductor device that has a photoconductive semiconductor film provided with electrodes and formed on a second substrate, the semiconductor film being formed by epitaxial growth on a first semiconductor substrate different from the second substrate, the second substrate being also provided with electrodes, and the electrodes of the second substrate and the electrodes of the photoconductive semiconductor film being held in contact with each other.

Abstract: A method for forming a selective ohmic contact for a Group III-nitride heterojunction structured device may include forming a conductive layer and a capping layer on an epitaxial substrate including at least one Group III-nitride heterojunction layer and having a defined ohmic contact region, the capping layer being formed on the conductive layer or between the conductive layer and the Group III-nitride heterojunction layer in one of the ohmic contact region and non-ohmic contact region, and applying at least one of a laser annealing process and an induction annealing process on the substrate at a temperature of less than or equal to about 750° C. to complete the selective ohmic contact in the ohmic contact region.

Abstract: A compound semiconductor device is manufactured by forming an III-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the III-nitride compound semiconductor device structure including a GaN alloy on GaN and a channel region arising near an interface between the GaN alloy and the GaN. One or more silicon-containing insulating layers are formed on a surface of the III-nitride compound semiconductor device structure adjacent the GaN alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the GaN alloy. A region of GaN is regrown in the contact opening, and the regrown region of GaN is doped exclusively with Si out-diffused from the one or more silicon-containing insulating layers to form an ohmic contact which is doped only with the Si out-diffused from the one or more silicon-containing insulating layers.

Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer.

Abstract: An object of the present invention is to provide a Group III nitride semiconductor epitaxial substrate, a Group III nitride semiconductor element, and a Group III nitride semiconductor free-standing substrate, which have good crystallinity, with not only AlGaN, GaN, and GaInN the growth temperature of which is 1050° C. or less, but also with AlxGa1-xN having a high Al composition, the growth temperature of which is high; a Group III nitride semiconductor growth substrate used for producing these, and a method for efficiently producing those. The present invention provides a Group III nitride semiconductor growth substrate comprising a crystal growth substrate including a surface portion composed of a Group III nitride semiconductor which contains at least Al, and a scandium nitride film formed on the surface portion are provided.

Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.

Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT).

Abstract: A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel structure. A first gate structure may be formed on the germanium containing fin structures. A III-V fin structure may then be formed on the sidewalls of the mandrel structure. The mandrel structure may be removed. A second gate structure may be formed on the III-V fin structure.

Abstract: Example embodiments are directed to a method of growing GaN single crystals on a silicon substrate, a method of manufacturing a GaN-based light emitting device using the silicon substrate, and a GaN-based light emitting device. The method of growing the GaN single crystals may include forming a buffer layer including a TiN group material or other like material on a silicon substrate, forming a nano-pattern including silicon oxide on the buffer layer, and growing GaN single crystals on the buffer layer and the nano-pattern.

Abstract: Provided is an epitaxial substrate for a semiconductor device, which has excellent schottky contact characteristics that are stable over time. The epitaxial substrate for a semiconductor device includes a base substrate, a channel layer formed of a first group III nitride containing at least Ga and having a composition of Inx1Aly1Gaz1N (x1+y1+z1=1), and a barrier layer formed of a second group III nitride containing at least In and Al and having a composition of Inx2Aly2Gaz2N (x2+y2+z2=1), wherein the barrier layer has tensile strains in an in-plane direction, and pits are formed on a surface of the barrier layer at a surface density of 5×107/cm2 or more and 1×109/cm2 or less.

Abstract: The invention relates to a method for equipping a process chamber in an apparatus for depositing at least one layer on a substrate held by a susceptor in the process chamber, process gases being introduced into the process chamber through a gas inlet element, in particular by means of a carrier gas, the process gases decomposing into decomposition products in the chamber, in particular on hot surfaces, the decomposition products comprising the components that form the layer. In order to improve the apparatus so that thick multi-layer structures can be deposited reproducibly in process steps that follow one another directly, it is proposed that a material is selected for the surface facing the process chamber at least of the wall of the process chamber that is opposite the susceptor, the optical reflectivity, optical absorptivity and optical transmissivity of which respectively correspond to those of the layer to be deposited during the layer growth.

Abstract: A multilayer construction is disclosed. The multilayer construction includes a -II-VI semiconductor layer (110)x and a Si3N4 layer (120) disposed directly on the II-VI semiconductor layer. To improve the adhesion of the Si3N4 layer (120) a native oxide on the II-VI semiconductor layer is removed.

Abstract: A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling structure is disposed adjacent to one of the first layer and the second layer. In some cases, the light coupling structure is disposed adjacent to the first layer. An orifice formed in the light coupling structure extends to the first layer. An electrode formed in the orifice is in electrical communication with the first layer.

Abstract: A method of manufacturing an IGZO active layer includes depositing ions including In, Ga, and Zn from a first target, and depositing ions including In from a second target having a different atomic composition from the first target. The deposition of ions from the second target may be controlled to adjust an atomic % of In in the IGZO layer to be about 45 atomic % to about 80 atomic %.

Abstract: A method of fabricating an (Al,Ga,In)N laser diode, comprising depositing one or more III-N layers upon a growth substrate at a first temperature, depositing an indium containing laser core at a second temperature upon layers deposited at a first temperature, and performing all subsequent fabrication steps under conditions that inhibit degradation of the laser core, wherein the conditions are a substantially lower temperature than the second temperature.

Abstract: A Gallium Nitride (GaN) series of devices—transistors and diodes are disclosed—that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional interdigitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.

Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.

Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.

Abstract: A method of fabricating a rare earth silicide gate electrode on III-N material grown on a silicon substrate includes growing a single crystal stress compensating template on a silicon substrate. The template is substantially crystal lattice matched to the surface of the silicon substrate. A single crystal GaN structure is grown on the surface of the template and substantially crystal lattice matched to the template. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched to the GaN structure. A single crystal monoclinic rare earth oxide dielectric layer is grown on the active layer of III-N material and a single crystal rare earth silicide gate electrode is grown on the dielectric layer, the silicide. Relative portions of the gadolinium metal and the silicon are adjusted during deposition so they react to form rare earth silicide during deposition.

Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.

Abstract: A reactive evaporation method for forming a group III-V amorphous material attached to a substrate includes subjecting the substrate to an ambient pressure of no greater than 0.01 Pa, and introducing active group-V matter to the surface of the substrate at a working pressure of between 0.05 Pa and 2.5 Pa, and group III metal vapor, until an amorphous group III-V material layer is formed on the surface.

Abstract: A method for fabricating a high quality freestanding nonpolar and semipolar nitride substrate with increased surface area, comprising stacking multiple films by growing the films one on top of each other with different and non-orthogonal growth directions.

Abstract: Embodiments relate to growing an epitaxy gallium-nitride (GaN) layer on a porous silicon (Si) substrate. The porous Si substrate has a larger surface area compared to non-porous Si substrate to distribute and accommodate stress caused by materials deposited on the substrate. An interface adjustment layer (e.g., transition metal silicide layer) is formed on the porous silicon substrate to promote growth of a buffer layer. A buffer layer formed for GaN layer may then be formed on the silicon substrate. A seed-layer for epitaxial growth of GaN layer is then formed on the buffer layer.

Abstract: When a p-layer 4 composed of GaN is maintained at ordinary temperature and TNO is sputtered thereon by an RF magnetron sputtering method, a laminated TNO layer 5 is in an amorphous state. Then, there is included a step of thermally treating the amorphous TNO layer in a reduced-pressure atmosphere where hydrogen gas is substantially absent to thereby crystallize the TNO layer. At the sputtering, an inert gas is passed through together with oxygen gas, and volume % of the oxygen gas contained in the gas passed through is 0.10 to 0.15%. In this regard, oxygen partial pressure is 5×10?3 Pa or lower. The temperature of the thermal treatment is 500° C. for about 1 hour.

Abstract: A method of making a sputtering target includes providing a backing structure, and forming a copper indium gallium sputtering target material on the backing structure by spray forming.