Conductive Macromolecular Conductor (including Metal Powder Filled Composition) Patents (Class 438/610)
  • Patent number: 10329446
    Abstract: The present invention relates to formulations for ink based on nanoparticles of silver. In particular, the present invention concerns formulations of ink based on nanoparticles of silver, which inks are stable, have an improved conductivity and are adapted for the area of serigraphy.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: June 25, 2019
    Assignee: Genes'ink SA
    Inventors: Nicolas Delpont, Corinne Versini, Virginie El Qacemi, Gregoire Staelens, Louis-Dominique Kauffman
  • Patent number: 10065861
    Abstract: A solar energy conversion niobium oxynitride microcone and a method of the synthesis and use of niobium oxynitride microcones are provided. The material is useful for solar energy conversion, optics, photocatalysis, electrochromics, sensors and biomedical applications. According to one embodiment, Nb205 microcones are formed by anodization of (1M NaF and 1 wt. % HF electrolyte ?40 V ?20 min), they were annealed in ammonia gas to allow their doping with nitrogen. Nitridation of the micro cones shifts the absorption edge from 450 nm for the oxide form to 777 nm for the oxynitride form.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: September 4, 2018
    Assignee: The American University in Cairo
    Inventors: Basamat S. Shaheen, Nageh K. Allam
  • Patent number: 9923201
    Abstract: Provided herein are nanostructures for lithium ion battery electrodes and methods of fabrication. In some embodiments, a nanostructure template coated with a silicon coating is provided. The silicon coating may include a non-conformal, more porous layer and a conformal, denser layer on the non-conformal, more porous layer. In some embodiments, two different deposition processes, e.g., a PECVD layer to deposit the non-conformal layer and a thermal CVD process to deposit the conformal layer, are used. Anodes including the nanostructures have longer cycle lifetimes than anodes made using either a PECVD or thermal CVD method alone.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: March 20, 2018
    Assignee: Amprius, Inc.
    Inventors: Weijie Wang, Zuqin Liu, Song Han, Jonathan Bornstein, Constantin Ionel Stefan
  • Patent number: 9716227
    Abstract: In various embodiments, a method of forming a graphene structure is provided. The method may include forming a body including at least one protrusion, and forming a graphene layer at an outer peripheral surface of the at least one protrusion.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: July 25, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans-Joachim Schulze, Peter Irsigler, Guenther Ruhl
  • Patent number: 9640430
    Abstract: A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 2, 2017
    Assignee: NXP USA, INC.
    Inventors: Douglas M. Reber, Mehul D. Shroff
  • Patent number: 9484302
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device comprises a workpiece including a conductive feature disposed in a first insulating material and a second insulating material disposed over the first insulating material, the second insulating material having an opening over the conductive feature. A graphene-based conductive layer is disposed over an exposed top surface of the conductive feature within the opening in the second insulating material. A carbon-based adhesive layer is disposed over sidewalls of the opening in the second insulating material. A carbon nano-tube (CNT) is disposed within the patterned second insulating material over the graphene-based conductive layer and the carbon-based adhesive layer.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: November 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Hsiang-Huan Lee, Hsien-Chang Wu
  • Patent number: 9355916
    Abstract: A method manufactures a semiconductor device which allows nanocarbon materials, such as high-quality graphene and carbon nanotube to be used. The method of manufacturing the semiconductor device comprises forming on a substrate a wiring structure including wires of nanocarbon material; forming on the wiring structure an element structure including a semiconductor element; and interconnecting the wires of the wiring structure and the semiconductor element of the element structure.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: May 31, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Daiyu Kondo, Shintaro Sato, Naoki Yokoyama, Motonobu Sato
  • Patent number: 9219008
    Abstract: A graphene patterning method for forming a graphene of predetermined pattern includes bringing a patterning member in which a catalyst metal layer of the predetermined pattern is formed into contact with a substrate having a graphene oxide film. In bringing the patterning member, the catalyst metal layer is brought into contact with the graphene oxide film.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: December 22, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takashi Matsumoto, Yusaku Kashiwagi
  • Patent number: 9163813
    Abstract: A lamp (1) has one or more LED's (2), supported above an open structure (7). The lamp (1) is made from thermoplastic material and has a base (3) including threads (4) and a lower contact (5). A thermoplastic body (6) of larger diameter is located above the base and has an open structure portion (7) preferably shaped as a truncated inverted and open cone. An upper part of the cone supports a circuit board (8) with a laminar form that supports the light emitting diodes (2). A upper semispherical element (9) is located over the body (6) and forms a light diffuser. An upper center of the base (3) has an internal electronic circuit (10) for connecting to a power source. The LED lamp with the open structure eases installation, has lower weight and cost, allows easy recycling and provides greater security for users.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: October 20, 2015
    Inventors: Fernando Roberto Sanchez, Gilmar Aparecido de Souza
  • Patent number: 9131610
    Abstract: A layer of material having a low thermal conductivity is coated over a substrate. A film of conductive ink is then coated over the layer of material having the low thermal conductivity, and then sintered. The film of conductive ink does not absorb as much energy from the sintering as the film of conductive ink coated over the layer of material having the low thermal conductivity. The layer of material having the low thermal conductivity may be a polymer, such as polyimide.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: September 8, 2015
    Assignees: PEN Inc., Ishihara Chemical Co., Ltd.
    Inventors: Zvi Yaniv, Mohshi Yang, Peter B. Laxton
  • Patent number: 9123894
    Abstract: A method of manufacturing an electronic device, comprising a layer of semiconductive material and at least one insulative feature arranged to interrupt the layer of semiconductive material, comprises: providing a layer of semiconductive material, and a layer of compressible material supporting the layer of semiconductive material; and forming the or each insulative feature by a method comprising displacing a respective selected portion of the layer of semiconductive material towards the compressible material so as to compress compressible material under the or each displaced portion and separate at least partly the or each displaced portion from undisplaced semiconductive material.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: September 1, 2015
    Assignee: Pragmatic Printing Ltd.
    Inventors: Aimin Song, Stephen Whitelegg, Yanming Sun, Shiwei Lin
  • Patent number: 9040364
    Abstract: A method of creating a semiconductor device is disclosed. An end of a carbon nanotube is unzipped to provide a substantially flat surface. A contact of the semiconductor device is formed. The substantially flat surface of the carbon nanotube is coupled to the contact to create the semiconductor device. An energy gap in the unzipped end of the carbon nanotube may be less than an energy gap in a region of the carbon nanotube outside of the unzipped end region.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith, George S. Tulevski
  • Patent number: 9034750
    Abstract: A method of fabricating a solder-on-pad structure is provided. The method may include providing a substrate with a pad, coating a solder bump maker including a first resin and a solder powder on the substrate, heating the solder bump maker to a temperature lower than a melting point of the solder powder to aggregate the solder powder on the pad, and removing the first resin.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: May 19, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kwang-Seong Choi, Ho-eun Bae, Hyun-cheol Bae, Yong Sung Eom, Su Jeong Jeon
  • Publication number: 20150123091
    Abstract: A transparent electrode is provided with a nitrogen-containing layer, an electrode layer having silver as the main component thereof, and an aluminum intermediate layer, wherein the aluminum intermediate layer is in contact with the nitrogen-containing layer and the electrode layer and sandwiched between the nitrogen-containing layer and the electrode layer. The nitrogen-containing layer is formed by using a compound containing a nitrogen atom. The effective unshared electron pair content [n/M] of this compound satisfies “3.9×10?3?[n/M]”, where n is the number of unshared electron pair(s) not involved in aromaticity and not coordinated to metal, among unshared electron pair(s) owned by the nitrogen atom, and M is molecular weight.
    Type: Application
    Filed: April 17, 2013
    Publication date: May 7, 2015
    Inventors: Takeshi Hakii, Hiroshi Ishidai, Toshiyuki Kinoshita, Kazuhiro Yoshida, Takatoshi Tsujimura, Minako Ono
  • Publication number: 20150104936
    Abstract: The invention provides a novel conductive film and a multilayered conductive structure, comprising a plurality of metal nanowires arranged in clusters and having an average aspect ratio of least 100,000, optionally decorated by metal nanoparticles. It is also disclosed a process for preparation of a conductive film comprising metal nanowires by surfactant/template assisted method which involves the use of a precursor solution based on surfactant (such as CTAB), metal precursor (such as HAuC14 and AgN03) and reducing agent (such as metal borohydride or sodium ascorbate).
    Type: Application
    Filed: February 28, 2013
    Publication date: April 16, 2015
    Inventors: Gil Markovich, Daniel Azulai, Tatyana Levi-Belenkova, Hagit Gilon, Fernando De La Vega, Ayala Kabla
  • Patent number: 9006095
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece including a conductive feature formed in a first insulating material and a second insulating material disposed over the first insulating material. The second insulating material has an opening over the conductive feature. The method includes forming a graphene-based conductive layer over an exposed top surface of the conductive feature within the opening in the second conductive material, and forming a carbon-based adhesive layer over sidewalls of the opening in the second insulating material. A carbon nano-tube (CNT) is formed in the patterned second insulating material over the graphene-based conductive layer and the carbon-based adhesive layer.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Ming Han Lee, Hsiang-Huan Lee, Hsien-Chang Wu
  • Patent number: 8999819
    Abstract: The present invention relates generally to dendritic metal structures and devices including them. The present invention also relates particularly to methods for making dendritic metal structures without the use of solid electrolyte materials. In one aspect, a method for constructing a dendritic metal structure includes providing a substrate having a surface and a cathode disposed on the surface; providing an anode comprising a metal; and disposing a liquid on the surface of the substrate, such that the liquid is in electrical contact with the anode and the cathode; and then applying a bias voltage across the cathode and the anode sufficient to grow the dendritic metal structure extending from the cathode. The methods described herein can be used to grow dendritic metal electrodes, which can be useful in devices such as LEDs, touchscreens, solar cells and photodetectors.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: April 7, 2015
    Assignee: Arizona Board of Regents, A Body Corporate of the State of Arizona Acting For on Behalf of Arizona State University
    Inventors: Michael N. Kozicki, Minghan Ren
  • Publication number: 20150061133
    Abstract: According to one embodiment, a semiconductor device using a graphene film comprises a catalytic metal layer formed on a groundwork substrate includes a contact via, and a multilayered graphene layer formed in a direction parallel with a surface of the substrate. The catalytic metal layer is formed to be connected to the contact via and covered with an insulation film except one side surface. The multilayered graphene layer is grown from the side surface of the catalytic metal layer which is not covered with the insulation film.
    Type: Application
    Filed: February 10, 2014
    Publication date: March 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsunobu ISOBAYASHI, Akihiro KAJITA, Tadashi SAKAI
  • Patent number: 8956905
    Abstract: Solid state thermoelectric energy conversion devices can provide electrical energy from heat flow, creating energy, or inversely, provide cooling through applying energy. Thick film methods are applied to fabricate thermoelectric device structures using microstructures formed through deposition and subsequent thermal processing conditions. An advantageous coincidence of material properties makes possible a wide variety of unique microstructures that are easily applied for the fabrication of device structures in general. As an example, a direct bond process is applied to fabricate thermoelectric semiconductor thick films on substrates by printing and subsequent thermal processing to form unique microstructures which can be densified. Bismuth and antimony are directly bonded to flexible nickel substrates.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: February 17, 2015
    Assignee: Berken Energy LLC
    Inventor: Ronald R Petkie
  • Publication number: 20150035149
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate provided with a lower interconnect layer formed thereon, and having a device region and a mark formation region, a CNT via structure formed in the device region such that it contacts the lower interconnect layer, a first mark formed in the mark formation region, formed by embedding carbon nanotubes, and formed in the same layer as the CNT via structure, a second mark formed in the mark formation region of the semiconductor substrate, formed with no carbon nanotubes, and formed in the same layer as the CNT via structure and the first mark, and an interconnect layer formed on the CNT via structure and the first and second marks, and electrically connected to the CNT via structure.
    Type: Application
    Filed: January 14, 2014
    Publication date: February 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Akihiro KAJITA, Atsunobu ISOBAYASHI, Tatsuro SAITO, Tadashi SAKAI, Taishi ISHIKURA
  • Patent number: 8940628
    Abstract: A method of manufacturing an interconnection of an embodiment includes: forming a via which penetrates an interlayer insulation film on a substrate; forming an underlying film in the via; removing the underlying film on a bottom part of the via; forming a catalyst metal inactivation film on the underlying film; removing the inactivation film on the bottom part of the via; forming a catalyst metal film on the bottom part of the via on which the inactivation film is removed; performing a first plasma treatment and a second plasma treatment using a gas not containing carbon on a member in which the catalyst metal film is formed; forming a graphite layer on the catalyst film after the first and second plasma treatment processes; and causing a growth of a carbon nanotube from the catalyst film on which the graphite layer is formed.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Tadashi Sakai
  • Publication number: 20150021554
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.
    Type: Application
    Filed: October 8, 2014
    Publication date: January 22, 2015
    Inventors: Michael R. Seacrist, Vikas Berry
  • Publication number: 20150014853
    Abstract: A method of forming an edge-doped graphene channel is described. The method involves selectively removing graphene from a graphene layer on a substrate in the presence of a dopant to form graphene channels. The dopant forms bonds with carbon atoms on the edge of the graphene such that the graphene channels are edge doped. An article of manufacture is also provided which includes a substrate layer, one or more edge-doped graphene channels on the substrate layer and a layer of an etch mask material on and coextensive with the one or more graphene channels. An article of manufacture is also provided which includes a substrate layer and one or more edge-doped graphene channels on the substrate layer, wherein each of the one or more the graphene channels has a width less than 100 nm and a carrier density greater than 5×1012 cm?3.
    Type: Application
    Filed: December 20, 2013
    Publication date: January 15, 2015
    Applicant: Harper Laboratories, LLC
    Inventors: Kevin BRENNER, Romeil SANDHU
  • Patent number: 8933496
    Abstract: A method and apparatus for making analog and digital electronics which includes a composite including a squishable material doped with conductive particles. A microelectromechanical systems (MEMS) device has a channel made from the composite, where the channel forms a primary conduction path for the device. Upon applied voltage, capacitive actuators squeeze the composite, causing it to become conductive. The squishable device includes a control electrode, and a composite electrically and mechanically connected to two terminal electrodes. By applying a voltage to the control electrode relative to a first terminal electrode, an electric field is developed between the control electrode and the first terminal electrode. This electric field results in an attractive force between the control electrode and the first terminal electrode, which compresses the composite and enables electric control of the electron conduction from the first terminal electrode through the channel to the second terminal electrode.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: January 13, 2015
    Assignee: Massachusetts Institute of Technology
    Inventors: Vladimir Bulovic, Jeffrey H. Lang, Sarah Paydavosi, Annie I-Jen Wang, Trisha L. Andrew, Apoorva Murarka, Farnaz Niroui, Frank Yaul, Jeffrey C. Grossman
  • Patent number: 8932950
    Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: January 13, 2015
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xinpeng Wang, Haiyang Zhang
  • Patent number: 8912047
    Abstract: A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: December 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Khalil Hosseini, Hans-Joachim Schulze
  • Patent number: 8906804
    Abstract: Methods for depositing nanomaterial onto a substrate are disclosed. Also disclosed are compositions useful for depositing nanomaterial, methods of making devices including nanomaterials, and a system and devices useful for depositing nanomaterials.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: December 9, 2014
    Assignee: QD Vision, Inc.
    Inventors: Seth Coe-Sullivan, Maria J. Anc, LeeAnn Kim, John E. Ritter, Marshall Cox, Craig Breen, Vladimir Bulovic, Ioannis Kymissis, Robert F. Praino, Jr.
  • Publication number: 20140346674
    Abstract: A structure including an Mx level including a first Mx metal, a second Mx metal, and a third Mx metal abutting and electrically connected in sequence with one another, the second Mx metal including graphene, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via, the via electrically connects the third Mx metal to the Mx+1 metal in a vertical orientation.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Andrew T. Kim, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20140284798
    Abstract: A graphene wiring has a substrate a catalyst layer on the substrate a first graphene sheet layer on the catalyst layer and a second graphene sheet layer on the first graphene layer. The second graphene layer comprises multilayer graphene sheets. The multilayer graphene sheets are intercalated with an atomic or molecular species.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi Sakai, Masayuki Katagiri, Yuichi Yamazaki, Mariko Suzuki
  • Publication number: 20140284802
    Abstract: According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another.
    Type: Application
    Filed: September 10, 2013
    Publication date: September 25, 2014
    Inventors: Atsuko SAKATA, Masayuki Kitamura, Makoto Wada, Masayuki Katagiri, Yuichi Yamazaki, Akihiro Kajita
  • Publication number: 20140284799
    Abstract: A semiconductor device has a substrate a lower layer wiring on the substrate, an interlayer dielectric on the lower layer wiring having a contact hole, a catalyst metal layer at the bottom of the contact hole having catalyst metal particles, multi-walled carbon nanotubes on the catalyst metal layer passing through the contact hole, and an upper layer wiring on the multi-walled carbon nanotubes. The multi-walled carbon nanotubes are intercalated with an atomic or molecular species.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki KATAGIRI, Tadashi SAKAI, Hisao MIYAZAKI, Yuichi YAMAZAKI, Mariko SUZUKI
  • Patent number: 8835299
    Abstract: A sintered connection is formed by pressing a semiconductor die against a substrate with a dried sintering material interposed between the substrate and the semiconductor die, the dried sintering material having sintering particles and a solvent. The substrate is heated to a temperature below a sintering temperature of the dried sintering material while the semiconductor die is pressed against the substrate to form local sinter connections between adjacent ones of the sintering particles. The local sinter connections collectively provide a stable joint that fixes the semiconductor die to the substrate prior to sintering. A sintered connection is then formed between the semiconductor die and the substrate from the dried sintering material, after the stable joint is formed.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: September 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Roland Speckels, Lars Böwer, Nicolas Heuck, Niels Oeschler
  • Publication number: 20140252615
    Abstract: According to one embodiment, a semiconductor device includes a wiring, a first insulation film, an underlayer deactivation layer, an underlayer, a catalyst layer and a carbon nanotube. The first insulation film is formed on the wiring and includes a hole which exposes the wiring. The underlayer deactivation layer is formed on the first insulation film at a side surface of the hole, and exposes the wiring at a bottom surface of the hole. The underlayer is formed on an exposed surface of the wiring at the bottom surface of the hole and on the underlayer deactivation layer at the side surface of the hole. The catalyst layer is formed on the underlayer at the bottom surface and the side surface of the hole. The carbon nanotube extends from the catalyst layer at the bottom surface of the hole, and fills the hole.
    Type: Application
    Filed: August 2, 2013
    Publication date: September 11, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro SAITO, Makoto WADA, Atsunobu ISOBAYASHI
  • Publication number: 20140235049
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece including a conductive feature formed in a first insulating material and a second insulating material disposed over the first insulating material. The second insulating material has an opening over the conductive feature. The method includes forming a graphene-based conductive layer over an exposed top surface of the conductive feature within the opening in the second conductive material, and forming a carbon-based adhesive layer over sidewalls of the opening in the second insulating material. A carbon nano-tube (CNT) is formed in the patterned second insulating material over the graphene-based conductive layer and the carbon-based adhesive layer.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 21, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Yi Yang, Ming Han Lee, Hsiang-Huan Lee, Hsien-Chang Wu
  • Publication number: 20140225260
    Abstract: A method of producing an electro-optic device includes providing a substructure, depositing a network of nanowires on the substructure, depositing a sol-gel solution on the network of nanowires and the substructure, and removing solvent from the sol-gel solution to provide fusing material that causes junctions of nanowires within the network of nanowires to fuse together to reduce electrical sheet resistance of the network of nanowires. An electro-optic device includes a sub-structure, a network of nanowires deposited on the substructure, and a plurality of nanoparticles attached to the network of nanowires. The plurality of nanoparticles fuse junctions of overlapping nanowires together to reduce electrical sheet resistance of the network of nanowires.
    Type: Application
    Filed: September 13, 2012
    Publication date: August 14, 2014
    Applicant: The Regents of the University of California
    Inventors: Yang Yang, Rui Zhu
  • Publication number: 20140220773
    Abstract: In some embodiments, the present disclosure pertains to methods of preparing graphene nanoribbons from a graphene film associated with a meniscus, where the method comprises patterning the graphene film while the meniscus acts as a mask above a region of the graphene film, and where the patterning results in formation of graphene nanoribbons from the meniscus-masked region of the graphene film. Additional embodiments of the present disclosure pertain to methods of preparing wires from a film associated with a meniscus, where the method comprises patterning the film while the meniscus acts as a mask above a region of the film, and where the patterning results in formation of a wire from the meniscus-masked region of the film. Additional embodiments of the present disclosure pertain to chemical methods of preparing wires from water-reactive materials.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 7, 2014
    Applicant: William Marsh Rice University
    Inventors: James M. Tour, Vera Abramova, Alexander Slesarev
  • Publication number: 20140199829
    Abstract: A graphene patterning method for forming a graphene of predetermined pattern includes bringing a patterning member in which a catalyst metal layer of the predetermined pattern is formed into contact with a substrate having a graphene oxide film. In bringing the patterning member, the catalyst metal layer is brought into contact with the graphene oxide film.
    Type: Application
    Filed: January 13, 2014
    Publication date: July 17, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Takashi MATSUMOTO, Yusaku KASHIWAGI
  • Publication number: 20140196781
    Abstract: A method of manufacturing a thick-film electrode comprising steps of: (a) applying a conductive paste onto a substrate comprising, (i) 100 parts by weight of a conductive powder, wherein the conductive powder is 16 to 49 weight percent based on the weight of the conductive paste; (ii) 0.5 to 10 parts by weight of a metal additive comprising bismuth (Bi); (iii) 1 to 25 parts by weight of a glass frit; and (iv) 50 to 300 parts by weight of an organic medium; and (b) firing the applied conductive paste to form the thick-film electrode, wherein thickness of the thick-film electrode is 0.5 to 15 ?m.
    Type: Application
    Filed: January 15, 2013
    Publication date: July 17, 2014
    Applicant: E.I. DU PONT DE NEMOURS AND COMPANY
    Inventors: Kazushige ITO, Kazutaka OZAWA
  • Publication number: 20140187033
    Abstract: A method of manufacturing an interconnection of an embodiment includes: forming a via which penetrates an interlayer insulation film on a substrate; forming an underlying film in the via; removing the underlying film on a bottom part of the via; forming a catalyst metal inactivation film on the underlying film; removing the inactivation film on the bottom part of the via; forming a catalyst metal film on the bottom part of the via on which the inactivation film is removed; performing a first plasma treatment and a second plasma treatment using a gas not containing carbon on a member in which the catalyst metal film is formed; forming a graphite layer on the catalyst film after the first and second plasma treatment processes; and causing a growth of a carbon nanotube from the catalyst film on which the graphite layer is formed.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuichi YAMAZAKI, Tadashi Sakai
  • Publication number: 20140183736
    Abstract: A laminated graphene device is demonstrated as a cathode. In one example the devices include organic photovoltaic devices. The measured properties demonstrate work-function matching via contact doping. Devices and method shown also provide increased power conversion efficiency due to transparency. These findings indicate that flexible, light-weight all carbon devices, such as solar cells, can be constructed using graphene as the cathode material.
    Type: Application
    Filed: March 8, 2012
    Publication date: July 3, 2014
    Applicant: The Trustees of Columbia University in the City of New York
    Inventors: Marshall Cox, Ioannis Kymissis, Alon Gorodetsky, Melinda Y. Han, Colin P. Nuckolls, Philip Kim
  • Publication number: 20140179045
    Abstract: A transparent conductive electrode stack containing a work function adjusted carbon-containing material is provided. Specifically, the transparent conductive electrode stack includes a layer of a carbon-containing material and a layer of a work function modifying material. The presence of the work function modifying material in the transparent conductive electrode stack shifts the work function of the layer of carbon-containing material to a higher value for better hole injection into the OLED device as compared to a transparent conductive electrode that includes only a layer of carbon-containing material and no work function modifying material.
    Type: Application
    Filed: February 3, 2014
    Publication date: June 26, 2014
    Applicant: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, James B. Hannon, Ning Li, Satoshi Oida, George S. Tulevski, Devendra K. Sadana
  • Publication number: 20140179097
    Abstract: A method for filling features in a layer over a substrate is provided. A dispersion of nanoparticles less than 5 nm is placed on the layer. The liquid is frozen by lowering a temperature of the liquid. The frozen liquid is sublimated by decreasing pressure and subsequently heating the frozen liquid, wherein the nanoparticles are not sublimated.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Diane J. HYMES, Stephen M. SIRARD
  • Patent number: 8735274
    Abstract: Electrodes formed in a partial surface area of a semiconductor substrate and distal ends of conductive nanotubes bristled on a surface of a growth substrate, are bombarded with rare gas plasma. The distal ends of the conductive nanotubes bombarded with the rare gas plasma are brought into contact with the electrodes bombarded with the rare gas plasma to fix the conductive nanotubes to the electrodes. The growth substrate is separated from the semiconductor substrate in such a manner that the conductive nanotubes fixed to the electrodes remain on the electrodes formed on the semiconductor substrate.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Taisuke Iwai
  • Publication number: 20140138829
    Abstract: The present invention relates to an interconnection structure and a method for fabricating the same. According to the present invention, cavities are formed between the interconnection dielectric by using a sacrificial layer, carbon nanotubes are used as the interconnection material for local interconnection between via holes, graphene nanoribbons are used as the interconnection material for metal lines, and cavities are included in the interconnection dielectric. In addition, the conventional CMOS BEOL Cu interconnection technique is applied to the intermediate interconnection level and the global interconnection level. In this way, the high parasitic resistance and parasitic capacitance in the Cu interconnection technique, which may occur when the local interconnection is relatively small in size, can be effectively overcome.
    Type: Application
    Filed: December 31, 2011
    Publication date: May 22, 2014
    Applicant: SHANGHAI IC R&D CENTER CO., LTD.
    Inventors: Yuhang Zhao, Xiaoxu Kang
  • Patent number: 8723049
    Abstract: A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: May 13, 2014
    Assignee: Tessera, Inc.
    Inventors: Charles G. Woychik, Kishor Desai, Ilyas Mohammed, Terrence Caskey
  • Publication number: 20140120714
    Abstract: A method of creating a semiconductor device is disclosed. An end of a carbon nanotube is unzipped to provide a substantially flat surface. A contact of the semiconductor device is formed. The substantially flat surface of the carbon nanotube is coupled to the contact to create the semiconductor device. An energy gap in the unzipped end of the carbon nanotube may be less than an energy gap in a region of the carbon nanotube outside of the unzipped end region.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith, George S. Tulevski
  • Patent number: 8691609
    Abstract: Gas sensor materials and methods are disclosed for preparing and using the same to produce gas sensor structures. Also disclosed are gas sensor structures and systems that employ these disclosed materials. A gas sense-enhancing metal such as platinum may be added to a gas sensitive metal oxide material in a manner that more highly disperses the added platinum than conventional methods so as to more effectively utilize the platinum at a lower concentration, thus achieving a more cost effective solution. An ink vehicle may also be used for deposition of a gas sensitive material (e.g. on the surface of integrated circuit) that is formulated to allow “burn-out” of ink vehicle components at relatively low temperatures as compared to conventional ink vehicles.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: April 8, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Peter Smith, Jane Blake, Leon Cavanagh, Raymond Speer
  • Publication number: 20140087552
    Abstract: The present disclosure relates to microstructure devices, in which a conductive pattern is formed on the basis of a conductive polymer material. In order to avoid the deposition and processing of the sacrificial materials and reduce a negative influence of the lithography process on sensitive conductive polymer materials a one-layer patterning sequence is proposed, in which a trench pattern is formed in a dielectric material that is subsequently filled with the conductive polymer material.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 27, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventors: Vincenza Di Palma, Andrea Di Matteo, Luigi Giuseppe Occhipinti
  • Patent number: 8669131
    Abstract: Gas sensor materials and methods are disclosed for preparing and using the same to produce gas sensor structures. Also disclosed are gas sensor structures and systems that employ these disclosed materials. A gas sense-enhancing metal such as platinum may be added to a gas sensitive metal oxide material in a manner that more highly disperses the added platinum than conventional methods so as to more effectively utilize the platinum at a lower concentration, thus achieving a more cost effective solution. An ink vehicle may also be used for deposition of a gas sensitive material (e.g. on the surface of integrated circuit) that is formulated to allow “burn-out” of ink vehicle components at relatively low temperatures as compared to conventional ink vehicles.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 11, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Peter Smith, Jane Blake, Leon Cavanagh, Raymond Speer
  • Publication number: 20140057428
    Abstract: A layer of material having a low thermal conductivity is coated over a substrate. A film of conductive ink is then coated over the layer of material having the low thermal conductivity, and then sintered. The film of conductive ink does not absorb as much energy from the sintering as the film of conductive ink coated over the layer of material having the low thermal conductivity. The layer of material having the low thermal conductivity maybe a polymer, such as polyimide.
    Type: Application
    Filed: November 7, 2013
    Publication date: February 27, 2014
    Applicant: APPLIED NANOTECH HOLDINGS, INC.
    Inventors: Zvi Yaniv, Mohshi Yang, Peter B. Laxton