Abstract: An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising one or more of these substrates.

Abstract: The present invention is directed to methods for making electronic devices with a thin anisotropic conducting layer interface layer formed between a substrate and an active device layer that is preferably patterned conductive layer. The interface layer preferably provides Ohmic and/or rectifying contact between the active device layer and the substrate and preferably provides good adhesion of the active device layer to the substrate. The active device layer is preferably fashioned from a nanoparticle ink solution that is patterned using embossing methods or other suitable printing and/or imaging methods. The active device layer is preferably patterned into an array of gate structures suitable for the fabrication of thin film transistors and the like.

Abstract: A process for fabricating ohmic contacts in a field-effect transistor includes the steps of: thinning a semiconductor layer forming recessed portions in the semiconductor layer; depositing ohmic contact over the recessed portions; and heating the deposited ohmic contacts. The field-effect transistor comprises a layered semiconductor structure which includes a first group III nitride compound semiconductor layer doped with a charge carrier, and a second group III nitride compound semiconductor layer positioned below the first layer, to generate an electron gas in the structure. After the heating step the ohmic contacts communicate with the electron gas. As a result, an excellent ohmic contact to the channel of the transistor is obtained.

Abstract: Multilayer thin-film electronics are manufactured at high speed, even while the various component functions are manufactured separately under conditions tailored to optimize component performance and yield. Each function or group of functions is fabricated on a separate flexible substrate. These flexible substrates are bonded to each other using adhesive films that are anisotropic electrical conductors or optical light guides. The bonding is performed by laminating the flexible substrates to each other in a continuous process, using the anisotropic conductor as the bonding layer.

Abstract: A method for a binder-free manufacturing a nanostructured porous film, e.g. for use in solar cells, includes the steps of preparing a suspension of semi-conducting nanometer-sized particles in a volatile suspending agent (21), depositing the particle suspension on a conducting substrate, removing the suspending agent by evaporation (31), thereby leaving a particle layer on said substrate and compressing (P) the deposited particle layer for mechanical and electrical interconnection.

Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.

Abstract: A solid electrolytic capacitor that comprises an anode that contains a valve-action metal (e.g., tantalum, niobium, and the like) and a dielectric film overlying the anode is provided. The capacitor also comprises a protective coating overlying the dielectric film, wherein the protective coating contains a relatively insulative, resinous material. For example, in one embodiment, the resinous material can be a drying oil, such as olive oil, linseed oil, tung oil, castor oil, soybean oil, shellac, and derivatives thereof. The capacitor also comprises a conductive polymer coating overlying the protective coating. As a result of the present invention, it has been discovered that a capacitor can be formed that can have a relatively low leakage current, dissipation factor, and equivalents series resistance.

Abstract: A microelectronic assembly includes composite conductive elements, each incorporating a core and a coating of a low-melting conductive material. The composite conductive elements interconnect microelectronic elements. At the normal operating temperature of the assembly, the low-melting conductive material melts, allowing the cores and microelectronic elements to move relative to one another and relieve thermally-induced stress.

Abstract: A multilayer circuit board, in which a plurality of insulating layers and a plurality of conductive layers, each of which includes a conductive pattern, have been laminated, includes an insulating layer, a conductive compound, and a conductive pattern. The insulating layer has a trench. The conductive compound is located in the trench. The conductive pattern adjoins the trench and is electrically connected to the conductive compound. The conductive pattern and the conductive compound make up a conductive wire that has a higher current-carrying capacity than the conductive pattern.

Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.

Abstract: A conductive adhesive agent of the invention contains an elution preventing film-forming agent 4, which becomes reactive after electric continuity through a conductive particle 3 appeared in the conductive adhesive agent when a binder resin 2 is being hardened, to thereby form an elution preventing film 5 on a surface of the conductive particle 3. By using this conductive adhesive agent, the packaging structure is made migration resistant and sulfurization resistant.

Abstract: In a method for mounting an electronic part on a mounting substrate in that projection electrodes provided on the electronic part are welded by fusion to join connection terminals provided on the mounting substrate, the flux paste includes a base flux and metal grains having diameters smaller than the diameters of projection electrodes and having a thickness so as to form a space between the flux paste and the electronic part when the electronic part is mounted on the mounting substrate and the flux paste is arranged on the mounting substrate. A resin is sealed in the space formed between the electronic part and the mounting substrate after the projection electrodes are joined to the connection terminals.

Abstract: An improved method for determining endpoint of a time division multiplexed process by monitoring an identified region of a spectral emission of the process at a characteristic process frequency. The region is identified based upon the expected emission spectra of materials used during the time division multiplexed process. The characteristic process frequency is determined based upon the duration of the steps in the time division multiplexed process. Changes in the magnitude of the monitored spectra indicate the endpoint of processes in the time division multiplexed process and transitions between layers of materials.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: A metal processing method is provided for growing a polycrystalline film by preferably chemical vapor deposition (CVD) from a suitable precursor gas or gases on a substrate which has been coated with seeds, preferably of nanocrystal size, of the metal material. The nanocrystal seeds serve as a template for the structure of the final polycrystalline film. The density of the seeds and the thickness of the grown polycrystalline film determine the grain size of the polycrystalline film at the surface of said film. CVD onto the seeds to produce the polycrystalline film avoids the recrystallization step generally necessary for the formation of a polycrystalline film, and thus allows for the growth of polycrystalline films at reduced temperatures.

Abstract: The formation of microelectronic structures in trenches and vias of an integrated circuit wafer are described using nanocrystal solutions. A nanocrystal solution is applied to flood the wafer surface. The solvent penetrates the trench recesses within the wafer surface. In the process, nanocrystals dissolved or suspended in the solution are carried into these regions. The solvent volatilizes more quickly from the wafer plateaus as compared to the recesses causing the nanocrystals to become concentrated in the shrinking solvent pools within the recesses. The nanocrystals become stranded in the dry trenches. Heating the wafer to a temperature sufficient to sinter or melt the nanocrystals results in the formation of bulk polycrystalline domains. Heating is also carried out concurrently with nanocrystals solution deposition. Copper nanocrystals of less than about 5 nanometers are particularly well suited for formation of interconnects at temperatures of less than 350 degrees Celsius.

Abstract: The disclosed invention relates to materials and processes for creating particle-enhanced bumps on electrical contact surfaces through stencil or screen printing processes. The materials are mixtures of conductive ink, conductive paste, or conductive adhesive and conductive hard particles (104). The process involves depositing the mixture (108) onto electrical contact surfaces by stencil printing, screen printing, or other dispensing techniques (110). In another embodiment, the ink, paste, or adhesive is first stenciled or screen printed and the particles are then applied on top of the ink, paste, or adhesive deposit. Once cured (114), the deposition provides a hard, electrical contact bump on the contact surface with a rough, conductive, sandpaper-like surface that can be easily connected to an opposing contact surface without any further surface preparation of either surface.

Abstract: A conductor pattern is constructed to prevent corners from peeling and raising off a substrate. The conductor pattern has a spiral configuration and includes straight lines and corners connected to the straight lines. The bottom surface cross-sectional width of the conductor pattern is smaller than the top surface cross-sectional width thereof. Moreover, the bottom surface cross-sectional width of the corner is larger than the bottom surface cross-sectional width of the straight line.

Abstract: Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.

Abstract: The present invention concerns the field of solid state capacitors and relates particularly to massed production methods for manufacturing solid state capacitors.

Abstract: A package to be mounted with semiconductor chips has a heat-radiating substrate having a thickness of smaller than 0.4 mm of a Cu—Mo composite as prepared by impregnating from 30 to 40% by mass of copper (Cu) melt into a green compact of molybdenum. The heat-radiating substrate is produced by preparing an Mo green compact through isostatic molding, mounting Cu on the Mo green compact, heating it to thereby impregnate copper into the Mo green compact to give a Cu—Mo composite, and rolling the Cu—Mo composite into a sheet substrate. In the isostatic molding process, at least two or more plates.

Abstract: The reactive element is introduced to the surface of the metal substrate in the form of an oxide powder and the aluminide-type coating is then formed.

Abstract: A process of making an electrode-to-electrode bond structure includes a step of forming a resin coating on a first bonding object having a first electrode portion in a manner such that the resin coating covers the first electrode portion. Then, an opening is formed in the resin coating to expose the first electrode portion. Then, the opening is filled with a metal paste containing a metal and a resin component. Then, the first bonding object is placed on a second bonding object having a second electrode portion in a manner such that the metal paste filled in the opening faces the second electrode portion while the resin coating contacts the second bonding object. Finally, heat-treatment is performed to cause the first electrode portion and the second electrode portion to be electrically connected with each other via the metal while causing the resin coating to harden.

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a conductive trace and an insulative base, wherein the chip includes a conductive pad, the conductive trace includes a bumped terminal, the bumped terminal includes a cavity that extends through the insulative base, and the insulative base contacts the conductive trace on a side opposite the chip, then forming a through-hole that extends through the insulative base and exposes the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, an insulative adhesive that attaches the chip to the conductive trace or an encapsulant that encapsulates the chip fills the cavity and provides compressible mechanical support for the bumped terminal.

Abstract: An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in a LOC arrangement. Alternately, a connector may contact a portion of the conductive trace to make contact therewith.

Abstract: A method for fabricating multi-cell solar devices using thermal spray deposition techniques to spray metal powder directly on solar cells and on the backing upon which solar cells are assembled, to form collection grid lines, bus bars, electrodes and interconnections between solar cells.

Abstract: A conductive adhesive agent of the invention contains an elution preventing film-forming agent 4, which becomes reactive after electric continuity through a conductive particle 3 appeared in the conductive adhesive agent when a binder resin 2 is being hardened, to thereby form an elution preventing film 5 on a surface of the conductive particle 3. By using this conductive adhesive agent, the packaging structure is made migration resistant and sulfurization resistant.

Abstract: A light-emitting element comprising a transparent electrode, a light-emitting layer, and a back electrode, on a substrate, wherein the light-emitting layer comprises photoluminescent metal oxide nanoparticles having an average particle size of 1 to 50 nm; and a method of producing the same.

Abstract: The present semiconductor element comprises a semiconductor substrate, a wiring pad formed thereon, a layer of barrier metal formed thereon, an intermetallic compound Ag3Sn formed thereon, and a protruded electrode consisting of low-melting metal formed thereon. In addition, a fabricating method of a semiconductor element comprises the steps of forming a wiring pad on a semiconductor substrate, forming a layer of barrier metal thereon, forming a metallic layer containing Ag thereon, forming a layer of low-melting metal containing Sn thereon, and melting the layer of low-melting metal containing Sn to form a protruded electrode and simultaneously to form an intermetallic compound Ag3Sn at an interface between the metallic layer containing Ag and the layer of low-melting metal containing Sn. Thus, with Pb-free solder, a semiconductor element of high reliability can be obtained.

Abstract: A method for selectively doping an organic semiconductor 1material in the region of a contact area 0.1formed between a contact and the organic semiconductor material disposed thereon includes introducing the dopant with the aid of nanoparticles, the nanoparticles being disposed in a manner adjoining the contact area and, as a result, only a very narrow region of the organic semiconductor material being doped. The field increase effected by the nanoparticles results in a further reduction of the contact resistance.

Abstract: A fine pitch wafer bumping process comprises: providing a wafer that has a plurality of contact pads exposed by a passivation layer formed on the surface of the wafer, wherein an under bump metal (UBM) is formed respectively on each contact pad; on the surface of the wafer, forming a first mask film having a plurality of first openings that expose respectively the under bump metals (UBM); filling a first solder material respectively in the first openings; reflowing the first solder material into a plurality of solder posts; on the first mask film, forming a second mask film having a plurality of second openings that respectively expose the first openings; filling a second solder material respectively in the second openings; reflowing the second solder material and the first solder posts; removing the first and second mask films; and reflowing the first and second solder posts to form a plurality of bumps.

Abstract: Visible light LEDs are produced having a layer of conjugated polymer which is cast directly from solution or formed as a gel-processed admixture with a carrier polymer. The LEDs can be formed so as to emit polarized light.

Abstract: A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low k nanopore/nanofoam dielectric material adjacent the conductive line ends.

Abstract: Process for producing electrical connections on the surface of a semiconductor package containing an integrated-circuit chip and having metal electrical-connection regions on the surface of the package, consisting of: covering these connection regions with a first metal layer forming an anti-diffusion barrier; covering this first layer with an anti-oxidation second metal layer; and depositing a metal solder drop or solder ball on the second metal layer. The solder drop comprises an addition of metal particles in suspension which contain at least one of the metals of the first metal layer so as to produce a precipitate comprising these additional metal particles and at least partly the metal of the second metal layer, the precipitate remaining in suspension in the solder drop.

Abstract: A simple and reliable method of providing a vertical interconnect between thin-film microelectronic devices is provided. In said method, a tool tip is used to make a notch in a vertical interconnect area of two organic electrically conducting areas separated from each other by an organic electrically insulating area. The method is used in the manufacture of integrated circuits consisting substantially of organic materials.

Abstract: A conductive adhesive agent of the invention contains an elution preventing film-forming agent 4, which becomes reactive after electric continuity through a conductive particle 3 appeared in the conductive adhesive agent when a binder resin 2 is being hardened, to thereby form an elution preventing film 5 on a surface of the conductive particle 3. By using this conductive adhesive agent, the packaging structure is made migration resistant and sulfurization resistant.

Abstract: A method of manufacturing an electrical interconnection of a semiconductor device produces an erosion protecting plug in a contact hole to protect a selected portion of an interlayer dielectric layer when the interlayer dielectric layer is being etched to form a recess for a conductive line. The contact hole is formed in the interlayer dielectric layer. The contact hole is filled with an organic material to form the erosion protecting plug. The organic material is a photoresist material or an organic polymer. A photoresist pattern is formed for exposing the erosion protecting plug and a portion of the interlayer dielectric layer adjacent to the erosion protecting plug. A recess which extends down to the contact hole is formed by etching the portion of the interlayer dielectric layer which is exposed by the photoresist pattern. The erosion protecting plug and the photoresist pattern are then removed. A conductive line filling the recess and a contact filling the contact hole are then formed.

Abstract: An improved wear resistant bump contact is produced by the inclusion of small particles of hard materials in the conductive material of the contact bump, preferably by co-deposition at the time of electroplating of the bump bulk material. Desirable attributes of the small particles of hard material include small particle size, hardness greater than the hardness of the bulk material of the contact bump, compatibility with the plating conditions, and electrical conductivity. Nitride, borides, silicides, carbides are typical interstitial compounds suitable for use in satisfying these desirable attributes. In one preferred example, a nickel bulk material and silicon carbide particles are utilized. In one variation, the bump of metal-particle co-deposited material is coated by a thin cap layer of noble, non-oxidizing metal to prevent electrical erosion by arcing as contact is made and broken from the pad. Rhodium and ruthenium are suitable metals and can be electrodeposition over the composite bump structure.

Abstract: A method is proposed for bonding a BGA (Ball Grid Array) package to a circuit board without causing the collapsing of the BGA package against the circuit board. The proposed method is characterized in the use of two groups of solder balls of different reflow collapse degrees, which are arranged in an interspersed manner among each other in the ball grid array. In one embodiment, the first group of solder balls are homogenously made of a solder material of a specific melting point; and the second group of solder balls each include an outer portion and a core portion, with the outer portion having substantially the same melting point as the first group of solder balls, and the core portion being greater in melting point than the outer portion. In another embodiment, the second group of solder balls are greater in melting point than the first group of solder balls.

Abstract: An improved method of growing a thin film in gaseous phase maintaining a uniform thickness and uniform electric properties such as resistivity, etc. over the whole surface of the film, and an apparatus for growing a thin film in gaseous phase adapted to conducting the above method.

Abstract: A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers.

Abstract: The present invention provides apparatus, systems, and methods related to the manufacture of integrated circuits. Specifically, embodiments of the present invention include apparatus designed to provide thorough and reliable fluid mixture for gases used in a semiconductor processing system. In one embodiment of the invention, the gas mixing apparatus comprises a gas mixer housing having a gas inlet, a fluid flow channel, and a gas outlet. The fluid flow channel is fluidly coupled to a plurality of gas sources. The majority of the gas mixture occurs in the fluid flow channel which comprises one or more fluid separators for separating the gas into two or more gas portions and one or more fluid collectors for allowing the gas portions to collide with each other to mix the gas portions. This separation and collection of the gas portions results in a thoroughly mixed gas.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: The formation of microelectronic structures in trenches and vias of an integrated circuit wafer are described using nanocrystal solutions. A nanocrystal solution is applied to flood the wafer surface. The solvent penetrates the trench recesses within the wafer surface. In the process, nanocrystals dissolved or suspended in the solution are carried into these regions. The solvent volatilizes more quickly from the wafer plateaus as compared to the recesses causing the nanocrystals to become concentrated in the shrinking solvent pools within the recesses. The nanocrystals become stranded in the dry trenches. Heating the wafer to a temperature sufficient to sinter or melt the nanocrystals results in the formation of bulk polycrystalline domains. Heating is also carried out concurrently with nanocrystals solution deposition. Copper nanocrystals of less than about 5 nanometers are particularly well suited for formation of interconnects at temperatures of less than 350 degrees Celcius.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a photoresist mask is patterned over the metal layer. The metal layer is etched and the portion of the metal layer not masked with the photoresist is removed. In this manner, additional metal can be formed on the pad site using only one additional mask step, and the thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: A semiconductor memory device comprises a semiconductor substrate, a first conducting layer formed above the main surface of the semiconductor substrate, a second conducting layer formed above the first conducting layer through a first insulating layer and connected to the first conducting layer through a first via-conductor formed in a first contact hole formed in the first insulating layer, and a third conducting layer formed beneath the second conducting layer through a second insulating layer and connected to the second conducting layer through a second via-conductor formed in a second contact hole formed in the second insulating layer, in which an angle formed by a tangent to an inner wall of the first contact hole and a normal to the first conducting layer at a portion of the first conducting layer at which the first contact hole is in contact with the first conducting layer, is larger than an angle formed by a tangent to an inner wall of the second contact hole and a normal to the third conducting laye

Abstract: An electronic device that is equipped with a plurality of bonding pads positioned on the device for making electrical interconnections and electrically conductive composite bumps adhered to the bonding pads wherein the bumps are formed of a composite material consisting of a thermoplastic polymer and at least about 30 volume percent of conductive metal particles based on the total volume of the metal particles and the thermoplastic polymer. The present invention is also directed to a method of making electrical interconnections to an electronic device by pressing a plurality of composite bumps of a polymeric based material against a substrate having an electrically conductive surface by mechanical means under a sufficient temperature and/or a sufficient pressure.

Abstract: Conductive interconnections are formed by depositing an adhesive material, made up of ferromagnetic particles dispersed within a matrix material, on a semiconductor substrate, such as an electronic component, and applying a magnetic field between an exposed surface of the adhesive material and an attached surface of the adhesive material (abutting the semiconductor substrate), such that a plurality of the ferromagnetic particles move and align within the matrix material under the influence of the magnetic field. One method of the present invention comprises depositing the adhesive material on a contact site of a first electronic component. A second electronic component having a contact site is aligned over the adhesive material and a magnetic field is applied between the first electronic component and the second electronic component.

Abstract: In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed.