Abstract: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.

Abstract: Water-soluble electrically conductive polymers and a composition comprising such polymers are provided. Also, an electrically conductive layer or film formed from the composition, and articles comprising the electrically conductive layer or film are provided. The electrically conductive polymers according to the present disclosure have one or more hydrophilic side chains. Hydrophilic side chains are covalently bonded to the conductive polymers, which allow the polymer to be stable at high temperature. Thus, the stability of electrical conductivity is prolonged. Depending on the concentration of hydrophilic side chains, the conductivity may be changed. The hydrophilic side chains provide a successful way to fabricate a ductile film exhibiting tunable conductivity. Furthermore, high levels of surface-resistance uniformity can be achieved in the field of coating technology that uses eco-friendly water-based solvents to uniformly and quickly coat the conductive polymer on to plastic film surfaces.

Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells.

Abstract: A process for fabricating a semiconductor package which includes using an exothermically active nanoparticle paste to join an electrode of a semiconductor die to a support body.

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.

Abstract: Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings corresponding to the contact pads of the circuit pattern, has an interposer layer sandwiched between them. The interposer layer includes randomly distributed mutually isolated conductive columns of spherical particles embedded in an elastomeric material, wherein the interposer layer is subjected to a compressive force from pressure exerted upon an underside surface of the semiconductor die. The compressive force deforms the interposer layer causing the conductive columns of spherical particles to electrically connect the contact pads of the circuit pattern with the corresponding bump pad landings of the package substrate.

Abstract: The invention relates to an illuminant (40) comprising a standardised connection socket (42) and a cover (50) consisting of a light-permeable material defining an inner chamber (52). A light chip arrangement (10; 110) comprising at least one semiconductor structure (14; 114) is contacted between contact regions (48a, 48b) of at least two supply lines (44a, 44b).

Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.

Abstract: An aggregate structure of carbon fibers, organized by a plurality of carbon fibers, includes, an aggregate of the carbon fibers aligned in a lengthwise direction, in which a density of the carbon fibers at one side end is different from a density of the carbon fibers at the other side end.

Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive thick film composition for use in a solar cell device.

Abstract: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Abstract: A Cu—Mo substrate 10 according to the present invention includes: a Cu base 1 containing Cu as a main component; an Mo base having opposing first and second principal faces 2a, 2b and containing Mo as a main component, the second principal face 2b of the Mo base 2 being positioned on at least a portion of a principal face 1a of the Cu base 1; and a first Sn—Cu-type alloy layer 3 covering the first principal face 2a and side faces 2c and 2d of the Mo base 2, the first Sn—Cu-type alloy layer 3 containing no less than 1 mass % and no more than 13 mass % of Sn.

Abstract: A gas inlet is disposed in a lower portion of a reaction chamber, a copper substrate is disposed in an upper portion thereof, and a tungsten catalytic body heated to 1600° C. is disposed midway between the two. Ammonia gas introduced from the gas inlet is decomposed by the tungsten catalytic body, a chemical species generated by the decomposition reacts with a surface of the copper substrate, and reduces and removes a contaminant on the copper surface, and a Cu3N thin film is formed on the copper substrate surface. This Cu3N film has the action of a film which prevents the oxidation of copper. This Cu3N film is thermally decomposed and removed when heated to temperatures of not less than 300° C., leaving a clean copper surface behind.

Abstract: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.

Abstract: Electrodes formed in a partial surface area of a semiconductor substrate and distal ends of conductive nanotubes bristled on a surface of a growth substrate, are bombarded with rare gas plasma. The distal ends of the conductive nanotubes bombarded with the rare gas plasma are brought into contact with the electrodes bombarded with the rare gas plasma to fix the conductive nanotubes to the electrodes. The growth substrate is separated from the semiconductor substrate in such a manner that the conductive nanotubes fixed to the electrodes remain on the electrodes formed on the semiconductor substrate.

Abstract: A semiconductor device includes a metal carrier and a spacer element attached to the metal carrier. The semiconductor device includes a first sintered metal layer on the spacer element and a semiconductor chip on the first sintered metal layer.

Abstract: It is an object of the invention to provide an electronic part capable of forming an accurate gap between opposing substrates while also capable of decreasing the area of the electronic part, and a method of producing the same. A second electrode portion (6), having a core pattern (7) and a bump pattern (8) covering the surface thereof, is provided on a device substrate (1), the core pattern (7) is made of a material having hardness greater than that of the bump pattern (8), a first electrode portion (5) of the same material as the bump pattern (8) is provided on a bonding substrate (2), and a functional portion of the device substrate (1) and the first electrode portion (5) are electrically connected by direct bonding of the first electrode portion (5) and the bump pattern (8).

Abstract: A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures. The patterned structures may be vias (vertical contacts) and trenches (horizontal lines) in a semiconductor substrate. These zeolite crystals can advantageously be used for dense and aligned nanocarbon growth or in other words growth of carbon nanostructures such as carbon nanotubes (CNT) within the pores of the zeolite structure. The growth of CNT is achieved within the porous structure of the zeolite crystals whereby the pores can be defined as confined spaces (channels) in nanometer dimensions acting as a micro-reactor for CNT growth.

Abstract: A method for manufacturing a semiconductor device of the present invention is provided including the steps of forming a first conductive layer over a substrate; forming a second conductive layer containing a conductive particle and resin over the first conductive layer; and increasing an area where the first conductive layer and the second conductive layer are in contact with each other by irradiating the second conductive layer with a laser beam. By including the step of laser beam irradiation, the portion where the first conductive layer and the second conductive layer are in contact with each other can be increased and defective electrical connection between the first conductive layer and the second conductive layer can be improved.

Abstract: An electronic device and/or component is manufactured using additive processing steps, including additive printing steps. A first layer is printed using additive printing techniques wherein a single first material is used to print the first layer in a single processing step. A second layer is printed in more than a single printing step where a first portion of the second layer is printed using a second material and a second portion of the second layer is printed using a third material, and the second and third materials are different from each other.

Abstract: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.

Abstract: Molecular systems are provided for electric field activated switches, such as a crossed-wire device or a pair of electrodes to which the molecular system is linked by linking moieties. The crossed-wire device comprises a pair of crossed wires that form a junction where one wire crosses another at an angle other than zero degrees and at least one connector species connecting the pair of crossed wires in the junction. The connector species comprises the molecular system, which has an electric field induced band gap change, and thus a change in its electrical conductivity, that occurs via one of the following mechanisms: (1) molecular conformation change; (2) change of extended conjugation via chemical bonding change to change the band gap; or (3) molecular folding or stretching. Nanometer-scale reversible electronic switches are thus provided that can be assembled easily to make cross-bar circuits, which provide memory, logic, and communication functions.

Abstract: An electrical device having carbonized conductors and a method and a device for the production thereof is disclosed. The electrical device has electrical components having connections. Furthermore, there are situated between the electrical components regions made of plastic with conductors having carbonized plastic and/or agglomerated nanoparticles. The conductors are connected to the connections of the components and/or to external connections of the electronic device.

Abstract: A method of filling a conductive material in a three dimensional integration feature formed on a surface of a wafer is disclosed. The feature is optionally lined with dielectric and/or adhesion/barrier layers and then filled with a liquid mixture containing conductive precursor, such as a solution with dissolved ruthenium precursor or a dispersion or suspension with conductive particles (e.g., gold, silver, copper), and the substrate is rotated while the mixture is on its surface. Then, the liquid carrier is dried from the feature, leaving a conductive layer in the feature. These two steps are optionally repeated until the feature is filled up with the conductor. Then, the conductor is annealed in the feature, thereby forming a dense conductive plug in the feature.

Abstract: A switching element includes a first electrode, a second electrode, an ionic conductive portion and a buffer portion. The first electrode is configured to be available to feed metal ions. The ionic conductive portion is configured to contact the first electrode and the second electrode, and include an ionic conductor in which the metal ions are movable. The buffer portion is configured to have a smaller hardness than the ionic conductor, and be located between the first electrode and the second electrode along the ionic conductive portion. Electrical characteristics are switched by depositing or melting metal between said first electrode and said second electrode based on a potential difference between said first electrode and said second electrode.

Abstract: A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures. The patterned structures may be vias (vertical contacts) and trenches (horizontal lines) in a semiconductor substrate. These zeolite crystals can advantageously be used for dense and aligned nanocarbon growth or in other words growth of carbon nanostructures such as carbon nanotubes (CNT) within the pores of the zeolite structure. The growth of CNT is achieved within the porous structure of the zeolite crystals whereby the pores can be defined as confined spaces (channels) in nanometer dimensions acting as a micro-reactor for CNT growth.

Abstract: It is an object of the present invention to simplify steps needed to process a wiring in forming a multilayer wiring. In addition, when a droplet discharging technique or a nanoimprint technique is used to form a wiring in a contact hole having a comparatively long diameter, the wiring in accordance with the shape of the contact hole is formed, and the wiring portion of the contact hole is likely to have a depression compared with other portions. A penetrating opening is formed by irradiating a light-transmitting insulating film with laser light having high intensity and a pulse high in repetition frequency. A plurality of openings having a minute contact area is provided instead of forming one penetrating opening having a large contact area to have an even thickness of a wiring by reducing a partial depression and also to ensure contact resistance.

Abstract: Nanotube and metal composite interconnects are generally described. In one example, an apparatus includes an interlayer dielectric (ILD) and one or more interconnect structures coupled to the ILD, the one or more interconnect structures including a composite of metal and one or more nanotubes.

Abstract: The invented ink-jet printing method for the construction of thin film transistors using all SWNTs on flexible plastic films is a new process. This method is more practical than all of exiting printing methods in the construction TFT and RFID tags because SWNTs have superior properties of both electrical and mechanical over organic conducting oligomers and polymers which often used for TFT. Furthermore, this method can be applied on thin films such as paper and plastic films while silicon based techniques can not used on such flexible films. These are superior to the traditional conducting polymers used in printable devices since they need no dopant and they are more stable. They could be used in conjunction with conducting polymers, or as stand-alone inks.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite contact into the particles such that an electrical connection is formed via the particles between the opposite contact pad and the substrate surface contact pad. The described self-assembled interconnect structure is particularly useful in display device fabrication.

Abstract: A method of filling a conductive material in a three dimensional integration structure feature formed on a surface of a wafer is disclosed. The feature is filled with a dispersion containing a plurality of conductive particles and a solvent. Then, the solvent is removed from the feature, leaving the plurality of conductive particles in the feature. These two steps are repeated until the feature is filled up with the conductive particles. Then, the conductive particles are annealed in the feature, thereby forming a dense conductive plug in the feature.

Abstract: An electronic part mounting method, a semiconductor module, and a semiconductor device, which can reduce a mounting area and a device thickness. In an electronic part mounting method for bonding an electrode formed on a substrate and an electrode formed on an electronic part to each other, the method comprises the step of bonding both the electrodes through a metal layer made up of aggregated particles of at least one kind of metal. Then, the metal particles have an average particle size of 1 to 50 nm. Preferably, the metal particles form a metal layer having a thickness of 5 to 100 ?m.

Abstract: It is an object of the present invention to alleviate unevenness due to an opening for making a contact with the lower layer even when the opening has a large diameter (1 ?m or more). Thus, it is a further object of the invention to reduce defects caused by the unevenness due to the contact hole. It is a feature of the invention to form a wiring by filling the contact hole with conductive fine particles. The conductive fine particles can be easily dispersed into a wiring material by using conductive fine particles having high wettability with the wiring material, thereby making a contact. Thus, planarization of a contact hole can be achieved without performing a reflow process. Further, more planarity can be obtained by performing a reflow process in addition, and the reliability is improved accordingly.

Abstract: A precursor composition for the deposition and formation of an electrical feature such as a conductive feature. The precursor composition advantageously has a low viscosity enabling deposition using direct-write tools. The precursor composition also has a low conversion temperature, enabling the deposition and conversion to an electrical feature on low temperature substrates. A particularly preferred precursor composition includes silver metal for the formation of highly conductive silver features.

Abstract: A method of manufacturing a semiconductor device includes: preparing a semiconductor element having a first metal layer made of first metal on a surface thereof, and a metal substrate made of second metal, the metal substrate having a fourth metal layer made of fourth metal on a surface thereof, and mounting the semiconductor element on the surface thereof; providing metal nanopaste between the first metal layer and the fourth metal layer, the metal nanopaste being formed by dispersing fine particles made of third metal with a mean diameter of 100 nm or less into an organic solvent; and heating, or heating and pressurizing the semiconductor element and the metal substrate between which the metal nanopaste is provided, thereby removing the solvent. Further, each of the first, third and fourth metals is made of any metal of gold, silver, platinum, copper, nickel, chromium, iron, lead, and cobalt, an alloy containing at least one of the metals, or a mixture of the metals or the alloys.

Abstract: Aspects of the current invention are directed to a method of mounting a flexible printed circuit and a manufacturing method of an electric optical device. Each of the methods form semiconductor elements and first terminal portions for electrically connecting the semiconductor elements and the outside of the board. These terminal portions have are completely or partially covered with an organic film 37 and are pressed into second terminal portion on the flexible printed circuit from the direction above the organic film thereby creating an electrical connection. Optionally, an anisotropic conductive paste or anisotropic conductive film may be provided between the second terminal portion and the organic film.

Abstract: An image sensor includes an inner lens to enable incident light to reach a condensing lens, so that the incident light may further reach photodiodes. Light loss can be reduced and photosensitivity can be improved. The image sensor includes at least one microlens that focuses incident light onto at least one photosensor that receives a light signal transmitted from the at least one microlens. The image sensor also includes at least one inner lens, disposed between the at least one microlens and the at least one photosensor, having an upper surface of a predetermined curvature to compensate photosensitivity of light received from the at least one microlens.

Abstract: An iPVD system is programmed to deposit uniform material, such as a metallic material, into high aspect ratio nano-sized features on semiconductor substrates using a process that enhances the feature filling compared to the field deposition, while maximizing the size of the grain features in the deposited material opening at the top of the feature during the process. Plural sequential dry filling plasma processes are used with backside gas pressure varied to control substrate temperature.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: etching an area where a plurality of modules are formed on a semiconductor substrate; forming a plurality of modules on the area; forming on insulation layer on the substrate; forming a plurality of contacts that contact a plurality of the modules by filling a selectively etched area of the isolation layer with conductive material; and forming a first conductive polymer wire for connecting contacts of the plurality of contacts.

Abstract: A plasma processing method performs a plasma processing on a substrate mounted on a mounting table installed in an airtight processing chamber, the mounting table having a smaller size than the substrate. The substrate having a surface, on which a resist mark is formed, is mounted on the mounting table and then electrostatically adsorbed on the mounting table by applying a voltage to an electrostatic chuck. The surface of the substrate is etched by using a plasma of an etching gas while the substrate is cooled through a heat transfer between the substrate and the mounting table via a thermally conductive gas supplied between a top surface of the mounting table and a bottom surface of the substrate. The supply of the thermally conductive gas is stopped, and the resist mask on the substrate is ashed by using a plasma of an ashing gas containing O2.

Abstract: Disclosed are methods for making microwave circuits using thickfilm components. In an embodiment, the method includes depositing a dielectric over a ground plane, and then forming a conductor on the dielectric. The conductor is formed by depositing a conductive thickfilm on the dielectric and then “subsintering” the conductive thickfilm. In one embodiment, before the subsintering, the conductive thickfilm is patterned to define at least one conductor. In another embodiment, after the subsintering, the conductive thickfilm is patterned to define at least one conductor. After subsintering, the conductive thickfilm is etched to expose the conductor(s), and the conductor(s) are then fired at a full sintering temperature.

Abstract: Methods for forming conductive layers. A layer of metal composite is applied on a substrate, comprising a plurality of metal flakes, a plurality of nanometer metal spheres, and a plurality of mixed metal precursors. The plurality of mixed metal precursors comprises a mixture of inorganic salts and organic acidic salts. The layer of metal composite is cured to induce an exothermic reaction, thereby forming a conductive layer on the substrate at a relatively low temperature (<200° C.

Abstract: A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions.

Abstract: The present invention relates to a method for fabricating a semiconductor device with a fine pattern. The method includes the steps of: (a) forming a semiconductor substrate structure including a substrate, a nitride layer for forming a hard mask, a plurality of conductive patterns, an etch stop layer, an inter-layer insulation layer, an anti-reflective coating (ARC) layer and a photoresist pattern; (b) selectively etching the ARC layer and the nitride layer with use of the photoresist pattern as an etch mask to form a hard mask; (c) removing the photoresist pattern and the ARC layer; (d) etching the inter-layer insulation layer disposed between the conductive patterns by using the hard mask as an etch mask to form a contact hole exposing the etch stop layer; (e) removing the etch stop layer formed at a bottom area of the contact hole to expose the substrate; and (f) forming a plug electrically contacted to the exposed substrate, wherein the steps (b) and (d) to (e) proceeds in an in situ condition.

Abstract: There is provided a method of producing an organic semiconductor device by which an organic semiconductor device having an optional configuration can easily be produced. A method of producing an organic semiconductor device comprising a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and an organic semiconductor layer is provided which comprises the steps of: 1) forming a monomer layer of a conductive polymer precursor; 2) maintaining the monomer layer at a given temperature; and 3) applying an oxidizing agent solution to a desired location of the monomer layer to obtain a polymer layer of a desired conductivity.

Abstract: A method and resultant device, in which metal nanoparticles are self-assembled into two-dimensional lattices. A periodic hole pattern (wells) is fabricated on a photoresist substrate, the wells having an aspect ratio of less than 0.37. The nanoparticles are synthesized within inverse micelles of a polymer, preferably a block copolymer, and are self-assembled onto the photoresist nanopatterns. The nanoparticles are selectively positioned in the holes due to the capillary forces related to the pattern geometry, with a controllable number of particles per lattice point.

Abstract: Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting assemblies. A semiconductor component substrate, such as a semiconductor die or other substrate, has dielectric material disposed on a surface thereof, surrounding but not covering interconnect elements, such as bond pads, on that surface. A second semiconductor component substrate, such as a carrier substrate with interconnect elements such as terminal pads, is adhered to the first semiconductor component substrate, forming a semiconductor package assembly having interconnect voids between the corresponding interconnect elements. A flowable conductive material is then injected into each interconnect void using an injection needle that passes through one of the substrates into the interconnect void, forming a conductive interconnect between the bond pads and terminal pads of the substrates.

Abstract: A composition including an amount of at least one vinyl terminated polymer; an amount of at least one cross-linker comprising a terminal Si—H unit; an amount of at least one thermally conductive first filler, and at least one thermally conductive second filler, wherein a melting point of the first filler is greater than the melting point of the second filler. An apparatus including a package configured to mate with a printed circuit board; a semiconductor device coupled to the package; a thermal element; and a curable thermal material disposed between the thermal element and the semiconductor device.

Abstract: The present invention relates to a method of and an apparatus for forming a thin metal film of copper, silver, or the like on a surface of a semiconductor or another substrate. A method of forming a thin metal film, comprises preparing a dispersed liquid having a metal-containing organic compound dispersed in a predetermined solvent, coating the dispersed liquid on a surface of a substrate and evaporating the solvent to form a coating layer, and applying an energy beam to the coating layer to decompose away an organic substance contained in the coating layer in an area irradiated with the energy beam and bond metal contained in the coating layer.According to the present invention, it is possible to form a thin metal film of good quality efficiently and stably. The thin metal film used as metal interconnects in highly integrated semiconductor circuits contributes to the progress of a process of fabricating semiconductor devices.