Forming Solder Contact Or Bonding Pad Patents (Class 438/612)
  • Patent number: 11049798
    Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
  • Patent number: 11026332
    Abstract: A reel-to-reel machine to fabricate a printed flexible circuit on the fly, the machine has a plurality of reels, a laser scanner to ablate a metal foil, a source of UV light or heat to curing an adhesive in a coverlay, another source of UV light or heat to debond a sacrificial liner on the fly. There is a depositor to deposit a sintering paste on the fly onto a predetermined spot for a pad on the metal foil. Removal of slugs are also possible on the fly.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: June 1, 2021
    Assignee: Manaflex, LLC
    Inventor: Robert Clinton Lane
  • Patent number: 11018124
    Abstract: A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventor: Andrew Collins
  • Patent number: 11004783
    Abstract: An integrated circuit (IC) chip design for symmetric power delivery includes an integrated circuit (IC) chip package with I/O connections exposed on a first surface and power connections exposed on a second opposite surface. At least one voltage regulation module (VRM) is positioned on the second opposite surface and electrically coupled to the power connections on the second opposite surface.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 11, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Vlad Radu Calugaru
  • Patent number: 10943841
    Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Patent number: 10930573
    Abstract: A circuit module includes a flat substrate, a frame substrate, a first electronic component, and a first sealing member. First connection electrodes are disposed at a peripheral portion of one main surface of the flat substrate. Second connection electrodes are disposed on one main surface of the frame substrate at locations corresponding to the first connection electrodes. Each of the first connection electrodes and a corresponding one of the second connection electrodes are connected to each other via a first connection member. The first electronic component is sealed by the first sealing member. The first electronic component and the first sealing member are disposed in a cavity defined by the one main surface of the flat substrate and an inner surface of the frame substrate. The first sealing member is separated from the inner surface of the frame substrate.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: February 23, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shingo Funakawa, Nobumitsu Amachi
  • Patent number: 10910337
    Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: February 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Noriko Okunishi, Toshinori Kiyohara
  • Patent number: 10886594
    Abstract: The present disclosure provides a packaging structure and a packaging method for an antenna. The packaging structure comprises a redistribution layer, having a first surface and an opposite second surface; a first metal joint pin, formed on the second surface of the redistribution layer; a first packaging layer, disposed on the redistribution layer covering the first metal joint pin; a first antenna metal layer, patterned on the first packaging layer, and a portion of the first antenna metal layer electrically connects with the first metal joint pin; a second metal joint pin, formed on the first antenna metal layer; a second packaging layer, disposed on the first antenna metal layer covering the second metal joint pin; a second antenna metal layer, formed on the second packaging layer; and a metal bump and an antenna circuit chip, bonded to the first surface of the redistribution layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 5, 2021
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin
  • Patent number: 10867893
    Abstract: A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: December 15, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Sergey Ananiev, Robert Bauer, Heinrich Koerner, Yik Yee Tan, Juergen Walter
  • Patent number: 10854570
    Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Jyun-Siang Peng
  • Patent number: 10790249
    Abstract: The invention concerns a discrete electronic component including: a semiconductor chip including a transistor, the chip including a first metallization of connection to a first conduction region of the transistor; and a printed circuit board including first and second separate connection pads, wherein: the chip is assembled on the printed circuit board so that the first metallization of the chip is in contact with the first and second connection pads of the printed circuit board; and the assembly including the semiconductor chip and the printed circuit board is encapsulated in a package made of an insulating material leaving access to first and second connection terminals of the component connected, inside of the package, respectively to the first and second connection pads of the printed circuit board.
    Type: Grant
    Filed: June 23, 2019
    Date of Patent: September 29, 2020
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sébastien Carcouet, Xavier Maynard
  • Patent number: 10777876
    Abstract: The present disclosure provides an antenna package structure and packaging method. The package structure includes: a metal joint pin fabricated by using a wire bonding process; and a packaging layer, covering the metal joint pin. An antenna circuit chip and an antenna metal layer are electrically connected to two ends of the antenna feeder package structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: September 15, 2020
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Jangshen Lin, Yenheng Chen, Chengchung Lin, Chengtar Wu
  • Patent number: 10714457
    Abstract: In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Hang Tung, Kuo-Chung Yee
  • Patent number: 10696919
    Abstract: The present subject matter describes a method for preparation of a lubricant dispersed with carbon nanotubes (CNTs) and a lubricant dispersed with the CNTs prepared thereof. The method comprises ball milling the CNTs and purifying the ball milled CNTs to remove impurities in the CNTs. The method also comprises oxidizing surfaces of the purified CNTs by adding the purified CNTs to a solution comprising at least one oxidizing acid and then refluxing the solution. The oxidized surfaces of the CNTs are modified by adding the CNTs to a solution comprising at least one fatty acid to obtain surface modified CNTs. The method also comprises dispersing the surface modified CNTs in a lubricant to obtain the lubricant dispersed with CNTs.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 30, 2020
    Assignee: Hindustan Petroleum Corporation Limited
    Inventors: Annaji Rajiv Kumar Tompala, Srinivas Vadapalli, Amitabh Kumar Jain, Venkata Chalapathi Rao Peddy, Venkateswarlu Choudary Nettem, Sri Ganesh Gandham
  • Patent number: 10679968
    Abstract: A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Hao Tsai, Chuei-Tang Wang
  • Patent number: 10622298
    Abstract: A wiring substrate includes a wiring, a solder resist layer formed on the wiring and having an opening from which a part of the wiring is exposed, a copper seed layer formed in the opening, a copper layer formed on the seed layer and filling the opening up to a certain depth thereof, and a metal post erected on the copper layer, having an upper surface located at a position higher than an upper surface of the solder resist layer and including any one of nickel, silver and tin.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 14, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yoshihisa Kanbe
  • Patent number: 10615130
    Abstract: A packaged semiconductor device includes a substrate having a ground plane, a first communication port on the substrate, a second communication port on the substrate adjacent the first communication port, and grounding structures on the substrate. Each of the grounding structures is in contact with two different locations on the ground plane and is adjacent to one of the first and second communication ports. An electrically insulating material completely covers a top side of each of the grounding structures.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 7, 2020
    Assignee: NXP USA, Inc.
    Inventor: Walter Parmon
  • Patent number: 10573614
    Abstract: A process for fabricating a circuit substrate is provided. A dielectric layer is formed to cover a surface of a circuit stack and a patterned conductive layer, and has bonding openings exposing bonding segments of traces of the patterned conductive layer, and has plating openings exposing plating segments of the traces. A plating seed layer is formed to cover the surface of the circuit stack, the bonding segments, the plating segments, and the dielectric layer. A mask is formed to cover the plating layer and has mask openings exposing portions of the plating seed layer on the bonding segments. Portions of the plating seed layer on the bonding segments are removed with use of the mask as an etching mask. A thickening conductive layer is plated on each of the bonding segments with use of the mask as a plating mask. The mask and the plating seed layer are removed.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: February 25, 2020
    Assignee: VIA Technologies, Inc.
    Inventor: Chen-Yueh Kung
  • Patent number: 10541213
    Abstract: An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding compound, the passivation layer including a passivation layer recess vertically aligned with the metal via, and a redistribution layer bond pad capping the metal via, a portion of the redistribution layer bond pad within the passivation layer recess projecting above a top surface of the molding compound.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 10482910
    Abstract: According to one embodiment, a flexible printed wiring board includes a base insulation layer, first wirings W1 on the base insulation layer, an intermediate insulation layer overlapped with the first wirings, connection pads on the intermediate insulation layer, a cover insulation layer overlapped with the connection pads and the intermediate insulation layer and including openings through which the connection pads are exposed to the cover layer, and conductive vias MT electrically connecting the first wirings to at least a part of the connection pads respectively. The conductive vias are overlapped with the connection pads in a thickness direction of the flexible printed wiring board.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: November 19, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporatoin
    Inventors: Norio Yoshikawa, Yoshihiro Amemiya
  • Patent number: 10453815
    Abstract: Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hao-Yi Tsai, Chien-Hsiun Lee, Chung-Shi Liu, Hsien-Wei Chen
  • Patent number: 10448517
    Abstract: A method and apparatus for multiple flexible circuit cable attachment is described herein. Gold bumps are bonded on interconnection pads of a substrate to create a columnar structure and solder or conductive epoxy is dispensed on the flexible cable circuit. The substrate and flexible cable circuit are aligned and pressed together using force or placement of a weight on either the substrate or flexible cable circuit. Appropriate heat is applied to reflow the solder or cure the epoxy. The solder wets to the substrate pads, assisted by the gold bumps, and have reduced bridging risk due to the columnar structure. A nonconductive underfill epoxy is applied to increase mechanical strength.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: October 15, 2019
    Assignee: Jabil Inc.
    Inventors: Wenlu Wang, Mark A. Tudman, Michael Piring Santos, Ross Kristensen Benz, Hien Ly, Gary Fang
  • Patent number: 10399186
    Abstract: A lead-free solder alloy contains zinc (Zn) as the main component and aluminum (Al) as an alloying metal. The solder alloy is a eutectic having a single melting point in the range of 320 to 390° C. (measured by DSC at a heating rate of 5° C. min-1).
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: September 3, 2019
    Assignee: Heraeus Materials Singapore Pte., Ltd.
    Inventors: Wei Chih Pan, Joseph Aaron Mesa Baquiran, Inciong Reynoso
  • Patent number: 10381279
    Abstract: To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akira Yajima
  • Patent number: 10332752
    Abstract: A substrate includes a support layer, a column-shaped first bump, and a second bump. The support layer has a main surface. The first bump is filled with a first conductive metal and also has a first upper surface and a side surface. The second bump includes a plurality of fine particles formed of a second conductive metal and also has a third portion configured to cover the first upper surface and a fourth portion configured to cover a part of the side surface. The first bump is disposed on the main surface, or the first bump is connected to an electrode disposed on the main surface. The second bump has a convex second upper surface. A height of the fourth portion in a direction perpendicular to the first upper surface is smaller than that of the first bump.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 25, 2019
    Assignee: OLYMPUS CORPORATION
    Inventor: Yoshiaki Takemoto
  • Patent number: 10211052
    Abstract: Systems and methods for fabrication of a redistribution layer are described. There is no deposition of a seed layer, made from copper, on top of a substrate. The lack of the seed layer avoids a need for etching the seed layer. When the seed layer is not etched, the redistribution layer, also made from copper, is not etched.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 19, 2019
    Assignee: Lam Research Corporation
    Inventors: Bryan L. Buckalew, Stephen J. Banik, II, Joseph Richardson, Thomas A. Ponnuswamy
  • Patent number: 10163797
    Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Teng, Jung-Hsun Tsai, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10153193
    Abstract: An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jeong Do Yang, Byoung Yong Kim, Seung-Soo Ryu, Sang Hyeon Song, Jung Yun Jo, Seung-Hwa Ha, Jeong Ho Hwang
  • Patent number: 10141271
    Abstract: A method of reducing electromagnetic interference in a semiconductor device includes: forming at least one functional circuit in a substrate of the semiconductor device; forming an integrated micro-shielding structure in the semiconductor device, the micro-shielding structure extending vertically through the substrate between a front surface and a back surface of the substrate and surrounding the functional circuit, the micro-shielding structure being configured to reduce radio frequency (RF) emissions in the semiconductor device and/or RF coupling between different functional parts of the functional circuit.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 27, 2018
    Assignee: COOLSTAR TECHNOLOGY, INC.
    Inventors: Shuming Xu, Yi Zheng
  • Patent number: 10128176
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a signal redistribution structure that comprises an anti-oxidation layer.
    Type: Grant
    Filed: May 8, 2016
    Date of Patent: November 13, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Jong Sik Paek, William Huang, Raymond Tsao, Mike Liang
  • Patent number: 10128206
    Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate having an opening over the contact pad; and a conductive pillar over the opening of the passivation layer, wherein the conductive pillar comprises an upper portion substantially perpendicular to a surface of the substrate and a lower portion having tapered sidewalls.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Wen-Hsiung Lu, Meng-Wei Chou, Hung-Jui Kuo, Chung-Shi Liu
  • Patent number: 10090270
    Abstract: A metal pillar with cushioned tip is disclosed. The cushioned tip offsets height difference among metal pillars. So that the height difference among metal pillars gives no significant effect to electrical coupling. The cushioned tip is a metal sponge. Additional one embodiment shows a second metal is plated on a tip of the metal sponge. A hardness of the second metal is greater than a hardness of a metal of the metal sponge, so that the second metal can stab into a corresponding metal sponge for electrical coupling.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 2, 2018
    Inventor: Dyi-Chung Hu
  • Patent number: 10026332
    Abstract: Educational information is provided to a user associated with a trigger object, and an education-related user attribute. Contemplated trigger objects include wearables, and especially pieces of jewelry. Contemplated education-related user attributes include current age, gender, subject being studied, current grade level, hobby, ethnicity, profession, vocation, location of interest, topic of interest, time period of interest, event of interest, favorite sport, favorite team, current school, color preference, resource preference, brand affinity, and expertise level. The educational information can be rendered directly on the trigger object, or on any other electronic rendering device.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 17, 2018
    Inventor: Jasmine Gupta
  • Patent number: 10020288
    Abstract: A semiconductor chip is provided including an integrated circuit on a substrate; pads electrically connected to the integrated circuit; a lower insulating structure defining contact holes exposing the pads, respectively; and first, second and third conductive patterns electrically connected to the pads. The second conductive pattern is between the first conductive pattern and the third conductive pattern when viewed from a plan view. Each of the first to third conductive patterns includes a contact portion filling the contact hole, a first conductive line portion extending in one direction on the lower insulating structure, and a bonding pad portion. Ends of the bonding pad portions of the first and third conductive patterns protrude in the one direction as compared with an end of the bonding pad portion of the second conductive pattern when viewed from a plan view.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Sik Park, Jung-Hoon Han
  • Patent number: 9966341
    Abstract: Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 8, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette
  • Patent number: 9966347
    Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: May 8, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Jaspreet S. Gandhi, Christopher J. Gambee, Satish Yeldandi
  • Patent number: 9928334
    Abstract: A method for redistribution layer routing is proposed. The method at least comprises inputting information regarding a redistribution layer layout, at least one netlist, and a constraint file. Next, it is creating a concentric-circle model based on the information, the netlist and the constraint file. Subsequently, it is assigning at least one pre-assignment net to at least one redistribution layer according to the concentric-circle model. Finally, the redistribution layer routing is performed.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: March 27, 2018
    Inventors: Bo-Qiao Lin, Ting-Chou Lin, Chun-Yi Yang, Yao-Wen Chang
  • Patent number: 9908773
    Abstract: A method for packaging a microelectronic device in an hermetically sealed cavity and managing an atmosphere of the cavity with a dedicated hole, including making said cavity between a support and a cap layer such that a sacrificial material and the device are arranged in the cavity; removing the sacrificial material through at least one release hole, and hermetically sealing the release hole; making a portion of wettable material on the cap layer, around a blind hole or a part of said outside surface corresponding to a location of said dedicated hole; making a portion of fuse material on the portion of wettable material; making the dedicated hole by etching the cap layer; and reflowing the portion of fuse material with a controlled atmosphere, forming a bump of fuse material which hermetically plugs said dedicated hole.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: March 6, 2018
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, EPCOS AG
    Inventors: Damien Saint-Patrice, Arnoldus Den Dekker, Marcel Giesen, Florent Greco, Gudrun Henn, Jean-Louis Pornin, Bruno Reig
  • Patent number: 9899342
    Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Hui Lee, Hung-Jui Kuo, Ming-Che Ho, Tzu-Yun Huang
  • Patent number: 9865516
    Abstract: A wafer and a forming method thereof are provided. The wafer has a die region and a scribe-line region adjacent to the die region, and includes a conductive bonding pad in the die region of the wafer and a wafer acceptance test (WAT) pad in the scribe-line region of the wafer. A top surface of the WAT pad is lower than a top surface of the conductive bonding pad.
    Type: Grant
    Filed: January 10, 2016
    Date of Patent: January 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Tzung-Han Lee, Chun-Yi Wu, Sheng-Yu Yan, Yi-Ting Cheng
  • Patent number: 9837326
    Abstract: To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: December 5, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akira Yajima
  • Patent number: 9812429
    Abstract: A multi-layer semiconductor device includes a first semiconductor structure having first and second opposing surfaces, the second surface of the first semiconductor structure having at least a first semiconductor package pitch. The multi-layer semiconductor device also includes a second semiconductor structure having first and second opposing surfaces, the first surface of the second semiconductor structure having a second semiconductor package pitch. The multi-layer semiconductor device additionally includes a third semiconductor structure having first and second opposing surfaces, the first surface of the third semiconductor structure having a third semiconductor package pitch which is different from at least the second semiconductor package pitch. The second and third semiconductor structures are provided on a same package level of the multi-layer semiconductor device. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: November 7, 2017
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Rabindra N. Das, Mark A. Gouker, Pascale Gouker, Leonard M. Johnson, Ryan C. Johnson
  • Patent number: 9798201
    Abstract: Provided are liquid crystal display and the method for manufacturing the same. According to an aspect of the present disclosure, there is provided a liquid crystal display device, including: a first substrate; a gate electrode disposed on the first substrate; a semiconductor pattern layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the semiconductor pattern layer and facing each other, wherein the gate electrode includes a reference plane and a protrusion protruding from the reference plane in a horizontal direction, and the protrusion overlaps the source electrode and the drain electrode.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 24, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hyung Gi Jung
  • Patent number: 9773831
    Abstract: An image sensor having a lower device, an upper devise, and a TSV structure is provides. The lower device may include a lower substrate, a lower TSV pad, and a lower interlayer insulating layer. The lower TSV pad may be formed over the lower substrate. The lower interlayer insulating layer may cover the lower TSV pad. The upper device may include an upper substrate, an upper TSV pad, and an upper interlayer insulating layer. The upper TSV pad may be formed over the upper substrate. The upper interlayer insulating layer may cover the upper TSV pad. The TSV structure may vertically pass through the upper device and electrically connect the upper TSV pad to the lower TSV pad. The upper TSV pad may include an upper opening. The lower TSV pad may include a unit pad and a lower opening. The unit pad may be exposed through the upper opening and contacts the TSV structure in a top view.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 26, 2017
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hui Yang, Young-Hun Choi
  • Patent number: 9773732
    Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Chia-Wei Tu
  • Patent number: 9728563
    Abstract: A method of combinatorial masking employs a combinatorial etch mask that includes a top layer of a stack of material layers and a secondary mask on the top layer to etch other material layers of the stack. The method includes patterning a first layer at a top of the stack of material layers, and providing the secondary mask on top of the patterned first layer. The method further includes etching other material layers of the stack including a second layer below the first layer with the combinatorial mask and then etching the first layer along with the other material layers of the stack excluding the second layer using the secondary mask as an etch mask.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: August 8, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Carl P. Taussig, Han-Jun Kim, Ohseung Kwon
  • Patent number: 9722106
    Abstract: The invention relates to the manufacturing process of a solar cell (1) with back contact and passivated emitter, comprising a dielectric stack (10) of at least two layers consisting of at least a first dielectric layer (11) made of AlOx in contact with a p-type silicon layer (3), and a second dielectric layer (13) deposited on the first dielectric layer (11). Besides, the method of manufacturing comprising a formation step of at least one partial opening (15) preferably by laser ablation into the dielectric stack (10), sparing at least partially the aforementioned first dielectric layer.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: August 1, 2017
    Assignees: IMEC, Total Marketing Services
    Inventors: Perine Jaffrennou, Johan Das, Angel Uruena De Castro
  • Patent number: 9692208
    Abstract: A method of manufacturing a semiconductor device includes: forming a ridge on a semiconductor layer stacked on a substrate by removing a part of the semiconductor layer; forming an electrode on the ridge so as to have a flat portion having a flat surface substantially parallel to the upper surface of the ridge and sloped portions on both sides of the flat portion with each of the sloped portions having a sloped surface that is sloped with respect to the upper surface of the ridge; forming a protective film disposed on each side of the ridge to cover a region from the side surface of the ridge to the sloped surface of the sloped portion of the electrode; and forming a pad electrode at least on an upper surface of the electrode and the protective film.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: June 27, 2017
    Assignee: NICHIA CORPORATION
    Inventors: Atsuo Michiue, Yasuhiro Kawata
  • Patent number: RE46784
    Abstract: The invention is to provide a structure of IC pad and its forming method. The structure is arranged in an insulation layer and is comprised of a lower electric-conduction layer, a compound layer structure and a pad layer. The lower electric-conduction layer is arranged at an appropriate position in the insulation layer and is connected to an electric potential. The compound layer structure is arranged on the insulation layer and is composed of at least one electric-conduction layer and at least one electric-conduction connecting layer, both are inter-overlapped to each other. The pad layer is arranged on the compound layer structure.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 10, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Ying-Hsi Lin
  • Patent number: RE47171
    Abstract: The invention is to provide a structure of IC pad and its forming method. The structure is arranged in an insulation layer and is comprised of a lower electric-conduction layer, a compound layer structure and a pad layer. The lower electric-conduction layer is arranged at an appropriate position in the insulation layer and is connected to an electric potential. The compound layer structure is arranged on the insulation layer and is composed of at least one electric-conduction layer and at least one electric-conduction connecting layer, both are inter-overlapped to each other. The pad layer is arranged on the compound layer structure.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: December 18, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Ying-Hsi Lin