Abstract: A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating encapsulation. The conductive structures are located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures is electrically connected to the at least one die. Each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof, and wherein each of the conductive structures has a plurality of pores distributed therein.

Abstract: A high-frequency transmission line includes a multi-layer substrate, a plurality of line portions, a plurality of signal vias, a ground plane, and a plurality of metal portions. When a high-frequency signal that is transmitted through each of the plurality of line portions is transmitted through the transmission area corresponding to each of the plurality of line portions, the plurality of metal portions confine the high-frequency signal in the transmission area. The plurality of metal portions pass through at least a single dielectric layer, are electrically continuous with the ground plane. The plurality of metal portions are formed along the transmission direction and are arranged in an alternating manner with each of the plurality of signal vias so as to sandwich each of the plurality of signal vias in a direction differing from the transmission direction.

Abstract: The present application provides a method for manufacturing a semiconductor package with air gaps for reducing capacitive coupling between conductive features. The method comprises: providing a first substrate with an integrated circuit; forming a first stack of insulating layers with first protruding portions on the integrated circuit; removing a topmost insulating layer in the first stack of insulating layers; forming through holes in the first stack to form a first semiconductor structure; providing a second substrate with an integrated circuit; forming a second stack of insulating layers with second protruding portions on the integrated circuit; forming a recess portion in the first stack to form a second semiconductor structure; and bonding the first semiconductor structure with the second semiconductor structure, with an air gap formed from the recess portion.

Abstract: A system and method for laser assisted bonding of semiconductor die. As non-limiting examples, various aspects of this disclosure provide systems and methods that enhance or control laser irradiation of a semiconductor die, for example spatially and/or temporally, to improve bonding of the semiconductor die to a substrate.

Abstract: An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.

Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.

Abstract: A semiconductor structure includes a semiconductor substrate, a via, a first dielectric layer, a first graphene layer, a metal line, and a second graphene layer. The via is over the semiconductor substrate. The first dielectric layer laterally surrounds the via. The first graphene layer extends along a top surface of the via. The metal line is over the via and is in contact with the first graphene layer. The second graphene layer peripherally encloses the metal line and the first graphene layer.

Abstract: The present application provides a method for preparing a semiconductor device, include the following steps: forming a source/drain (S/D) region in a semiconductor substrate; forming a bonding pad over the semiconductor substrate; forming a first spacer over a sidewall of the bonding pad; forming a first passivation layer covering the bonding pad and the first spacer; and forming a conductive bump over the first passivation layer, wherein the conductive bump penetrates through the first passivation layer to electrically connect to the bonding pad and the S/D region.

Abstract: Provided is a protective material ring in which a plurality of silicon members are joined. A protective material ring is to be installed in a treatment chamber of a substrate treatment apparatus performing plasma treatment on a substrate, and the substrate is accommodated in the treatment chamber. The protective material ring includes: three or more silicon members; and a joining part joining the silicon members. The joining part contains boron oxide.

Abstract: A method of producing a layer stack includes a) forming a first layer having a first material composition on a substrate, b) performing intermediate processing of the substrate with the first layer, c) forming an additional layer having a second material composition, the first material composition and the second material composition differing from each other by at most 10% by weight, at least locally directly on the first layer and d) applying a second layer at least in places directly onto the additional layer.

Abstract: The present disclosure provides a packaging structure and a packaging method for an antenna. The packaging structure comprises a redistribution layer, having a first surface and an opposite second surface; a first metal joint pin, formed on the second surface of the redistribution layer; a first packaging layer, disposed on the redistribution layer covering the first metal joint pin; a first antenna metal layer, patterned on the first packaging layer, and a portion of the first antenna metal layer electrically connects with the first metal joint pin; a second metal joint pin, formed on the first antenna metal layer; a second packaging layer, disposed on the first antenna metal layer covering the second metal joint pin; a second antenna metal layer, formed on the second packaging layer; and a metal bump and an antenna circuit chip, bonded to the first surface of the redistribution layer.

Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate. The method includes depositing a first-side UBM layer on a first surface of the semiconductor substrate. The method includes forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the semiconductor substrate. The method includes forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.

Abstract: The present disclosure provides an antenna package structure and packaging method. The package structure includes: a metal joint pin fabricated by using a wire bonding process; and a packaging layer, covering the metal joint pin. An antenna circuit chip and an antenna metal layer are electrically connected to two ends of the antenna feeder package structure.

Abstract: A wafer processing method is disclosed to divide a wafer of glass substrate into individual chips along division lines. In the shield tunnel forming step, a pulsed laser beam of a wavelength, which transmits through the wafer, is irradiated with its focal point positioned at a region corresponding to each division line so that a plurality of shield tunnels which are each formed of perforations and affected regions surrounding the perforations are formed along the division lines, respectively. In the modified layer forming step, another pulsed laser beam of a wavelength, which transmits through the wafer, is irradiated with its focal point positioned at the region corresponding to each division line so that modified layers are formed in addition to the shield tunnels along the division lines, respectively. In the dividing step, an external force is applied to the wafer to divide the wafer into individual chips.

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of providing a semiconductor body, forming a trench in the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body, and coating inner walls of the trench with an isolation layer. The method further comprises the steps of coating the isolation layer at the inner walls with a metallization layer, coating a top side of the semiconductor body, at which the trench is formed, at least partially with an electrically conductive contact layer, where the contact layer is electrically connected with the metallization layer, coating the top side of the semiconductor body at least partially and the trench with a capping layer, and forming a contact pad at the top side of the semiconductor body by removing the contact layer and the capping layer at least partially. Furthermore, a semiconductor device is provided.

Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

Abstract: Provided is a ring for an electrode in which a plurality of silicon members is joined. The ring for the electrode includes a plurality of first silicon members abutted in one direction, an embedded silicon member that is embedded at a position across the plurality of first silicon members abutted, and a joining part joining the plurality of first silicon members and the embedded silicon member, the joining part provided between the plurality of first silicon members and the embedded silicon member.

Abstract: An imaging module of the invention includes: an imaging element; and a substrate positioned on a rear surface opposite to an imaging surface of the imaging element and provided to extend from the rear surface to a side opposite to the imaging surface. An electrode pad provided on the rear surface of the imaging element and a front end portion of an electrode pad provided on a main surface of the substrate at a position close to the imaging element are electrically connected via a conductive connecting material portion. A notch portion recessed from a distal end of the front end portion is formed at the front end portion of the electrode pad of the substrate.

Abstract: A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material.

Abstract: A method for interconnecting a first conductor and a second conductor includes forming a layer of substantially pure copper on the first conductor, applying a copper sintering material to the first conductor, the second conductor, or both, and interconnecting the first conductor and the second conductor by sintering the copper sintering material so as to form a copper-copper interface that includes the layer of substantially pure copper, the second conductor, and the copper sintering material.

Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

Abstract: An apparatus comprises a circuit board having a first conductive pad on a circuit board surface and a conductive overlay, which has a first surface and a second surface opposite the first surface and is configured to deflect in response to a touch on the first surface. A protrusion protrudes from the second surface and is configured to be a second conductive pad. The circuit board, the conductive overlay, and the protrusion are arranged such that the second surface faces the circuit board surface and is separated from the first conductive pad by a first distance. The protrusion and the first conductive pad are separated by a second distance and have an overlapping area. The apparatus may also comprise a spacer configured to separate the first conductive pad from the second surface by the first distance and from the protrusion by the second distance.

Abstract: A method for manufacturing a backside metalized compound semiconductor wafer includes the steps of: providing a compound semiconductor wafer; attaching the compound semiconductor wafer to a supporting structure; forming an adhesion layer including nickel and vanadium on a back surface of the compound semiconductor wafer; forming an alloy layer including titanium and tungsten on the adhesion layer; forming a metallization layer including gold on the alloy layer; and removing the supporting structure from the compound semiconductor wafer to obtain the backside metalized compound semiconductor wafer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a bond pad layer onto a dielectric structure formed over a substrate. The dielectric structure surrounds a plurality of interconnect layers. A protective layer is formed onto the bond pad layer, and the bond pad layer and the protective layer are patterned to define a bond pad covered by the protective layer. One or more upper passivation layers are formed over the protective layer. A dry etching process is performed to form an opening extending through the one or more upper passivation layers to the protective layer. A wet etching process is performed to remove a part of the protective layer and expose an upper surface of the bond pad.

Abstract: An electronic device includes a first component carrier with a stack of at least one first electrically conductive layer structure and at least one first electrically insulating layer structure, and a second component carrier with a respective stack of at least one second electrically conductive layer structure and at least one second electrically insulating layer structure. The second component carrier is connected with the first component carrier so that a stacking direction of the first component carrier is angled with regard to a stacking direction of the second component carrier.

Abstract: The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic apparatus, in which irregular reflection of light inside a solid-state imaging element package can be suppressed. In the solid-state imaging element, a plurality of pixels is planarly arranged, a connection portion utilized for connection to the outside is provided on a more outer side than an imaging region, and an open portion that is opened up to the connection portion from a light incident surface side of the imaging region where light is incident is formed. Additionally, a plurality of protruding portions periodically arranged is formed on a counterbore surface that is a surface inside the open portion excluding the connection portion. The present technology can be applied to, for example, a back-illuminated type or layered CMOS image sensor.

Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

Abstract: A semiconductor device package includes a first semiconductor device, a first redistribution layer (RDL) structure and a second RDL structure. The first semiconductor device has a first conductive terminal and a second conductive terminal. The first RDL structure covers the first conductive terminal. The second RDL structure covers the second conductive terminal and being separated from the first RDL structure.

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Abstract: A reel-to-reel machine to fabricate a printed flexible circuit on the fly, the machine has a plurality of reels, a laser scanner to ablate a metal foil, a source of UV light or heat to curing an adhesive in a coverlay, another source of UV light or heat to debond a sacrificial liner on the fly. There is a depositor to deposit a sintering paste on the fly onto a predetermined spot for a pad on the metal foil. Removal of slugs are also possible on the fly.

Abstract: A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

Abstract: An integrated circuit (IC) chip design for symmetric power delivery includes an integrated circuit (IC) chip package with I/O connections exposed on a first surface and power connections exposed on a second opposite surface. At least one voltage regulation module (VRM) is positioned on the second opposite surface and electrically coupled to the power connections on the second opposite surface.

Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad.

Abstract: A circuit module includes a flat substrate, a frame substrate, a first electronic component, and a first sealing member. First connection electrodes are disposed at a peripheral portion of one main surface of the flat substrate. Second connection electrodes are disposed on one main surface of the frame substrate at locations corresponding to the first connection electrodes. Each of the first connection electrodes and a corresponding one of the second connection electrodes are connected to each other via a first connection member. The first electronic component is sealed by the first sealing member. The first electronic component and the first sealing member are disposed in a cavity defined by the one main surface of the flat substrate and an inner surface of the frame substrate. The first sealing member is separated from the inner surface of the frame substrate.

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.

Abstract: The present disclosure provides a packaging structure and a packaging method for an antenna. The packaging structure comprises a redistribution layer, having a first surface and an opposite second surface; a first metal joint pin, formed on the second surface of the redistribution layer; a first packaging layer, disposed on the redistribution layer covering the first metal joint pin; a first antenna metal layer, patterned on the first packaging layer, and a portion of the first antenna metal layer electrically connects with the first metal joint pin; a second metal joint pin, formed on the first antenna metal layer; a second packaging layer, disposed on the first antenna metal layer covering the second metal joint pin; a second antenna metal layer, formed on the second packaging layer; and a metal bump and an antenna circuit chip, bonded to the first surface of the redistribution layer.

Abstract: A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.

Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.

Abstract: The invention concerns a discrete electronic component including: a semiconductor chip including a transistor, the chip including a first metallization of connection to a first conduction region of the transistor; and a printed circuit board including first and second separate connection pads, wherein: the chip is assembled on the printed circuit board so that the first metallization of the chip is in contact with the first and second connection pads of the printed circuit board; and the assembly including the semiconductor chip and the printed circuit board is encapsulated in a package made of an insulating material leaving access to first and second connection terminals of the component connected, inside of the package, respectively to the first and second connection pads of the printed circuit board.

Abstract: The present disclosure provides an antenna package structure and packaging method. The package structure includes: a metal joint pin fabricated by using a wire bonding process; and a packaging layer, covering the metal joint pin. An antenna circuit chip and an antenna metal layer are electrically connected to two ends of the antenna feeder package structure.

Abstract: In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.

Abstract: The present subject matter describes a method for preparation of a lubricant dispersed with carbon nanotubes (CNTs) and a lubricant dispersed with the CNTs prepared thereof. The method comprises ball milling the CNTs and purifying the ball milled CNTs to remove impurities in the CNTs. The method also comprises oxidizing surfaces of the purified CNTs by adding the purified CNTs to a solution comprising at least one oxidizing acid and then refluxing the solution. The oxidized surfaces of the CNTs are modified by adding the CNTs to a solution comprising at least one fatty acid to obtain surface modified CNTs. The method also comprises dispersing the surface modified CNTs in a lubricant to obtain the lubricant dispersed with CNTs.

Abstract: A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.

Abstract: A wiring substrate includes a wiring, a solder resist layer formed on the wiring and having an opening from which a part of the wiring is exposed, a copper seed layer formed in the opening, a copper layer formed on the seed layer and filling the opening up to a certain depth thereof, and a metal post erected on the copper layer, having an upper surface located at a position higher than an upper surface of the solder resist layer and including any one of nickel, silver and tin.

Abstract: A packaged semiconductor device includes a substrate having a ground plane, a first communication port on the substrate, a second communication port on the substrate adjacent the first communication port, and grounding structures on the substrate. Each of the grounding structures is in contact with two different locations on the ground plane and is adjacent to one of the first and second communication ports. An electrically insulating material completely covers a top side of each of the grounding structures.

Abstract: A process for fabricating a circuit substrate is provided. A dielectric layer is formed to cover a surface of a circuit stack and a patterned conductive layer, and has bonding openings exposing bonding segments of traces of the patterned conductive layer, and has plating openings exposing plating segments of the traces. A plating seed layer is formed to cover the surface of the circuit stack, the bonding segments, the plating segments, and the dielectric layer. A mask is formed to cover the plating layer and has mask openings exposing portions of the plating seed layer on the bonding segments. Portions of the plating seed layer on the bonding segments are removed with use of the mask as an etching mask. A thickening conductive layer is plated on each of the bonding segments with use of the mask as a plating mask. The mask and the plating seed layer are removed.

Abstract: An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding compound, the passivation layer including a passivation layer recess vertically aligned with the metal via, and a redistribution layer bond pad capping the metal via, a portion of the redistribution layer bond pad within the passivation layer recess projecting above a top surface of the molding compound.

Abstract: According to one embodiment, a flexible printed wiring board includes a base insulation layer, first wirings W1 on the base insulation layer, an intermediate insulation layer overlapped with the first wirings, connection pads on the intermediate insulation layer, a cover insulation layer overlapped with the connection pads and the intermediate insulation layer and including openings through which the connection pads are exposed to the cover layer, and conductive vias MT electrically connecting the first wirings to at least a part of the connection pads respectively. The conductive vias are overlapped with the connection pads in a thickness direction of the flexible printed wiring board.

Abstract: Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed.