Bump Electrode Patents (Class 438/613)
  • Patent number: 11075111
    Abstract: A method for fabricating a semiconductor device includes preparing a substrate including a first region and a second region, forming a lower alternating stack on the substrate; etching the lower alternating stack to form a lower opening in the second region, forming an upper alternating stack on the lower opening and the lower alternating stack to form recess portion caused by filling the lower opening in the second region, forming a mask layer on the upper alternating stack using the recess portion as an alignment key, and etching the upper alternating stack by using the mask layer as a barrier to form a pattern in the first region.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Hoon Kim
  • Patent number: 11049833
    Abstract: A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: June 29, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Patent number: 11037897
    Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 15, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Tadahiro Morifuji, Shigeyuki Ueda
  • Patent number: 11032904
    Abstract: An interposer substrate includes a body, first to third external connection conductors, and a wiring conductor. The body includes first to third principal surfaces. A distance between the first and second principal surfaces is different from a distance between the first and third principal surfaces. The first external connection conductor is provided on the first principal surface and is connected to an external circuit board. The second external connection conductor is provided on the second principal surface and is connected to a first flat cable. The third external connection conductor is provided on the third principal surface and is connected to a second flat cable. The wiring conductor is provided in the body, and connects the first external connection conductor and second and third external connection conductors.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: June 8, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hirokazu Yazaki, Keito Yonemori, Takanori Tsuchiya, Koji Kamada, Takashi Noma
  • Patent number: 11024560
    Abstract: A semiconductor structure including a substrate, a dielectric layer, a conductive via, and a landing pad is provided. The dielectric layer is positioned on the substrate. The conductive via penetrates from a lower surface of the substrate to an upper surface of the dielectric layer. The landing pad is embedded in the conductive via.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 1, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11014805
    Abstract: A method of making a semiconductor package includes bonding a carrier to a surface of the substrate, wherein the carrier is free of active devices, wherein the carrier includes a carrier bond pad on a surface of the carrier. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad, wherein the bonding of the wafer bond pad to the carrier bond pad comprises re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-wen Cheng, Hung-Chia Tsai, Lan-Lin Chao, Yuan-Chih Hsieh, Ping-Yin Liu
  • Patent number: 10985134
    Abstract: The present disclosure provides a method of manufacturing stacked wafers. The method includes receiving a first wafer having semiconductor components formed therein; receiving a second wafer having semiconductor components formed therein; attaching the first wafer to the second wafer; and forming a set of stacked wafers by thinning the second wafer, using the first wafer as a holder.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: April 20, 2021
    Assignee: Nanya Technology Corporation
    Inventor: Hsih-Yang Chiu
  • Patent number: 10957645
    Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a metallization layer and a dielectric layer disposed on the metallization layer. The metallization layer has conductive patterns, where each of the conductive patterns includes crystal grains, the crystal grains each are in a column shape and include a plurality of first banded structures having copper atoms oriented on a (220) lattice plane.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ming Lee, Chiang-Hao Lee, Hung-Jui Kuo, Ming-Che Ho
  • Patent number: 10896886
    Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mayukhee Das, Jonathan S. Hacker, Christopher J. Gambee, Chandra S. Tiwari
  • Patent number: 10825730
    Abstract: A method for manufacturing a solid-state imaging device comprises a first step of preparing an imaging element having a second principal surface having an electrode arranged thereon, and a photoelectric converter part configured to photoelectrically convert the incident energy line so as to generate a signal charge; a second step of preparing a support substrate, provided with a through hole extending in a thickness direction thereof, having a third principal surface; a third step of aligning the imaging element and the support substrate with each other so that the electrode is exposed out of the through hole while the second and third principal surfaces oppose each other and joining the imaging element and the support substrate to each other; and a fourth step of arranging a conductive ball-shaped member in the through hole and electrically connecting the ball-shaped member to the electrode after the third step.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: November 3, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Yasuhito Yoneta, Ryoto Takisawa, Shingo Ishihara, Hisanori Suzuki, Masaharu Muramatsu
  • Patent number: 10784221
    Abstract: A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiu-Jen Lin, Chung-Shi Liu, Ming-Da Cheng, Chung-Cheng Lin, Yu-Peng Tsai, Cheng-Ting Chen
  • Patent number: 10777496
    Abstract: The present invention is directed to a method for interconnecting two components. The first component includes a first substrate and a set of structured metal pads arranged on a main surface. Each of the pads includes one or more channels, extending in-plane with an average plane of the pad, so as to form at least two raised structures. The second interconnect component includes a second substrate and a set of metal pillars arranged on a main surface. The structured metal pads are bonded to a respective, opposite one of the metal pillars, using metal paste. The paste is sintered to form porous metal joints at the level of the channels. Metal interconnects are obtained between the substrates. During the bonding, the metal paste is sintered by exposing the structured metal pads and metal pillars to a reducing agent. The channels and raised structures improve the penetration of the reducing agent.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Luca Del Carro, Jonas Zürcher
  • Patent number: 10774427
    Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 15, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Yi Wu, Chun-Hung Lu
  • Patent number: 10766103
    Abstract: The present invention discloses a solder alloy, solder and a method for producing the same, and belongs to the field of solder. The solder alloy contains 0.9-4.1 wt % of silver, 0.3-1 wt % of copper, 0.02-0.085 wt % of rhodium, and the balance being tin, based on the total weight of the solder alloy being 100 wt %. After the solder formed by the solder alloy of the present invention is subjected to multiple reflows and tested by a ball shear test, the residual tin in the solder joint could reach at least 95%, which meets the ball shear standards required by AEC-Q100.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: September 8, 2020
    Assignee: SHANGHAI PHICHEM MATERIAL CO., LTD.
    Inventor: Yongchang Zhou
  • Patent number: 10756062
    Abstract: A semiconductor chip includes a semiconductor substrate, a through electrode, an inter-mediation pad, an upper pad, and a rewiring line. The semiconductor substrate includes a first surface that is an active surface and a second surface that is opposite to the first surface. The through electrode penetrates the semiconductor substrate and is disposed in at least one column in a first direction in a center portion of the semiconductor substrate. The inter-mediation pad is disposed in at least one column in the first direction in an edge portion of the second surface. The upper pad is disposed on the second surface and connected to the through electrode. The rewiring line is disposed on the second surface and connects the inter-mediation pad to the upper pad.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-Soo Kim, Seung-Duk Baek, Sun-Won Kang, Ho-Geon Song, Gun-Ho Chang
  • Patent number: 10734348
    Abstract: A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tung-Liang Shao, Chih-Hang Tung
  • Patent number: 10686158
    Abstract: A display device is provided. The display device includes a light-emitting unit. The light-emitting unit includes a light-emitting part, wherein a light extraction structure is disposed on a first surface of the light-emitting part. The light-emitting unit also includes a connective part disposed on a second surface opposite to the first surface of the light-emitting part. The light-emitting unit further includes a protective part surrounding the light-emitting part and the connective part. In addition, the display device includes a substrate having a plurality of active elements and at least one bonding pad, wherein the bonding pad is electrically connected to the corresponding connective part of the light-emitting unit. The roughness of the light extraction structure is greater than or equal to 0.2 ?m and less than or equal to 5 ?m.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: June 16, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Shun-Yuan Hu, Tsau-Hua Hsieh, Tzu-Min Yan, Ming-Chang Lin, Yu-Hsin Liu, Shu-Ming Kuo, Ming-I Chao
  • Patent number: 10636762
    Abstract: A method of manufacturing a semiconductor device includes a step of preparing a semiconductor element including a functional surface on which a bump is formed and an adhesive layer of a film shape including a flux component, a step of positioning the semiconductor element above a board including an electrode, a step of activating a flux component by applying ultrasonic vibration to the semiconductor element, a step of bringing the bump into contact with the electrode by pressing the semiconductor element to the board, and a step of bonding the bump to the electrode by continuing the application of the ultrasonic vibration and the pressing of the semiconductor element.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: April 28, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takatoshi Ishikawa, Teppei Kojio
  • Patent number: 10580985
    Abstract: A deposition mask and a manufacturing method thereof capable of performing vapor deposition at a desired place, without causing any gap between the deposition mask and a substrate for vapor deposition having a surface of irregularity, even when depositing a vapor deposition material only at a predetermined place on a bottom part of the substrate for vapor deposition, are provided. The manufacturing method includes preparing a dummy substrate having irregularity corresponding to a surface shape of the substrate for vapor deposition (step S1), coating a liquid resin material on an uneven surface of the dummy substrate to form a resin coating layer (step S2), and raising the temperature of the resin coating layer and baking the resin coating layer to obtain a baked resin film (step S3).
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: March 3, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Koshi Nishida, Kozo Yano, Katsuhiko Kishimoto
  • Patent number: 10580665
    Abstract: A package structure includes an interconnection layer; a passivation layer disposed on the interconnection layer, in which the interconnection layer and the passivation layer defined at least one opening; at least one elastic bump disposed on the interconnection layer, in which a portion of the elastic bump is embedded in the opening; and a conductive layer disposed on the elastic bump.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Patent number: 10522501
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10510714
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Chun Tang, Chuei-Tang Wang, Chun-Lin Lu, Wei-Ting Chen, Vincent Chen, Shou-Zen Chang, Kai-Chiang Wu
  • Patent number: 10304797
    Abstract: An apparatus and method for soldering chips to a substrate. A substrate and two or more different chips having different heating properties are provided. A solder material is disposed between the chips and the substrate. A flash lamp generates a light pulse for heating the chips, wherein the solder material is at least partially melted by contact with the heated chips. A masking device is disposed between the flash lamp and the chips causing different light intensities in different areas of the light pulse passing the masking device thereby heating the chips with different light intensities. This may compensate the different heating properties to reduce a spread in temperature between the chips as a result of the heating by the light pulse.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 28, 2019
    Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO
    Inventors: Gari Arutinov, Edsger Constant Pieter Smits, Jeroen van den Brand
  • Patent number: 10295832
    Abstract: The present disclosure is to provide a slit grating applied in autostereoscopic display apparatus and autostereoscopic display apparatus. The slit grating includes a substrate and a plurality of light-shielding strips arranged in intervals on the substrate; the light-shielding strips is used to shielding incident light; the slit grating further includes a wire grid among a light-transmitting region between the light-shielding strips, and the wire grid is used to transmitting a first polarized component of the incident light and reflecting a second polarized component that is perpendicular to the first polarized component of the incident light. The autostereoscopic display apparatus includes a backlight module, a liquid crystal display and the slit grating. The present disclosure can improve brightness of display device, and achieve cost decreasing and thickness reducing at the same time.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 21, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Guowei Zha
  • Patent number: 10192741
    Abstract: According to one embodiment, a device substrate includes a multilayer film that includes a film constituting a device element and is disposed on a substrate. A main face on which the device element is disposed includes a patterning region on which a resist is to be applied during an imprint process, and a bevel region provided as a region from a peripheral edge portion of the patterning region to an end portion of the device substrate. The bevel region includes a region where an upper surface of the bevel region becomes lower toward the end portion of the device substrate relative to an upper surface of the patterning region. The upper surface of the bevel region has an inclination angle of 10° or more and 90° or less with respect to the upper surface of the patterning region, at a boundary between the patterning region and the bevel region.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: January 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takahito Nishimura, Yoshihisa Kawamura, Kazuhiro Takahata, Ikuo Yoneda, Yoshiharu Ono
  • Patent number: 10192838
    Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: January 29, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Lung Chuang, Po-Yi Wu, Meng-Tsung Lee, Yih-Jenn Jiang
  • Patent number: 10062657
    Abstract: In order to manufacture an alloy bump, a resist pattern having openings which expose a substrate is formed on the substrate, an under-bump metal is formed on the substrate inside the openings, a first plating film is formed on the under-bump metal by electroplating, a second plating film containing no metal components which are contained in the first plating film is formed on the first plating film by electroplating, the resist pattern is removed, and the alloy bump is formed by heat treating the substrate to thereby alloy the first plating film and the second plating film.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: August 28, 2018
    Assignee: ISHIHARA CHEMICAL CO., LTD.
    Inventors: Shoya Iuchi, Masaru Hatabe
  • Patent number: 9955578
    Abstract: A circuit structure includes a patterned circuit layer, a patterned insulating layer and a support plate. The patterned insulating layer covers a portion of the patterned circuit layer, wherein an upper surface of the patterned circuit layer is aligned with a top surface of the patterned insulating layer. The support plate is disposed on a bottom surface of the patterned insulating layer, wherein the support plate, the patterned insulating layer and the patterned circuit layer define a plurality of air gaps.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: April 24, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Chia-Chan Chang, Gwo-Chaur Chen, Yung-Tsai Chen
  • Patent number: 9870988
    Abstract: A semiconductor substrate is provided with an annular cavity extending from a front side of the substrate to an opposite rear side. A metallization is applied in the annular cavity, thereby forming a through-substrate via and leaving an opening of the annular cavity at the front side. A solder ball is placed above the opening and a reflow of the solder ball is effected, thereby forming a void of the through-substrate via, the void being covered by the solder ball.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: January 16, 2018
    Assignee: ams AG
    Inventors: Cathal Cassidy, Martin Schrems, Franz Schrank
  • Patent number: 9831205
    Abstract: A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen, Tsung-Yuan Yu
  • Patent number: 9779965
    Abstract: A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures. A bonding surface of at least one of the first conductive structures and the second conductive structures includes a frangible coating.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: October 3, 2017
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventors: Robert N. Chylak, Dominick A. DeAngelis, Horst Clauberg
  • Patent number: 9773729
    Abstract: A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening. A reflow of the solder ball is performed in such a way that the solder ball closes the through-substrate via and leaves a void in the through-substrate via.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 26, 2017
    Assignee: ams AG
    Inventors: Cathal Cassidy, Martin Schrems, Franz Schrank
  • Patent number: 9768138
    Abstract: A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Chen-Shien Chen, Chen-Cheng Kuo, Ming-Fa Chen, Rung-De Wang
  • Patent number: 9754995
    Abstract: A method for manufacturing a solid-state imaging device comprises a first step of preparing an imaging element including a second principal surface having an electrode arranged thereon, and a photoelectric converter part configured to photoelectrically convert the incident energy line so as to generate a signal charge; a second step of preparing a support substrate, provided with at least one through hole extending in a thickness direction thereof, having a third principal surface; a third step of aligning the imaging element and the support substrate with each other so that the one electrode is exposed out of the one through hole while the second and third principal surfaces oppose each other and joining the imaging element and the support substrate to each other; and a fourth step of embedding a conductive member in the through hole after the third step.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: September 5, 2017
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Yasuhito Yoneta, Ryoto Takisawa, Shingo Ishihara, Hisanori Suzuki, Masaharu Muramatsu
  • Patent number: 9728672
    Abstract: A light-emitting diode (LED) and a method for manufacturing the same are provided. The method includes following steps. An LED wafer is fixed on a crafting table and is processed such that a substrate of the LED wafer has a thickness smaller than or equal to 100 ?m. A fixing piece is pasted on the LED wafer surface. The LED wafer is detached from the crafting table. The LED wafer together with the fixing piece are cut and broken, such that the LED wafer forms a plurality of LEDs. The fixing piece is removed. Before the LED wafer is detached from the crafting table, the fixing piece is pasted on the LED wafer to provide a supporting force to the LED wafer to maintain the flatness of the wafer and avoid the wafer being warped or the substrate being broken or damaged, such that product quality and reliability can be improved.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: August 8, 2017
    Assignee: GENESIS PHOTONICS INC.
    Inventors: Shao-Ying Ting, Jing-En Huang
  • Patent number: 9711472
    Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hua Chang, Cheng-Lin Huang, Jing-Cheng Lin
  • Patent number: 9704841
    Abstract: A wafer package process includes the following steps. A wafer with a plurality of first dies is provided. A plurality of second dies are bonded on the first dies by using flip chip technology, wherein the size of the first die is larger than that of the second die. A molding material is formed to entirely cover the second dies and the wafer. A through via is formed in the molding material. A conductive material is formed to fill the through via onto the molding material.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: July 11, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Li Kuo
  • Patent number: 9559044
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao
  • Patent number: 9524944
    Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion d having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: December 20, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-Wei Yeh, Chun-Hsien Shen, Hsiu-Jung Li, Ya-Yi Lai, Fu-Tang Huang
  • Patent number: 9521749
    Abstract: A circuit substrate which is capable of decreasing the possibility that the amount of solder in the overall mounting land is uneven and reducing formation of a solder void even when a mounting terminal has a large soldering area. An electronic component having the mounting terminal is mounted on the circuit substrate. A mounting land is connected to the mounting terminal of the electronic component by soldering, and the mounting land has a protruding portion of an insulating material formed so as to protrude from an outer side of the mounting land toward an inner side of the mounting land, and the protruding portion does not divide the mounting land into a plurality of areas.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: December 13, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koichi Odagaki, Shuichi Kato
  • Patent number: 9515018
    Abstract: A wiring substrate includes an insulating layer, a wiring layer, a via wiring, and a solder resist layer. The wiring layer includes a pad body that constitutes a part of a pad and a wiring pattern including an upper surface. The pad includes the pad body, a first metal layer formed on an upper surface of the pad body and including an embedded part embedded in the insulating layer and a projecting part including upper and side surfaces and projecting from the upper surface of the insulating layer, and a second metal layer including an upper surface and covering the upper and side surfaces of the projecting part. The upper surface of the pad body and the upper surface of the wiring pattern are on the same plane. The upper surface of the second metal layer is positioned lower than the upper surface of the solder resist layer.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 6, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Tomohiro Suzuki
  • Patent number: 9466553
    Abstract: Disclosed herein is a method for manufacturing a package structure. According to an exemplary embodiment of the present invention, the method for manufacturing a package structure includes: preparing a die having a metal pillar disposed on one surface thereof; bonding the die on the metal plate to allow the metal pillar to face the outside; forming an insulating film covering the metal plate and the die; buffing the insulating film so as to expose the metal pillar; and manufacturing a first package structure by forming a circuit structure electrically connected to the metal pillar on the insulating film.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: October 11, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Heung Ku Kim
  • Patent number: 9466577
    Abstract: A semiconductor device is made by forming a first conductive layer over a substrate, forming a first passivation layer over the first conductive layer, forming a first via in the first passivation layer to expose the first conductive layer, forming a second conductive layer over the first passivation layer and within the first via to electrically connect to the first conductive layer, forming a second passivation layer over the second conductive layer, and forming a second via in the second passivation layer to expose the second conductive layer. The second via is smaller than the first via. The second via is either physically separate from or disposed over the first via. The second conductive layer within the second via has a flat surface which is wider than the second via. An under bump metallization is formed in the second via and electrically connected to the second conductive layer.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: October 11, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Yaojian Lin
  • Patent number: 9449913
    Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: September 20, 2016
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, Mark T. Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju, Hang-Shing Ma
  • Patent number: 9443837
    Abstract: An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact electrically coupled with the terminal. A first element has a first surface facing the first surface of the substrate, a first conductor at the first surface and a second conductor at a second surface. An interconnect structure may extend through the first element electrically coupling the first and second conductors. An adhesive layer may bond first surfaces of the first element and the substrate, and at least portions of the first conductor and the substrate conductor may be beyond an edge of the adhesive layer. A continuous electroless plated metal region may extend between the first conductor and the substrate conductor.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: September 13, 2016
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Cyprian Emeka Uzoh
  • Patent number: 9431359
    Abstract: A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: August 30, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brian M. Erwin, Ian Melville, Ekta Misra, George J. Scott
  • Patent number: 9412653
    Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: August 9, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chun-Ling Lin, Huei-Ru Tsai, Ching-Wei Hsu, Chin-Fu Lin, Hsin-Yu Chen
  • Patent number: 9406645
    Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: August 2, 2016
    Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Razu
  • Patent number: 9391036
    Abstract: A semiconductor device includes a first semiconductor electronic component which includes a pad electrode, a solder bump, and a metal layer between a pad and solder that is configured to have an underlying metal layer formed between the pad electrode and the solder bump and connected to the pad electrode, and a main metal layer formed on the underlying metal layer, and in which the main metal layer has an eave portion at an outer edge portion thereof.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: July 12, 2016
    Assignee: SONY CORPORATION
    Inventors: Katsuji Matsumoto, Hiizu Ootorii
  • Patent number: 9373565
    Abstract: A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: June 21, 2016
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht