Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.

Abstract: A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.

Abstract: A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

Abstract: An electronic assembly includes a copper pillar attach substrate that has a dielectric layer and a solder resist layer overlying the dielectric layer. The solder resist layer has a plurality of solder resist openings. A plurality of parallel traces are formed on the dielectric layer. Each trace has a first end portion, a second end portion and an intermediate portion. The first and second end portions of each trace are covered by the solder resist layer and the intermediate portions are positioned in the solder resist openings. Each of the intermediate portions has at least one conductive coating layer on it and has a height measured from the dielectric layer to the top of the topmost conductive coating layer that is at least as great as the solder resist layer thickness.

Abstract: An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer.

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

Abstract: A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

Abstract: A method of forming an integrated circuit device comprises forming a metal pillar over a semiconductor substrate. The method also comprises forming a solder layer over the metal pillar. The method further comprises forming a metallization layer comprising a cobalt (Co) element, the metallization layer covering the metal pillar and the solder layer. The method additionally comprises thermally reflowing the solder layer to form a solder bump, driving the Co element of the metallization layer into the solder bump. The method also comprises oxidizing the metallization layer to form a metal oxide layer on a sidewall surface of the metal pillar.

Abstract: A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.

Abstract: A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.

Abstract: A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a photoresist pattern having a side recess on a seed metal layer and forming a plating layer having a hem using a plating process to fill the side recess.

Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion and having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.

Abstract: A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon.

Abstract: In a method of improving ball strength of a semiconductor device, a ball pattern of a plurality of connection balls to be formed as electrical connections for the semiconductor device is received. The pattern includes a number of columns and rows crossing each other. The balls are arranged at intersections of the columns and rows. An arrangement of balls in a region of the ball pattern is modified so that the region includes no isolated balls.

Abstract: A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.

Abstract: A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer. The copper-containing electrical conductor is bonded to the at least one additional metal layer of the semiconductor die via an electrically conductive coating of the copper-containing electrical conductor which is softer than the copper of the copper-containing electrical conductor.

Abstract: A semiconductor structure includes a semiconductor chip having at least an electrode pad, a first metal layer formed on the electrode pad, a second metal layer completely formed on and in contact with the first metal layer, and a conductive pillar disposed on the second metal layer, where a material of the first metal layer is different from a material of the second metal layer, the first metal layer has a first distribution-projected area larger than a second distribution projected-area of the conductive pillar, and the second metal layer has a third distribution-projected area that is the same as the second distribution-projected area of the conductive pillar.

Abstract: A method for joining integrated circuit (IC) die. The includes pressing the IC die toward a workpiece so that a protruding bonding feature is inserted into a cavity of a receptacle through an opening. The pressing bends peripheral shelf regions downward into the cavity and towards sidewall portions of the receptacle to form bent peripheral shelf regions. A protruding bonding feature contacts the bent peripheral shelf regions along a contact area. The contact area being at least primarily along the sidewall surfaces of the protruding bonding feature.

Abstract: A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.

Abstract: A method includes coating a photo resist over an Under-Bump Metallurgy (UBM) layer and exposing the photo resist. In the step of exposing, a light amount reaching a bottom of the photo resist is less than about 5 percent of a light amount reaching a top surface of the photo resist. The method further includes developing the photo resist to form an opening in the photo resist. A portion of the UBM layer is exposed through the opening. The opening has a bottom lateral dimension greater than a top lateral dimension. An electrical connector is formed in the opening, wherein the electrical connector is non-reflowable.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed.

Abstract: A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.

Abstract: A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 ?m to 1.0 ?m. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer.

Abstract: The present disclosure relates to a tool arrangement and method to reduce warpage within a package-on-package semiconductor structure, while minimizing void formation within an electrically-insulating adhesive which couples the packages. A pressure generator and a variable frequency microwave source are coupled to a process chamber which encapsulates a package-on-package semiconductor structure. The package-on-package semiconductor structure is simultaneously heated by the variable frequency microwave source at variable frequency, variable temperature, and variable duration and exposed to an elevated pressure by the pressure generator. This combination for microwave heating and elevated pressure limits the amount of warpage introduced while preventing void formation within an electrically-insulating adhesive which couples the substrates of the package-on-package semiconductor structure.

Abstract: A method includes forming a polymer layer over a passivation layer, wherein the passivation layer further comprises a portion over a metal pad. The polymer layer is patterned to form an opening in the polymer layer, wherein exposed surfaces of the polymer layer have a first roughness. A surface treatment is performed to increase a roughness of the polymer layer to a second roughness greater than the first roughness. A metallic feature is formed over the exposed surface of the polymer layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is more than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.

Abstract: A semiconductor device in which reliability of a bonding pad to which a conductive wire is bonded is achieved. A bonding pad having an OPM structure is formed of an Al—Cu alloy film having a Cu concentration of 2 wt % or more. By increasing the Cu concentration, the Al—Cu alloy film forming the bonding pad is hardened. Therefore, the bonding pad is difficult to be deformed by impact in bonding of a Cu wire, and deformation of an OPM film as following the deformation of the bonding pad can be reduced. In this manner, concentration of a stress on the OPM film caused by the impact from the Cu wire can be reduced, and therefore, the breakage of the OPM film can be prevented.

Abstract: According to one embodiment, a semiconductor device manufacturing method provides filling a through-hole which penetrates through a first side of substrate to a second side thereof. A seed film including copper is formed on the inner wall surface of the through-hole. A first metal layer including copper is grown bottom-up from one end of the through-hole toward the other end thereof, to partially fill the through-hole, leaving a space having a depth less than the radius of the through-hole as measured from the second side surface of the substrate. A second metal layer including nickel is conformally grown in the space from the inner peripheral surface of the through-hole to a height having a summit surface protruding from the second side surface of the substrate. A third metal layer is formed on the summit surface of the second metal layer.

Abstract: Electronic device packages and related methods are provided. The electronic device package includes a first substrate having a first contact portion disposed thereon, a bump having a first contact surface connected to the first contact portion and a second contact surface disposed opposite to the first contact surface, and a buffer spring pad portion between the first contact portion of the first substrate and the first contact surface of the bump. The buffer spring pad portion includes at least two different conductive material layers which are stacked.

Abstract: A method of fabricating a package substrate including preparing a substrate having at least one conductive pad, forming an insulating layer having an opening to expose the conductive pad on the substrate, forming a separation barrier layer on the conductive pad inside the opening to be higher than the upper surface of the insulating layer along the side walls thereof, forming a post terminal on the separation barrier layer, and forming a solder bump on the post terminal.

Abstract: An integrated circuit with distributed power using through-silicon-vias (TSVs) is presented. The integrated circuit has conducting pads for providing power and ground located within the peripheral region of the top surface. A number of through-silicon-vias are distributed within the peripheral region and a set of TSVs are formed within the non-peripheral region of the integrated circuit. Conducting lines on the bottom surface are coupled between each peripheral through-silicon-via and a corresponding non-peripheral through-silicon-via. Power is distributed from the conducting pads to the TSVs within the non-peripheral region through the TSVs within the peripheral region, thus supplying power and ground to circuits located within the non-peripheral region of the integrated circuit chip.

Abstract: A device and fabrication techniques are described that employ wafer-level packaging techniques for fabricating semiconductor devices that include a pad defined contact. In implementations, the wafer-level package device that employs the techniques of the present disclosure includes a substrate, a passivation layer, a top metal contact pad, a thin film with a via formed therein, a redistribution layer structure configured to contact the top metal contact pad, and a dielectric layer on the thin film and the redistribution layer structure. In implementations, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, forming a passivation layer, depositing a top metal contact pad, forming a thin film with a via formed therein, forming a redistribution layer structure in the via formed in the thin film, and forming a dielectric layer on the thin film and the redistribution layer structure.

Abstract: Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.

Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

Abstract: One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

Abstract: A method of manufacturing a semiconductor device having a transition layer, including (a) forming a wiring and a die pad on a wafer, (b) forming a thin film layer on an entire surface of the wafer obtained in the step (a), (c) forming a resist layer on the thin film layer, and forming a thickening layer on a resist layer unformed section, (d) peeling the resist layer, (e) removing the thin film layer by etching, and (f) dividing the wafer to thereby form semiconductor devices.

Abstract: A semiconductor package and a method for fabricating the same. The semiconductor package includes a first substrate including a first pad, a second substrate spaced apart from the first substrate and where a second pad is formed to face the first pad, a first bump electrically connecting the first pad to the second pad, and a second bump mechanically connecting the first substrate to the second substrate is disposed between the first substrate where the first pad is not formed and the second substrate where the second pad is not formed. A coefficient of thermal expansion (CTE) of the second bump is smaller than that of the first bump.

Abstract: An embodiment is an integrated circuit structure including a first die attached to a second die by a first connector. The first connector includes a solder joint portion between a first nickel-containing layer and a second nickel-containing layer, a first copper-containing layer between the first nickel-containing layer and the solder joint portion, and a second copper-containing layer between the second nickel-containing layer and the solder joint portion.

Abstract: A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a copper-containing metallization layer, a nickel-containing metallization layer, and a first intermetallic compound (IMC) layer between the copper-containing metallization layer and the nickel-containing metallization layer. The first IMC layer is in direct contact with the copper-containing metallization layer and the nickel-containing metallization layer.

Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.

Abstract: Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.

Abstract: A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.

Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.

Abstract: A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.

Abstract: Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.