Abstract: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.

Abstract: A semiconductor metal structure with an efficient usage of the chip area is provided. The structure includes a substrate, a copper-based interconnection structure over the substrate, the copper-based interconnection structure comprising a plurality of metallization layers connected by vias and in first dielectric layers, at least one aluminum-based layer over and connected to the copper-based interconnection structure, wherein a top layer of the at least one aluminum-based layer comprises a bond pad and an interconnect line connecting to two underlying vias, vias/contacts connecting a top layer of the copper-based interconnection structure and a bottom layer of the at least one aluminum-based layer, wherein the vias/contacts are in a second dielectric layer, and a third dielectric layer overlying the at least one aluminum-based layer, wherein the bond pad is exposed through an opening in the third dielectric layer.

Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.

Abstract: A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is formed on the passivation layer. The first patterned photoresist layer has a plurality of second openings exposing a portion of each of the pads. A plurality of first bumps is formed in the second openings, respectively. An under ball metal (UBM) material layer is formed over the substrate to cover the first patterned photoresist layer and the first bumps. A plurality of conductive lines is formed on the UBM material layer. The UBM material layer is patterned to form a plurality of UBM layers using the conductive lines as a mask.

Abstract: A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu-OSP can be formed over the substrate.

Abstract: A print mask is used to form bumps on barrier metal layers of a wafer. The mask comprises a plurality of elongated perforations disposed in a linear arrangement such that paste can be applied to an object to be printed on via the perforations. Each of the perforations includes an edge disposed along the longitudinal direction, and the edge is inclined with respect to the direction perpendicular to the direction of arranging the perforations.

Abstract: A manufacturing method for a semiconductor device, including the steps of: forming a passivation film that covers a surface of a semiconductor substrate on which electrodes have been formed, in which an opening is formed so as to expose a predetermined electrode from among the electrodes; forming a diffusion prevention plug of a first metal in the vicinity of the opening in the passivation film; supplying a second metal material to the surface of the semiconductor substrate on which the diffusion prevention plug has been formed, so as to form a seed layer of the second metal; forming a resist film that covers the seed layer and in which an opening is formed so as to expose a predetermined region of the seed layer on the diffusion prevention plug; supplying a third metal material into the opening in the resist film so as to form a protrusion electrode of the third metal; removing the resist film after the step of forming a protrusion electrode; and removing the seed layer after the step of forming a protrusion

Abstract: A combined thermal interface material and second layer interconnect reflow material and method are disclosed.

Abstract: A semiconductor device includes a semiconductor substrate, a first metal film on a back surface of the semiconductor substrate, a second metal film on the first metal film, and a third metal film on the second metal film. The first metal film forms an alloy with a solder. The second metal film causes isothermal solidification of the solder. The third metal film improves solder wetting properties or inhibits oxidation. Further, in a method for die-bonding a semiconductor device, a specific metal is diffused into a solder, when the solder melts, to transform the solder into a high melting point alloy, thereby causing isothermal solidification of the solder. The specific metal is different from the metal of the solder.

Abstract: An improved semiconductor device interconnect structure comprising a dielectric layer recessed with respect to the conductive interconnect features. This structure and method reduces embedded metallic residues from CMP scratches and metal cap applications and provides improved mechanical integrity at the capping layer/liner/dielectric interface.

Abstract: A substrate for device bonding is provided, which enables bonding of a device with high bond strength to an Au electrode formed on a substrate such as aluminum nitride by soldering the device at a low temperature using a soft solder metal having a low melting point such as an Au—Sn-based solder having an Au content of 10% by weight. The substrate for device bonding comprises a substrate having an Au electrode layer formed on its surface and in which (i) a layer composed of a platinum group element, (ii) a layer composed of at least one transition metal element selected from the group consisting of Ti, V, Cr and Co, (iii) a barrier metal layer composed of at least one metal selected from the group consisting of Ag, Cu and Ni and (iv) a solder layer composed of a solder containing Sn or In as a main component are laminated in this order on the Au electrode layer.

Abstract: Provided is a semiconductor device. The semiconductor device includes a first bump column on an active surface of the semiconductor device and including a plurality of first bumps spaced a first distance from an edge of the semiconductor device, a second bump column on the active surface and including a plurality of second bumps spaced a second distance that is greater than the first distance from the edge of the semiconductor device, and a third bump column on the active surface, and including a plurality of third bumps spaced a third distance that is greater than the second distance from the edge of the semiconductor device. The second bumps and the third bumps are sequentially alternated at least twice between the first bumps.

Abstract: A connection structure includes a semiconductor die having a first major surface and an electrically conductive substrate having a second major surface. At least part of the second major surface is positioned facing towards and spaced at a distance from the first major surface. A galvanically deposited metallic layer extends between the first major surface and the second major surface and electrically connects the first major surface and the second major surface.

Abstract: Embodiments relate to a passivation fabricating method. In the passivation fabricating method according to embodiments, a first oxide film may be formed by repeating deposition and etching of an oxide film on a silicon substrate in which an upper metal pad may be formed and a second oxide film may be formed by performing only deposition on the first oxide film. A thickness of the first oxide film may be set to be above 5 k?. A first passivation layer may be formed by planarizing the first and second oxide films. In the planarizing process, a thickness of the first passivation layer may be 4 k?. A second passivation layer of a nitride film may be formed on the first passivation layer and the first and second passivations may be selectively etched so as to expose the upper metal pad.

Abstract: A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.

Abstract: A method is described for packaging integrated circuit dice such that each package includes a die with an integrated passive component mounted to the active surface of the die.

Abstract: A controlled collapse chip connection (C4) method and integrated circuit structure for lead (Pb)-free solder balls with stress relief to the underlying insulating layers of the integrated circuit chip by deposing soft thick insulating cushions beneath the solder balls and connecting the metallization of the integrated circuit out-of-contact of the cushions but within the pitch of the solder balls.

Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.

Abstract: A structure and a method for forming the same. The structure includes a first dielectric layer, an electrically conductive bond pad on the first dielectric layer, and a second dielectric layer on top of the first dielectric layer and the electrically conductive bond pad. The electrically conductive bond pad is sandwiched between the first and second dielectric layers. The second dielectric layer includes N separate final via openings such that a top surface of the electrically conductive bond pad is exposed to a surrounding ambient through each final via opening of the N separate final via openings. N is a positive integer greater than 1.

Abstract: A method for reduction of soft error rates in integrated circuits. The method including: providing a test device, the test device comprising: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level on a top surface of the substrate; selecting an energy of alpha particles of a given energy to be stopped from penetrating through the stack of one or more wiring levels; bombarding the semiconductor substrate with a flux of the alpha particles of the selected energy; and determining a combination of a thickness of a blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of the maximum energy striking a top surface of the blocking layer from penetrating through the stack of one or more wiring levels.

Abstract: In a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed above the first conductive posts. The second conductive posts are electrically connected to the first conductive posts. Then, a second insulating layer is formed so as to cover the second conductive posts. The second insulating layer is made of adhesive resin. Finally, a semiconductor device is adhered to the second conductive posts by the second insulating layer while a gap between the first semiconductor device and the first insulating layer is sealed by the second insulating layer.

Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

Abstract: A method to provide direct bonding of wires to silicon for microelectronic and micro-electromechanical systems (MEMS). The method includes preparing a rough “pothole” during one of the many deep etch steps already provided in MEMS fabrication. The method also includes roughening of the smooth silicon surface in and around the rough pothole and plastically deforming a ball-bond into the rough pothole, such that the interconnection will eliminate a costly metallization layer, and thereby lower fabrication expenses and allow high temperature processing.

Abstract: Methods to form a three-dimensionally curved pad in a substrate and integrated circuits incorporating such a substrate are disclosed. An example method to form a three-dimensionally curved pad comprises isotropically etching a portion of a surface of a substrate to form a recess having a radial shape, forming a conductive layer in the recess to form the bonding pad, and placing a conductive element in the pad.

Abstract: A semiconductor device is provided configured to be electrically connected to another device by through silicon interconnect technology. The semiconductor device includes a semiconductor substrate with at least one through hole. A through silicon conductor extends inside the through hole from the upper side to the bottom side of the semiconductor substrate. The through silicon conductor is electrical isolated from the semiconductor substrate and includes a conductor bump at one of its ends. Between the inner surface of the through hole and the through silicon conductor a gap is formed. The gap surrounds the through silicon conductor on one side of the semiconductor substrate having the conductor bump, and extends from this side of the substrate into the substrate. The gap is filled with a flexible dielectric material.

Abstract: A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, the semiconductor device may include a semiconductor substrate formed with a metal interconnection, a first interlayer dielectric layer formed on the metal interconnection and having a first contact plug, a second interlayer dielectric layer formed on the first interlayer dielectric layer and having a second contact plug, and a third interlayer dielectric layer formed on the second interlayer dielectric layer and having a third contact plug, wherein the first to third contact plugs are connected to each other.

Abstract: A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate. The bonding regions are preferably formed by a thick layer of a material chosen from among aluminum, copper and nickel, covered by a thin layer of a material chosen from between palladium and platinum. Spacing regions ensure exact spacing between the two wafers.

Abstract: A conductive structure of a chip and a method for manufacturing the conductive structure are provided. An under bump metal (UBM) is formed on the redistribution layer (RDL) by performing an electroless plating process. Subsequently, the solder bump is formed on the under bump metal for electrical connection. Thus, the photomask can be economized and the cost of manufacturing can be reduced.

Abstract: A semiconductor device has a semiconductor die with a solder bump formed on its surface. A contact pad is formed on a substrate. A signal trace is formed on the substrate. The pitch between the contact pad and signal trace is less than 150 micrometers. An electroless surface treatment is formed over the contact pad. The electroless surface treatment can include tin, ENIG, or OSP. A film layer is formed over the contact pad with an opening over the signal trace. An oxide layer is formed over the signal trace. The film layer and surface treatment prevent formation of the oxide layer over the contact pad. The film layer is removed. The solder bump is reflowed to metallurgically and electrically bond to the contact pad. In the event that the solder bump physically contacts the oxide layer, the oxide layer maintains electrical isolation between the solder bump and signal trace.

Abstract: An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Abstract: An interconnect structure for a semiconductor device is made by forming a contact pad on a substrate, forming an under bump metallization layer over the contact pad, forming a photoresist layer over the substrate, removing a portion of the photoresist layer to form an opening which exposes the UBM, depositing a first conductive material into the opening of the photoresist, removing the photoresist layer, depositing a second conductive material over the first conductive material, and coating the second conductive material with an organic solderability preservative. The interconnect structure is formed without solder reflow. The first conductive layer is nickel and the second conductive layer is copper. The organic solderability preservative is made with benzotriazole, rosin, rosin esters, benzimidazole compounds, or imidazole compounds. The interconnect structure decreases the pitch between the core pillars in the interconnect array and increases the density of I/O contacts on the semiconductor device.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.

Abstract: Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.

Abstract: By patterning the underbump metallization layer stack on the basis of a dry etch process, significant advantages may be achieved compared to conventional techniques involving a highly complex wet chemical etch process. In particular embodiments, a titanium tungsten layer or any other appropriate last layer of an underbump metallization layer stack may be etched on the basis of a plasma etch process using a fluorine-based chemistry and oxygen as a physical component. Moreover, appropriate cleaning processes may be performed for removing particles and residues prior to and after the plasma-based patterning process.

Abstract: An uppermost one of multilayered electrode pads, on which a bump and a plating coat will be formed, is made of metal having high ionization tendency, particularly, Al. On the other hand, an uppermost one of multilayered electrode pads, on which none of the bump and the plating coat will be formed, is made of metal having low ionization tendency, particularly, Cu.

Abstract: There is provide a semiconductor device manufacturing method, including: preparing a substrate; laminating an insulation layer on the substrate; laminating a first underlying metal layer on the insulation layer; forming rewiring on the first underlying metal layer; removing exposed portions of the first underlying metal layer; laminating a second underlying metal layer on the rewiring and the insulation layer; forming a column electrode on the rewiring via the second underlying metal layer; and removing exposed portions of the second underlying metal layer.

Abstract: Disclosed is a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip that includes metal pads provided on a predetermined area of an upper side of a semiconductor substrate, where element structures used to manufacture a semiconductor element are formed, and bump electrodes connected to the metal pads; and a passivation film that is provided on an entire surface of the semiconductor chip other than upper surface of the bump electrodes. Therefore, it is possible to avoid difficulties in performing an epoxy underfill process used in a conventional flip chip bonding, and complexity and high cost resulting from the use of a molding compound process and a solder ball process. It is also possible to prevent damages to the lateral surface of the semiconductor chip due to an absence of the passivation film on the lateral surface of the semiconductor chip in a conventional wafer level package.

Abstract: A conductive line structure of a semiconductor device, the structure comprising a substrate having bonding pad; a first dielectric layer formed over the substrate; a solder pad formed over the first dielectric layer; a buffer scheme formed over the first dielectric layer and between the bonding pad and the solder pad; a conductive line formed over the buffer scheme for coupling between the bonding pad and the solder pad; a second dielectric layer formed over the conductive line to expose the solder pad; and a solder ball formed over the solder pad.

Abstract: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.

Abstract: The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate, a first passivation film covering an end portion of the pad electrode and having a first opening on the pad electrode, a plating layer formed on the pad electrode in the first opening, a second passivation film covering an exposed portion of the pad electrode between an end portion of the first passivation film and the plating layer, covering an end portion of the plating layer, and having a second opening on the plating layer, and a conductive terminal formed on the plating layer in the second opening.

Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Abstract: A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure.

Abstract: A method producing conductive rods localized on conductive blocks of an electronic component.

Abstract: Methods of forming a conductive via in a substrate include contacting the substrate with a wave of conductive liquid material, such as molten solder, and drawing the liquid material into the aperture with a vacuum. The wave may be formed by flowing the liquid material out from an outlet in a direction generally against the gravitational field. The liquid material may be solidified to form an electrically conductive structure. A plurality of apertures may be selectively filled with the liquid material one at a time, and liquids having different compositions may be used to provide conductive vias having different compositions in the same substrate. Systems for forming conductive vias include a substrate fixture, a vacuum device having a vacuum fixture, and a solder-dispensing device configured to provide a wave of molten solder material. Relative lateral and vertical movement is provided between the wave of molten solder and a substrate supported by the substrate fixture.

Abstract: A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO2 film provided on the silicon substrate, copper films embedded in the SiO2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO2 film, and SiON films covering an upper face of the TiN films.

Abstract: Provided is a semiconductor device including a wafer having an electrode pad; an insulating layer that is formed on the wafer and has an exposure hole formed in one side thereof, the exposure layer exposing the electrode pad, and a support post formed in the other side, the support post having a buffer groove; a redistribution layer that is formed on the top surface of the insulating layer and has one end connected to the electrode pad and the other end extending to the support post; an encapsulation layer that is formed on the redistribution layer and the insulating layer and exposes the redistribution layer formed on the support post; and a solder bump that is provided on the exposed portion of the redistribution layer.

Abstract: An LGA substrate includes a core (110), having build-up dielectric material (150), at least one metal layer (125), and solder resist (155) formed thereon, an electrically conductive land grid array pad (120) electrically connected to the metal layer, a nickel layer (121) on the electrically conductive land grid array pad, a palladium layer (122) on the nickel layer, and a gold layer (123) on the palladium layer.

Abstract: A method for fabricating an electrical conductive structure of a circuit board is disclosed. The method includes providing a circuit board having a plurality of first and second electrically conductive pads; forming on the circuit board an insulating protection layer having a plurality of openings for exposing the first and second electrically conductive pads; forming a metal adhesive layer on the first and second electrically conductive pads; forming a conductive layer on the insulating protection layer and on the metal adhesive layer formed on the first and second electrically conductive pads, the conductive layer being electrical conductive to the first and second electrically conductive pads; forming on the conductive layer a resist layer having a plurality of openings for exposing the conductive layer on the second electrically conductive pads; and electroplating a conductive structure on the conductive layer on the second electrically conductive pads exposed from the openings.

Abstract: A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess, using the barrier layer to conduct electrical current.