Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

Abstract: A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.

Abstract: A method for forming, on a surface of a thinned-down semiconductor substrate, a contact connected to a metal track of an interconnect stack formed on the opposite surface of the thinned-down substrate, including the steps of: forming, on the side of a first surface of a substrate, an insulating region penetrating into the substrate and coated with a conductive region and with an insulating layer crossed by conductive vias, the vias connecting a metal track of the interconnect stack to the conductive region; gluing the external surface of the interconnect stack on a support and thinning down the substrate; etching the external surface of the thinned-down substrate and stopping on the insulating region; etching the insulating region and stopping on the conductive region; and filling the etched opening with a metal.

Abstract: An integrated circuit system with one or more copper interconnects is provided. The one or more copper interconnects are in conductive contact with a substrate. The integrated circuit system includes a first dielectric layer, a copper material filling a first via through the first dielectric layer, a second dielectric layer in contact with the first dielectric layer, and a diffusion barrier layer. The diffusion barrier layer at least partially fills a second via through the second dielectric layer. At least a first part of the diffusion barrier layer is in direct contact with the copper material, and at least a second part of the diffusion barrier layer is in direct contact with the second dielectric layer. The integrated circuit system further includes a gold material at least partially filling the second via. The gold material is conductively connected with the copper material through the diffusion barrier layer and conductively connected with a substrate.

Abstract: A method of fabricating a thin wafer die includes creating circuits and front-end-of-line wiring on a silicon wafer, drilling holes in a topside of the wafer, depositing an insulator on the drilled holes surface to provide a dielectric insulator, removing any excess surface deposition from the surface, putting a metal fill into the holes to form through-silicon-vias (TSV), creating back-end-of-line wiring and pads on the top surface for interconnection, thinning down the wafer to expose the insulator in from the TSVs to adapt the TSVs to be contacted from a backside of the wafer, depositing an insulating layer which contacts the TSV dielectric, thinning down the backside of the wafer, opening through the dielectric to expose the conductor of the TSV to provide a dielectric insulation about exposed backside silicon, and depositing ball limiting metallurgy pads and solder bumps on the backside of the wafer to form an integrated circuit.

Abstract: In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface.

Abstract: A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer. After stripping the photoresist layer, there is no need to perform a wet etching process on the Cu UBM layer, and thereby the UBM structure has a non-undercut profile.

Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved by forming different height first and second conductive layer above a substrate. A first patterned photoresist layer is formed over the substrate. A first conductive layer is formed in the first patterned photoresist layer. The first patterned photoresist layer is removed. A second patterned photoresist layer is formed over the substrate. A second conductive layer is formed in the second patterned photoresist layer. The height of the second conductive layer, for example 25 micrometers, is greater than the height of the first conductive layer which is 5 micrometers. The first and second conductive layers are interposed between each other close together to minimize pitch and increase I/O count while maintaining sufficient spacing to avoid electrical shorting after bump formation. An interconnect structure is formed over the first and second conductive layers.

Abstract: The present invention provides a solder ball printing apparatus in which solder balls are uniformly dispersed on a mask surface and are loaded into an opening area of the mask. A solder ball shaking and discharging unit includes a solder ball reception unit which receives solder balls from a solder ball reservoir unit, a wire member in a convex shape which is attached to surround a solder ball shaking and discharging port of the solder ball shaking and discharging unit and in which a plurality of wire members are arranged at predetermined intervals, and solder ball rotating and collecting mechanisms which sweep and collect the solder balls at the wire member in a convex shape.

Abstract: A method for manufacturing a semiconductor device includes the steps of providing an element forming layer on a first surface of a semiconductor substrate, and providing an external connection terminal on a second surface of the semiconductor substrate opposite to the first surface so that the external connection terminal is electrically connected to the element forming layer through a via hole. The via hole is formed through the steps of forming a buried conductor layer on the first surface so as to electrically insulate the buried conductor layer from the semiconductor substrate, forming a communication hole on the second surface so as to communicate it with the buried conductor layer, and electrically connecting the buried conductor layer and the communication hole.

Abstract: An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions.

Abstract: A structure and method of forming pillar bumps with controllable shape and size are provided, which use polishing planarization technology to eliminate shape difference among pillar bumps on a wafer and die, thus yield the pillar bumps with design shape and size.

Abstract: A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.

Abstract: A semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump.

Abstract: A semiconductor device is disclosed wherein a tin diffusion inhibiting layer is provided above the land of a wiring line, and a solder ball is provided above the tin diffusion inhibiting layer. Thus, even when this semiconductor device is, for example, a power supply IC which deals with a high current, the presence of the tin diffusion inhibiting layer makes it possible to more inhibit the diffusion of tin in the solder ball into the wiring line.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: An under-bump metallization (UBM) structure for a semiconductor device is provided. A passivation layer is formed over a contact pad such that at least a portion of the contact pad is exposed. A protective layer, such as a polyimide layer, may be formed over the passivation layer. The UBM structure, such as a conductive pillar, is formed over the underlying contact pad such that the underlying contact pad extends laterally past the UBM structure by a distance large enough to prevent or reduce cracking of the passivation layer and or protective layer.

Abstract: A method for electrically connecting an integrated circuit to a via in a substrate is disclosed. The method can include deforming a ball over the via to form a bump and attaching a bond wire to the bump. The method also can include attaching the bond wire to the integrated circuit, such as by forming an end of the bond wire into a second ball and deforming the second ball over the integrated circuit. Alternatively, the method can include forming an end of the bond wire into a ball and deforming the ball over the via. Embodiments of a disclosed integrated circuit and substrate assembly can include, for example, a bump aligned with at least a portion of a via in a substrate and a bond wire attached to the integrated circuit and the bump. Other embodiments can include a via with a top metal cap and an upper plating.

Abstract: A copper pillar may be provided on a chip and a first tin-containing layer may be provided over the copper pillar. A second tin-containing layer may be provided on a substrate. The first tin-containing layer may be joined with the second tin-containing layer during a packaging process.

Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved by forming different height first and second conductive layer above a substrate. A first patterned photoresist layer is formed over the substrate. A first conductive layer is formed in the first patterned photoresist layer. The first patterned photoresist layer is removed. A second patterned photoresist layer is formed over the substrate. A second conductive layer is formed in the second patterned photoresist layer. The height of the second conductive layer, for example 25 micrometers, is greater than the height of the first conductive layer which is 5 micrometers. The first and second conductive layers are interposed between each other close together to minimize pitch and increase I/O count while maintaining sufficient spacing to avoid electrical shorting after bump formation. An interconnect structure is formed over the first and second conductive layers.

Abstract: A semiconductor device has a first conductive layer formed over a top surface of a substrate. A first insulating layer is formed over the substrate. A first dielectric layer is formed over the first insulating layer. A second conductive layer is formed over the first conductive layer and first dielectric layer. A second dielectric layer is formed over the second conductive layer. A polymer material is deposited over the second dielectric layer and second conductive layer. A third conductive layer is formed over the polymer material and second conductive layer. The third conductive layer is electrically connected to the second conductive layer. A first solder bump is formed over the third conductive layer. A conductive via is formed through a back surface of the substrate. The conductive via is electrically connected to the first conductive layer. The polymer material has a low coefficient of thermal expansion.

Abstract: A method for bonding a semiconductor device onto a substrate is provided which comprises the steps of picking up a solder ball with a pick head, placing the solder ball onto the substrate and melting the solder ball on the substrate and placing the semiconductor device on the molten solder ball. The molten solder ball is then allowed to cool to form a solder joint which bonds the semiconductor device to the substrate.

Abstract: A manufacturing method of a bump structure having a reinforcement member is disclosed. First, a substrate including pads and a passivation layer is provided. The passivation layer has first openings, and each first opening exposes a portion of the corresponding pad respectively. Next, an under ball metal (UBM) material layer is formed on the substrate to cover the passivation layer and the pads exposed by the passivation layer. Bumps are formed on the UBM material layer and the lower surface of each bump is smaller than that of the opening. Each reinforcement member formed on the UBM material layer around each bump contacts with each bump, and the material of the reinforcement member is a polymer. The UBM material layer is patterned to form UBM layers and the lower surface of each UBM layer is larger than that of each corresponding opening. Hence, the bump has a planar upper surface.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: In accordance with the present invention, during formation of the interconnection board, the interconnection board remains securely fixed to a high rigidity plate being higher in rigidity than the interconnection board for suppressing the interconnection board from being bent.

Abstract: A method for manufacturing a semiconductor device includes: a) preparing a structure including a semiconductor substrate, an electrode provided on a first surface of the semiconductor substrate, and an insulation film provided on the first surface and having an opening positioned on a first part of the electrode; b) forming a first metal layer from an upper surface of the first part of the electrode to an upper surface of the insulation film; c) forming a resin layer on a first part of the first metal layer, which is positioned on the first part of the electrode, and on the insulation film after the step b); d) removing at least a second part of the resin layer, which is positioned on the first part of the first metal layer, in a manner to leave a first part of the resin layer so as to form a resin protrusion; and e) forming a second metal layer, which is electrically connected with the electrode, from an upper surface of the first metal layer to an upper surface of the resin protrusion.

Abstract: Methods and UBM structures having bilayer or trilayer UBM layers that include a thin TiW adhesion layer and a thick Ni-based barrier layer thereover both deposited under sputtering operating conditions that provide the resultant bilayer or trilayer UBM layers with minimal composite stresses. The Ni-based barrier layer may be pure Ni or a Ni alloy. These UBM layers may be patterned to fabricate bilayer or trilayer UBM capture pads, followed by joining a lead-free solder thereto for providing lead-free solder joints that maintain reliability after multiple reflows. Optionally, the top layer of the trilayer UBM structures may include soluble or insoluble metals for doping the lead-free solder connections.

Abstract: A semiconductor chip according to the present invention includes a semiconductor substrate, a bump of a metal projecting from a surface of the semiconductor substrate, and an alloy film covering the entire surface of the bump, the alloy film being composed of an alloy of the metal of the bump and a second metal.

Abstract: A semiconductor device structure has a semiconductor die that has a bond pad with a passivation layer surrounding a portion of the bond pad. A nickel layer, which is deposited, is on the inner portion. A space is between a sidewall of the nickel layer and the passivation layer and extends to the bond pad. A palladium layer is over the nickel layer and fills the space. The space is initially quite small but is widened by an isotropic etch so that when the palladium layer is deposited, the space is sufficiently large so that the deposition of palladium is able to fill the space. Filling the space results in a structure in which the palladium contacts the nickel layer, the passivation layer and the bond pad.

Abstract: A method for producing an electrically conducting metal contact on a semiconductor component having a coating on the surface of a semiconductor substrate. In order to keep transfer resistances low while maintaining good mechanical strength, the invention proposes applying a particle-containing fluid onto the coating, where the particles contain at least metal particles and glass frits, curing the fluid while simultaneously forming metal areas in the substrate through heat treatment, removing the cured fluid and the areas of the coating covered by the fluid, and depositing, for the purposes of forming the contact without using intermediate layers, electrically conducting material from a solution onto areas of the semiconductor component in which the coating is removed while at the same time conductively connecting the metal areas present in said areas on the substrate.

Abstract: A method for fabricating semiconductor components includes the steps of: providing a semiconductor substrate having a circuit side, a back side and conductive vias; removing portions of the substrate from the back side to expose terminal portions of the conductive vias; depositing a polymer layer on the back side encapsulating the terminal portions; and then planarizing the polymer layer and ends of the terminal portions to form self aligned conductors embedded in the polymer layer. Additional back side elements, such as terminal contacts and back side redistribution conductors, can also be formed in electrical contact with the conductive vias. A semiconductor component includes the semiconductor substrate, the conductive vias, and the back side conductors embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another.

Abstract: The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.

Abstract: A semiconductor device includes: a semiconductor chip having a semiconductor substrate; a pad electrode formed on the semiconductor substrate; a base metal layer formed on said pad electrode; and a bump electrode formed on the base metal layer, in which an exposed surface including a side surface of the base metal layer is covered with the solder bump electrode.

Abstract: A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

Abstract: A method of fabricating a bumped chip package includes forming a first seed layer on a dielectric layer, the dielectric layer comprising a dielectric layer opening exposing a substrate terminal of a substrate, the first seed layer being formed within the dielectric layer opening and on the substrate terminal. A circuit pattern is plated on the first seed layer, wherein an exposed portion of the first seed layer is exposed from the circuit pattern. The exposed portion of the first seed layer is removed by laser-ablation. By using a laser-ablation process, a chemical etching process is avoided thus eliminating the need to treat or dispose of chemical etching hazardous waste. Further, circuit pattern width erosion and undercut of the circuit pattern associated with a chemical etching process are avoided.

Abstract: A T-shaped post for semiconductor devices is provided. The T-shaped post has an under-bump metallization (UBM) section and a pillar section extending from the UBM section. The UBM section and the pillar section may be formed of a same material or different materials. In an embodiment, a substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like, having T-shaped posts is attached to a contact of another substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like. The T-shaped posts may have a solder material pre-formed on the pillar section such that the pillar section is exposed or such that the pillar section is covered by the solder material. In another embodiment, the T-shaped posts may be formed on one substrate and the solder material formed on the other substrate.

Abstract: A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.

Abstract: There is provided a package substrate capable of controlling the degree of warpage thereof by improving the composition and formation of a post terminal and a method of fabricating the same. The package substrate includes a substrate having at least one conductive pad; an insulating layer provided on the substrate and having an opening to expose the conductive pad; a separation barrier layer provided on the conductive pad inside the opening and formed to be higher than the upper surface of the insulating layer along the side walls thereof; a post terminal provided on the separation barrier layer; and a solder bump provided on the post terminal.

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.

Abstract: A semiconductor device includes at least two conductive pads, one of the conductive pads being formed above another of the at least two conductive pads, and a redistribution layer extending from at least one of the conductive pads. The semiconductor device also includes a bump structure formed over the conductive pads and electrically coupled to the conductive pads.

Abstract: A metallic interconnect structure (200) for connecting a gold bump (205) and a contact pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 ?m), which covers the copper pad. The nickel layer insures that the gold/tin intermetallics and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.

Abstract: A method of manufacturing an interconnect structure for a semiconductor device having a device substrate is provided. The semiconductor device includes an electrically-conductive pad formed overlying the device substrate and an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity. The electrically-conductive platform has a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion. The semiconductor device also includes a cushioning material disposed in the cavity.

Abstract: A method of manufacturing a printed circuit board having solder balls. The method may include: stacking a second carrier, in which at least one hole is formed, over one side of a first carrier; forming at least one solder bump by filling the hole with a conductive material; forming a circuit pattern layer, which is electrically connected with the solder bump, on the second carrier; and exposing the solder bump by removing the first carrier and the second carrier. Using this method, uniform hemispherical solder balls with fine pitch can be formed as a part of the manufacturing process, without having to attach the solder balls separately. Carriers may be used to serve as supports during the manufacturing process, whereby deformations can be prevented in the board.

Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.

Abstract: The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, A thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.

Abstract: In order to realize a semiconductor device which is easily mounted on a circuit board and which has high mounting reliability, a semiconductor device 1 of the present invention includes: a semiconductor substrate 2; and an Au bump 3 provided on an electrode 21. The Au bump 3 is provided with a projection 3a. Also, on a surface of the Au bump 3, a solder layer 32 is formed via a Ni layer 31. The projection 3a makes it possible to easily mount the semiconductor device 1 by applying a small weight. Further, even if the amount of solder 62 supplied on an electrode 61 on a circuit board 6 is reduced, it is possible to bond the semiconductor device with a sufficient amount of solder during mounting. Furthermore, because a Ni layer 31 prevents dissolution of the bump, it is possible to ensure high mounting reliability.

Abstract: A copper pillar may be provided on a chip and a first tin-containing layer may be provided over the copper pillar. A second tin-containing layer may be provided on a substrate. The first tin-containing layer may be joined with the second tin-containing layer during a packaging process.

Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.

Abstract: Recessed features on a Damascene substrate are filled with metal using plasma PVD. Recessed features having widths of less than about 300 nm, e.g., between about 30-300 nm can be filled with metals (e.g., copper and aluminum), without forming voids. In one approach, the deposition is performed by exposing the substrate to a high-density plasma characterized by high fractional ionization of metal. Under these conditions, the metal is deposited within the recess, without forming large overhang at the opening of the recess. In some embodiments, the metal is deposited within the recess, while diffusion barrier material is simultaneously etched from the field region. In a second approach, recessed features are filled by performing a plurality of profiling cycles, wherein each cycle includes a net etching and a net depositing operation. Etching and depositing parameters are adjusted such that the recessed features are filled without forming overhangs and voids.

Abstract: A manufacturing method of a semiconductor device includes: forming a columnar electrode on a semiconductor wafer; flip-chip bonding a second semiconductor chip onto the semiconductor wafer; forming a molding portion on the semiconductor wafer, the molding portion covering and molding the columnar electrode and the second semiconductor chip; grinding or polishing the molding portion and the second semiconductor chip so that an upper face of the columnar electrode and an upper face of the semiconductor chip are exposed; and cutting the molding portion and the semiconductor wafer so that a first semiconductor chip, where the second semiconductor chip is flip-chip bonded and the columnar electrode is formed, is formed.