Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.

Abstract: A semiconductor device includes a porous interlayer insulation film including therein a stacking of SiO2 particles having a diameter in the range between about 5 nm and about 50 nm and stacked so as to form a void between adjacent particles, wherein the interlayer insulation film has a porosity in the range between about 13% and about 42%.

Abstract: Air-gap technology is introduced in the damascene scheme, reducing the capacitance between interconnect metal lines on an integrated circuit substrate, and ultimately enhancing the speed of the device. Reduction of extraneous signal energy (cross-talk) from traversing from one metal line to another is also realized. The method for implementing an air-gap filled dielectric between the interconnect metal lines involves depositing a first dielectric layer on the substrate at a predetermined height. Next the first dielectric is patterned and etched to form lines. A second dielectric layer is then deposited using air-gap technology, such that the second dielectric contains air-gaps between the first dielectric lines. These air-gaps are situated below the predetermined height of the first dielectric. The substrate is then polished so that the top surface of the first dielectric is exposed. The first dielectric lines are then etched and removed.

Abstract: A semiconductor producing method includes the steps of: forming an SOG pre-film on a semimanufactured semiconductor device by means of spin-on-glass (SOG) process; and forming a modified SOG film by doping the SOG pre-film with at least one impurity ion selected from: inert gas ions; simple ions of Groups IIIb, IVb, Vb, VIb, VIIb, IVa and Va elements; and ions of compounds containing any one of Groups IIIb, IVb, Vb, VIb, VIIb, IVa and Va elements.

Abstract: A semiconductor device manufacturing method capable of manufacturing a semiconductor device having a small wiring capacitance even for a small wiring pitch is provided. Steps of forming an interlayer insulating film containing a hydrogen silsesquioxance (HSQ) film on a wiring layer, implanting hydrogen ions into the HSQ film, and annealing the semiconductor device are included.

Abstract: In one aspect, the invention provides a method of exposing a material from which photoresist cannot be substantially selectively removed utilizing photoresist. In still another aspect of the invention, laser ablation of photoresist is utilized. In one implementation, the invention comprises forming a first material over a substrate. Photoresist is deposited over the first material and an opening is formed within the photoresist over the first material. Etching is then conducted into the first material through the photoresist opening. After the etching, the photoresist is laser ablated from over the first material.

Abstract: A method for fabricating a metal interconnect involves forming a first dielectric layer on the substrate having metal lines formed thereon, wherein the top surface of the first dielectric layer is lower than that of the metal line. As a result, the top surface and a part of the sidewall of the metal line are exposed. A spacer is then formed on the exposed sidewall of the metal line. A second dielectric layer is formed on the substrate, wherein the spacer has different etching selectivity from the second dielectric layer. With the spacer serving as an etching stop layer, a via opening is formed in the second dielectric layer, while the via opening is filled with a metal plug to form a via plug.

Abstract: Using a CVD method, there is deposited, on a semiconductor substrate, a first silicon oxide layer on which a porous layer is then deposited. The porous layer is then etched to form a wiring groove. Using a CVD method, a second silicon oxide layer is deposited throughout the surface of the porous layer, and the first and second silicon oxide layers are etched to form a through-hole therein. Then, a conductive layer is deposited throughout the surface of the semiconductor substrate. Then, the conductive layer is subjected to CMP to form a wiring layer composed of the conductive layer.

Abstract: The present invention provides a method of depositing a silicon oxide layer on a semiconductor wafer. The semiconductor wafer comprises a plurality of transistors positioned on its surface. The method comprises performing a cleaning process on the semiconductor wafer by using an alkaline solution to make a more uniform deposition rate of the silicon oxide layer on the transistors and other areas over the surface of the semiconductor wafer, then performing a deposition process by employing ozone as a reactive gas to form a silicon oxide layer of even thickness and without voids.

Abstract: A method for fabricating a metal interconnect structure. A first insulating layer and a second insulating layer with a low dielectric constant are formed on a substrate in sequence. An opening is formed in the second insulating layer. A compact and high density third insulating layer is formed on the second insulating layer and in the opening to protect the second insulating layer from being damaged in a subsequent process for removing a photo-resist layer. A contact window is then formed in the third insulating layer at a bottom of the opening and the first insulating layer, so that a dual damascene opening is formed. The dual damascene opening is filled with metal with low resistivity to form the metal interconnect.

Abstract: A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A low-k material is then deposited to fill the gaps between metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A protective layer is deposited on top of the metal lines and the low-k material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photo-resist, and to clean the vias.

Abstract: A semiconductor device and process for making the same are disclosed which use organic-containing materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with an inorganic substrate encapsulation layer 32 deposited conformally over this structure. A layer of an organic-containing dielectric material 22 (pure parylene, for example) is then deposited to substantially fill the gaps between and also cover the conductors. An inorganic cap layer 24 of a material such as SiO2 is deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the organic-containing dielectric (this step may also be used to strip the photoresist).

Abstract: The present invention discloses a method of forming self-aligned unlanded via holes. First, a substrate having a patterned conductive layer on its surface is provided, and then a first dielectric layer is deposited on the substrate by using high density plasma chemical vapor deposition (HDP CVD). Next, a silicon nitride layer and a second dielectric layer are sequentially deposited on the first dielectric layer. Thereafter, the second dielectric layer, the silicon nitride layer and the first dielectric layer are etched back to remove a portion of the silicon nitride layer overlying the patterned conductive layer. Finally, a third dielectric layer is deposited, and then via holes are defined in the third dielectric layer.

Abstract: A method of forming a planar interlayer dielectric layer over underlying structures is disclosed. First, a liner oxide layer is formed over the underlying structures. Then, a BPSG layer is formed over the liner oxide layer. The BPSG layer is polished and a cap oxide layer is formed over the BPSG layer. Finally, a nitride layer is formed over the cap oxide layer.

Abstract: A method of dual damascene includes forming a first conducting layer on a substrate, which already contains formed devices, and then forming a first dielectric layer and a hard material layer on the first conducting layer. The hard material layer contains a first opening, which is located right over the first conducting layer. A second dielectric layer is formed on the hard material layer, wherein the second dielectric layer is enforced by a ion implantation process or a plasma process. A hard mask layer containing a second opening is then formed on the second dielectric layer, wherein the second opening gradually widens upward, and wherein the second opening is located over the first opening. The hard mask layer is then used to pattern the second dielectric layer to expose the hard material layer. A part of the first dielectric layer is removed to expose the first conducting layer and form a third opening after a protection layer is formed on the side wall of the second dielectric layer.

Abstract: A method for making a semiconductor device includes the steps of forming a first conductive layer adjacent a substrate, forming an etch stop layer on the conductive layer, and forming a dielectric layer on the etch stop layer. The dielectric layer includes a material having a low dielectric constant, and a via is formed through the dielectric layer to expose the etch stop layer at the bottom, with porous sidewalls being produced. The exposed etch stop layer is etched using an etchant that cooperates with etched material from the etch stop layer to form a polymeric layer to coat the porous sidewalls of the via. Since the etchant cooperates with the etched material from the etch stop layer to form the polymeric layer coating the porous sidewalls of the via, a separate coating layer deposition step is not required after the via is etched and cleaned.

Abstract: A method and apparatus for depositing nano-porous low dielectric constant films by reaction of a silicon hydride containing compound or mixture optionally having thermally labile organic groups with a peroxide compound on the surface of a substrate. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a foam structure. The nano-porous silicon oxide based films are useful for filling gaps between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures. Preferred nano-porous silicon oxide based films are produced by reaction of 1,3,5-trisilanacyclohexane, bis(formyloxysilano)methane, or bis(glyoxylylsilano)methane and hydrogen peroxide followed by a cure/anneal that includes a gradual increase in temperature.

Abstract: A method of forming a multilayered pattern in an electronic part wherein a pattern of multilayer wiring is formed via insulating layers in which a pattern for a succeeding layer is formed by adjusting to a position and a configuration of the pattern which was already formed by recognizing a position and configuration of the pattern.

Abstract: A USG layer 26 is formed to cover an aluminum wiring 24 deposited a field oxide film 22. An organic SOG layer 28 whose thick layer can be easily formed is formed in a groove on the surface of the USG layer 26. Thus, the unevenness of the surface of the USG layer 26 can be relaxed in a degree. Further, an USG layer 30 is formed thereon is formed through the vapor phase growth technique using the high density plasma which can realize excellent embedding. Accordingly, the inter-metal dielectric film 32 having a flat upper surface can be formed. Further, the SOG step is carried out only once in the step of forming the organic SOG layer 28, thereby reducing the production cost. Further, since the organic SOG layer 28 can be encircled by the USG layers 26 and 39 having good film quality, even if the material of the organic SOG layer 28 is not so good, the inter-metal dielectric film 32 with an excellent dielectric property can be formed.

Abstract: An SiOF layer is formed by using as raw material an organic Si compound having Si—F bonds. Since an organic Si compound is used as raw material, an intermediate product being formed during the formation of an SiOF layer is liable to polymerize and has fluidity. Moreover, since the organic Si compound has Si—F bonds, low in bond energy, and is thus capable of easily getting only Si—F bonds separated, the SiOF layer is prevented from getting contaminated by reaction by-products and fluorine can be introduced into the SiOF layer in stable fashion. Therefore, an insulator layer, low in dielectric constant, low in hygroscopicity and excellent in step coverage, can be formed by using a low powered apparatus.

Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a norbornene-type polymer is used as a sacrificial material to occupy a closed interior volume in a semiconductor structure. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, preferably by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the norbornene-type polymer. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween.

Abstract: A first insulating film is formed on a semiconductor substrate. On the first insulating film, a first photoresist is then formed. A pattern for contact hole is formed in the first photoresist. Thereafter, the first insulating film is etched by using the first photoresist as a mask, and thereby a contact hole is formed. The first photoresist is then removed, and an organic insulating film is formed on a whole surface. In addition, a second insulating film is formed on the organic insulating film. Subsequently, a second photoresist is formed on the second insulating film. A pattern for wiring trench is formed in the second photoresist. Thereafter, the second insulating film is etched by using the second photoresist as a mask. Subsequently, the organic insulating film is etched by using the second insulating film as a mask, and thereby a wiring trench is formed.

Abstract: A method for forming a planarized thin film dielectric film on a surface of a common circuit base upon which one or more integrated circuits are to be attached. The common circuit base includes raised features formed over its surface such that the raised features define a trench area between them. The method includes the steps of forming a first layer of the dielectric film over the common circuit base and over the raised features and the trench, then patterning the newly formed layer to remove portions of the layer formed over the raised features and expose the raised features. After the layer is patterned, formation of the dielectric film is completed by forming a second layer of the dielectric film over the patterned first layer.

Abstract: The present invention relates to insulating layers and a forming method thereof, more particularly, to planarized insulating layers among wires on the same insulating layer or different layers and a forming method thereof which minimize parasitic capacitance generated from the wires, prevent via poison and reduce step difference between the adjacent layers by forming a dielectric layer having a low dielectric constant between the wires patterned in the same layer and by forming an insulating interlayer having excellent heat-dissipation efficiency and interface-adhesiveness between the wires in the different layer.

Abstract: In a multilayer wiring structure, a plurality of wiring layers (9, 11, 13) are formed on an inorganic lowermost insulating film (2) formed on a silicon substrate (1), and organic interlayer insulating films (14, 15, 16, 17, 18) are interposed between the respective adjacent wiring layers. Via metal (8, 10, 12) are formed in the inorganic lowermost insulating film (2) and the organic interlayer insulating films (15, 17), and openings having the shape corresponding to an electrode pad are formed in the organic interlayer insulating films (14, 15, 16, 17, 18), and these openings are filled with metal material to form metal film patterns (3, 4, 6, 5, 7), whereby the electrode pad is constructed as the laminate body of the metal film patterns (3, 4, 6, 5, 7).

Abstract: An interlayer insulating film (104) that is formed on a substrate (101) so as to cover TFTs (102, 103) is planarized by mechanical polishing that is typified by CMP. Pixel electrodes (106, 107) are formed on the interlayer insulating film (104) and an insulating layer (108) is formed so as to cover the pixel electrodes. The insulating layer (108) is planarized by second mechanical polishing so that the surfaces of the pixel electrodes become flush with those of resulting buried insulating layers (112, 113). Since the pixel electrode surfaces have no steps, such problems as alignment failures of a liquid crystal material and a contrast reduction due to diffused reflection of light can be prevented.

Abstract: A method for fabricating a hybrid low dielectric constant intermetal dielectric layer with improved reliability for multilevel electrical interconnections on integrated circuits is achieved. After forming metal lines for interconnecting the semiconductor devices, a protective insulating layer composed of a low-k fluorine-doped oxide (k=3.5) is deposited. A porous low-k spin-on dielectric layer (k less than 3) is formed in the gaps between the metal lines to further minimize the intralevel capacitance. A more dense low-k dielectric layer, such as FSG, is deposited on the porous layer to provide improved structural mechanical strength and over the metal lines to provide reduced intralevel capacitance. Via holes are etched in the FSG and are filled with metal plugs and the method can be repeated for additional metal levels to complete the multilevel interconnections on the integrated circuit.

Abstract: The invention includes a method of forming an insulating material between components of an integrated circuit. A pair of spaced electrical components are provided over a substrate. Polysilicon is chemical vapor deposited over, between, and against the pair of electrical components. Cavities are formed within the polysilicon to enhance porosity of the polysilicon. After the cavities are formed, at least some of the polysilicon is transformed into porous silicon dioxide.

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias etches a via opening in a first insulating layer. A photoresist layer that the defines the conductive wiring is deposited and patterned on the first insulating layer after the via opening has been created. The via opening and the conductive wire opening in the resist layer are then filled with the conductive material, such as copper. The resist layer may then be removed and a second insulating layer provided over the first insulating layer.

Abstract: A method of fabricating an electrically conductive via in a substrate which includes providing an electrically insulating substrate having first and second opposing surfaces and forming a first layer of electrically conductive material on the first of the opposing surfaces and forming a second layer of electrically conductive material on the second of the opposing surface. In accordance with one embodiment, the second layer has a thickness greater than the electrically insulating layer and no greater than the sum of the thicknesses of the electrically insulating layer and the first layer. In accordance with a second embodiment, the second layer has a thickness greater than the electrically insulating layer and no greater than the sum of the thicknesses of the electrically insulating layer and the first layer. A hole is formed in the first layer having sidewalls. A stud is formed in the second layer aligned with the hole in the first layer.

Abstract: A process for the formation and planarization of polymeric dielectric films on semiconductor substrates and for achieving high chemical mechanical polish removal rates when planarizing these films. A cured, globally planarized, polymeric dielectric thin film is produced on a semiconductor substrate by (a) depositing a polymeric, dielectric film composition onto a surface of a semiconductor substrate; (b) partially curing the deposited film; (c) performing a chemical mechanical polishing step to said partially cured dielectric film, until said dielectric film is substantially planarized; and (d) subjecting the polished film to an additional curing step. Preferred dielectric films are polyarylene ether and/or fluorinated polyarylene ether polymers which are deposited by a spin coating process onto a semiconductor substrate. A thermal treatment partially cures the polymer. A chemical mechanical polishing step achieves global planarization. Another thermal treatment accomplishes a final cure of the polymer.

Abstract: A method of making a semiconductor device has a multilayer interconnection structure including a lower organic interlayer insulation film, an etching stopper film on the lower interlayer insulation film and an upper organic interlayer insulation film covering the etching stopper film, wherein the upper organic interlayer insulation film is covered by first and second etching stopper films of respective, different compositions.

Abstract: Cavities such as vias and contacts formed in semiconductor devices are filled in a multi-stage process to provide low resistance electrical connections. A liner is first deposited into the cavity at a relatively low power and deposition rate to enhance "wetting" of a subsequently deposited fill material. The fill material is deposited at a comparatively greater power and deposition rate to close the mouth of the cavity, after which the fill material is extruded at high pressure into the cavity to substantially fill the cavity. Relatively low processing temperatures and high pressures are utilized to allow for the use of lower dielectric constant dielectrics, which are thermally unstable at conventional processing temperatures.

Abstract: A method for planarizing the surface of a semiconductor wafer is disclosed. It involves the steps of: (a) applying a coating solution containing a polymeric material on a semiconductor wafer having a non-planar surface; (b) curing the polymeric material to cause the polymeric material to become a hardened polymeric material; (c) subjecting the hardened polymeric material to a N.sub.2 O gas plasma treatment, so that an outer portion of the hardened polymeric material can be polished by a conventional CMP slurry which is typically intended for polishing silicon oxide; and (d) polishing the N.sub.2 O gas plasma treated polymeric material using a conventional CMP slurry. This method allows conventional CMP slurries to be used for the chemical-mechanical polishing of the chemically more inert polymeric material, thus eliminating stocking and potential compatibility problem. It also advantageously allows the unaffected portion of the polymeric material to serve as a self-provided etch stop.

Abstract: An interlevel dielectric stack for use in semiconductor devices is provided. The interlevel stack includes a bottom adhesion layer, a middle layer composed of a fluorinated amorphous carbon film, and a top adhesion layer. The bottom and top adhesion layers are composed of a silicon carbide material containing hydrogen. The dielectric stack is subjected to rigorous adhesion and thermal testing. A single continuous process for depositing the dielectric stack in a high density plasma reactor is also provided.

Abstract: A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with a dielectric material having a low dielectric constant. In another embodiment, a conformal dielectric coating is deposited, having a low dielectric constant.

Abstract: A vertically integrated semiconductor component is provided with component levels disposed on different substrates. The substrates are joined by a connecting layer of benzocyclobutene and an electrical connection is provided between component levels by a vertical contact structure. A low-stress gluing is provided by the benzocyclobutene connecting layer.

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a composite dielectric layer with enhanced adhesion. There is first provided a substrate. There is then formed over and upon the substrate a first dielectric layer comprising a silicon, oxygen and nitrogen containing dielectric material in contact with a second dielectric layer comprising an organic polymer spin-on-polymer (SOP) dielectric material. The interface between the dielectric layers may be treated by ion implantation methods to provide the resulting silicon, oxygen and nitrogen containing dielectric layer composition to provide the composite dielectric layer with enhanced adhesion at the interface.

Abstract: A novel passivation structure and its method of fabrication. According to the present invention a first dielectric layer is formed upon a conductive layer formed over a substrate. The first dielectric layer and the conductive layer are then patterned into a first dielectric capped interconnect and a dielectric capped bond pad. Next, a second dielectric layer is formed over and between the dielectric capped interconnect and the dielectric capped bond pad. The top portion of the second dielectric layer is removed so as to expose the dielectric capped bond pad and the dielectric capped interconnect. A third dielectric layer is then formed over the exposed dielectric capped bond pad and the exposed dielectric capped interconnect and over the second dielectric.

Abstract: An integrated circuit and its method of formation are disclosed. The circuit utilizes a spin-on glass as an interlevel dielectric. Above and below the spin-on glass is located a phosphorous doped dielectric. The doped dielectric prevents sodium from becoming mobile under the influence of subsequently applied electric fields.

Abstract: A first insulating film with a dielectric constant lower than that of a silicon oxide film is formed on a semiconductor substrate. Next, a second insulating film, which has degrees of moisture absorption and deformation in an oxygen plasma process and exposure to a resist releasing solution equal to or less than those of a silicon oxide film, is formed on the first insulating film. Then, a third insulating film, which has degrees of moisture absorption and deformation in an oxygen plasma process and exposure to a resist releasing solution equal to or less than those of a silicon oxide film are formed on the second insulating film. Thereafter, the third insulating film is patterned to a prescribed pattern. An opening is formed in the first and second insulating films using the third insulating film as a mask.

Abstract: An array substrate typically used in a liquid crystal display device includes inter-layer insulating films thick enough to prevent step-off breakage of conductive layers at contact holes while promising a reliability. Thick inter-layer insulating films are made by stacking a film made of an inorganic material, such as silicon nitride or silicon oxide, having a low moisture permeability and thereby promising a reliability of the liquid crystal display device, and a film made of an organic material, such as acrylic resin, that can be readily stacked thick so that the inner wall of the contact hole is gently sloped with respect to the substrate surface to thereby prevent step-off breakage of a conductive layer as thin as 100 nm or less.

Abstract: In a semiconductor device which includes at least an interlayer insulating film containing a plurality of Si--H bonds, a Si--OH bond portion is removed from a surface of the interlayer insulating film.

Abstract: A method of manufacturing a semiconductor device copes with miniaturization owing to reduction in an overlapping margin. According to this manufacturing method, a conductive layer forming an upper interconnection layer is formed in an opening provided for connection to a lower interconnection layer, and then an organic polymer film filling a concavity at the conductive layer located in the opening is formed. After forming a resist pattern on the organic polymer film, organic polymer film and conductive layer are etched. The overlapping margin is reduced owing to the fact the organic polymer film fills the concavity at the conductive layer.

Abstract: This invention pertains generally to precursors and deposition methods suited to aerogel thin film fabrication. An aerogel precursor sol which contains an oligomerized metal alkoxide (such as TEOS), a high vapor pressure solvent (such as ethanol) and a low vapor pressure solvent (such as water and 1-butanol) is disclosed. By a method according to the present invention, such a precursor sol is applied as a thin film to a semiconductor wafer, and the high vapor pressure solvent is allowed to evaporate while evaporation of the low vapor pressure solvent is limited, preferably by controlling the atmosphere adjacent to the wafer. The reduced sol is then allowed to gel at a concentration determined by the ratio of metal.alkoxide to low vapor pressure solvent. One advantage of the present invention is that it provides a stable, spinnable sol for setting film thickness and providing good planarity and gap fill for patterned wafers.

Abstract: An interlayer insulating film of a semiconductor device is made of a material in which silicon atoms are main elements, and each of the silicon atoms has an oxygen bond and a carbon bond, and further at least some of the silicon atoms have a hydrogen bond. The interlayer insulating film is formed by chemical vapor deposition employing a mixed gas of hydrogen peroxide and a reactive gas having a gas molecular structure in which silicon atoms have a hydrogen bond and a carbon bond.

Abstract: A process for curing low-k spin-on dielectric layers based on alkyl silsesquioxane polymers by laser scanning is described wherein curing is achieved by both photothermal and photochemical mechanisms. The layers are deposited by spin deposition, dried and cured by raster scanning with a pulsed laser at energies between 0.1 and 1 Joules/cm.sup.2. Because the laser causes heating of the layer, a nitrogen jet is applied in the wake of the scanning laser beam to rapidly cool the layer and to inhibit oxidation and moisture absorption. The laser induced heating also assists in the discharge of moisture and by-products of the polymerization process. The laser operates at wavelengths between 200 and 400 nm. Insulative layers such as silicon oxide are sufficiently transparent at these so that oxide segments overlying the polymer layer do not inhibit the curing process. Implementation of the laser scanning feature is readily incorporated into an existing spin-on deposition and curing tool.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A method of making a semiconductor device includes forming a low permittivity dielectric layer over one or more conductive lines of a semiconductor device. The dielectric layer is made using a silicon-containing material having a relatively low permittivity including, for example, silicon oxyfluoride (SiO.sub.y F.sub.x) and hydrogen silsesquioxane (HSQ). An optional oxide layer may be formed over the dielectric layer. At least a portion of the dielectric layer and/or the optional oxide layer is subsequently removed to form a planar dielectric layer having a contaminated surface layer. The contaminated surface layer is due to exposure to water and is removed by, for example, exposing the surface to an acid, such as hydrofluoric acid.

Abstract: A method for forming a dual damascene structure using low-dielectric constant materials is disclosed. The method includes providing a substrate first. A first dielectric layer is formed on the substrate, and the first dielectric layer is then cured to form a stop layer. Then, a second dielectric layer is formed on the stop layer, and the second dielectric layer is cured to form an insulating layer. The insulating layer, the second dielectric layer, the stop layer, and the first dielectric layer are etched to form a via hole, and the insulating layer and the second dielectric layer is then etched to form a trench line.