Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.

Abstract: A method of fabricating metal interconnects and an inter-metal dielectric layer thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the second metal interconnect pattern. The inter-metal dielectric layer is then planarized and the second metal interconnect pattern is exposed.

Abstract: A method of manufacturing a semiconductor device includes forming on a lower insulating layer first to third electrically conducting layers sequentially, forming a mask pattern on the third conducting layer, dry-etching the first to third conducting layers with the mask pattern as a mask, thereby dividing the conducting layers, and forming an insulating layer between the adjacent second conducting layers by an HDP-CVD process so that a void is defined so as to be located lower than an interface between the first and second conducting layers and higher than an interface between the second and third conducting layers so as to have a sectional area larger than the second conducting layer. The forming of the insulating layer by the HDP-CVD process includes burying the insulating layer and sputtering to spread a frontage of a buried region buried by the burying process, both burying and sputtering being repeated alternately.

Abstract: A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for forming an integrated circuit insulator. The method includes forming an insulating layer using a first structural material upon a substrate, the first structural material having sufficient mechanical characteristics to support metal during chemical-mechanical polishing (CMP). The method also includes depositing a metallic layer upon the insulating layer, the metallic layer adapted to be used as a wiring channel. The method further includes processing the metallic layer to form the wiring channel, where processing includes CMP. In addition, the method includes removing and replacing at least a portion of the first structural material with a second structural material, the second structural material having insufficient mechanical characteristics to support metal during CMP. Other aspects and embodiments are provided herein.

Abstract: The present invention relates to a technology for depositing a thin metal film by using a plasma sputtering technique on a top surface of a target object, e.g., a semiconductor wafer or the like, and on a surface of a recess opened at the top surface. The film deposition method is characterized in that a film deposition process to deposit a metal film on a sidewall of the recess by generating metal ions by way of making a metal target sputter with a plasma generated from a discharge gas in the processing container and by applying to the mounting table a bias power to cause a metal film deposition based on a metal ion attraction and a sputter etching based on the plasma generated from the discharge gas simultaneously on the top surface of the target object.

Abstract: A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 ?m or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.

Abstract: An improved interconnect structure and method of making such a device. The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.

Abstract: Aimed at improving adhesiveness between upper and lower interconnects in semiconductor devices, a semiconductor device of the present invention includes a second dielectric multi-layered film formed on a substrate, and containing a lower interconnect; a first dielectric multi-layered film formed on the second dielectric multi-layered film, and having a recess; an MOx film formed on the inner wall of the recess, and containing a metal M and oxygen as major components; an M film formed on the MOx film, and containing the M as a major component; and an electric conductor formed on the M film so as to fill the recess, and containing Cu as a major component, wherein the surficial portion of the interconnect fallen straight under the bottom of the recess has an oxygen concentration of 1% or smaller.

Abstract: Disclosed are a substrate for electronic devices such as semiconductor devices and a method for processing the same, In the processing method, firstly a substrate for electronic devices is prepared and an insulating film (I) composed of a fluorocarbon (CF) is formed on the surface of the substrate. Then, fluorine (F) atoms exposed in the surface of the insulating film (I) are removed therefrom by bombarding the surface of the insulating film (I) with, for example, active species (KR+) produced in a krypton (Kr) gas plasma. In this connection, the substrate is kept out of contact with moisture at least from immediately after the insulating film forming step until completion of the fluorine removing step.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a multilayer structure; a semiconductor pillar; a third insulating film; and a fourth insulating film layer. The a multilayer structure is provided on the semiconductor substrate and including a plurality of constituent multilayer bodies stacked in a first direction perpendicular to a major surface of the semiconductor substrate. Each of the plurality of constituent multilayer bodies includes an electrode film provided parallel to the major surface, a first insulating film, a charge storage layer provided between the electrode film and the first insulating film, and a second insulating film provided between the charge storage layer and the electrode film. The semiconductor pillar penetrates through the multilayer structure in the first direction. The third insulating film is provided between the semiconductor pillar and the electrode film.

Abstract: A spacer is adjacent to a conductive line. Vias that do not completely land on the conductive line land on the spacer and do not punch through into a volume below the spacer.

Abstract: A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. An insulating layer is formed over the passivation layer. The insulating layer is removed over the first contact pad, but not from the second contact pad. A metal layer is formed over the first contact pad. The metal layer is coiled on the surface of the substrate to produce inductive properties. The formation of the metal layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the insulating layer. The insulating layer is removed from the second contact pad after forming the metal layer over the first contact pad. An external connection is formed on the second contact pad.

Abstract: Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous OSG film as a hardmask for use in semiconductor devices are provided herein. The novel interconnect structures are capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed and also because of the relatively uniform line heights made feasible by these unique and seemingly counterintuitive features.

Abstract: A metal interconnects structure, comprises a substrate (11), a dielectric layer (12) lying above the substrate, a stop layer (13) for metal etching lying above the dielectric layer, a metal layer (15?) lying above the stop layer, said metal layer being patterned according to a desired pattern.

Abstract: Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster write cycles and lower power requirements than some other materials. However, the present inventors have recognized, for example, that conventional techniques for working with the polymers produce polymer layers with thickness variations that compromise performance and manufacturing yield. Accordingly, the present inventors devised unique methods and structures for polymer-based ferroelectric memories. One exemplary method entails forming an insulative layer on a substrate, forming two or more first conductive structures, with at least two of the first conductive structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first conductive structures. In some embodiments, the gap-filling structure is a polymer, a spin-on-glass, or a flow-fill oxide.

Abstract: In a semiconductor device, a plurality of interconnections are formed in an interconnection formation insulating interlayer, and a plurality of reinforcing elements are substantially evenly formed in blank areas of the interconnection insulating interlayer in which no interconnection is formed. A wire-bonding electrode pad is provided above the interconnection formation insulating interlayer so that a pad area, on which the wire-bonding electrode pad is projected, is defined on the interconnection formation insulating interlayer. A part of the reinforcing elements included in the pad area features a larger size than that of the remaining reinforcing elements.

Abstract: A contact arrangement is manufactured by providing a substrate that includes first regions that are arranged along a row direction and a second region. An interlayer is provided that covers the first regions and the second region. A buried mask including a first trim opening above the first regions is provided. A top mask including first template openings is provided, where each first template opening is arranged above one of the first regions. A second template opening is provided above the second region. The fill material and the interlayer are etched to form contact trenches above the first regions and the second region. Substrate area efficient chains of evenly spaced contacts are provided.

Abstract: A method for fabricating an inductor structure or a dual damascene structure includes following steps. First, a dielectric layer is provided. Subsequently, a first etching process is performed on the dielectric layer so as to form a first opening in the dielectric layer. A polymer is also formed in the first opening during the first etching process. Next, a polymer-removing step is performed to remove the polymer. Thereafter, a second etching process is performed on the dielectric layer to form a second opening in the dielectric layer. Furthermore, the first opening and the second opening are filled with a conductive material so as to form an inductor structure or a dual damascene structure.

Abstract: Multi-functional electronic switching and current control device comprising a chalcogenide material. The devices include a load terminal, a reference terminal and a control terminal. Application of a control signal to the control terminal permits the device to function in one or more of the following modes reversibly: (1) a gain mode in which gain is induced in the current passing between the load and reference terminals; (2) a conductivity modulation mode in which the conductivity of the chalcogenide material between the load and reference terminals is modulated; (3) a current modulation mode in which the current or current density between the load and reference terminals is modulated; and/or (4) a threshold modulation mode in which the voltage required to switch the chalcogenide material between the load and reference terminals from a resistive state to a conductive state is modulated. The devices may be used as interconnection devices or signal providing devices in circuits and networks.

Abstract: An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

Abstract: The present invention describes a method including: providing a substrate; stacking interlevel dielectric layers over said substrate, and separating said interlevel dielectric layers with a dielectric separator layer.

Abstract: In a method for fabricating a metal interconnection of a semiconductor device, a lower interconnection and a lower insulation layer are formed over a semiconductor substrate. An etch stop layer is formed over the lower insulation layer. An upper insulation layer is formed over the etch stop layer. A first via hole is formed to expose the etch stop layer corresponding to the lower interconnection. A second via hole exposing the lower interconnection is formed by a primary etching process that selectively removes the etch stop layer exposed by the first via hole. A chemical cleaning process is performed on the second via hole, wherein polymer is formed over the surface of the lower interconnection during the chemical cleaning process. The polymer is removed from the second via hole by a secondary etching process using vaporized gas.

Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

Abstract: A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner in the upper region of the via and tungsten filler; selectively removing the second liner from the tungsten filler; forming a copper seed layer on top of the tungsten filler; depositing a copper filler on top of the copper seed layer; and performing chemical CMP to smooth out and remove the second liner and copper filler from the semiconductor's exposed surface.

Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).

Abstract: A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.

Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

Abstract: Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

Abstract: In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric material and/or functional layers of one or more metallization layers may be provided with appropriate internal stress levels so as to maintain substrate warpage at a non-critical level, thereby substantially reducing yield losses in the manufacturing process caused by non-reliable attachment of substrates to substrate holders in process and transport tools.

Abstract: Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating PSAB layers are formed not only at the surface of the metal layers, but also within the unexposed portions of the metal lines. Encapsulating PSAB layer, for example, can surround the metal line with the PSAB material, thereby protecting interfaces between the metal line and diffusion barriers. Encapsulating PSAB layers can be formed by treating the exposed surfaces of metal lines with GeH4. Capping PSAB layers can be formed by treating the exposed surfaces of metal lines with SiH4. Interconnects having both a silicon-containing capping PSAB layer and a germanium-containing encapsulating PSAB layer provide good performance in terms of adhesion, resistance shift, and electromigration characteristics.

Abstract: A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first conductive layer to expose the first insulating layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first conductive layer; forming a second insulating layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second insulating layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second insulating layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer.

Abstract: Processes for sealing porous low k dielectric film generally comprises exposing the porous surface of the porous low k dielectric film to ultraviolet (UV) radiation at intensities, times, wavelengths and in an atmosphere effective to seal the porous dielectric surface by means of carbonization, oxidation, and/or film densification. The surface of the surface of the porous low k material is sealed to a depth less than or equal to about 20 nanometers, wherein the surface is substantially free of pores after the UV exposure.

Abstract: A method of deprocessing a semiconductor structure is provided. The method involves removing one or more interlevel dielectric layers and one or more metal components from a frontside of the semiconductor structure. By removing the interlevel dielectric layer and the metal component, the exposed portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics by using an inspection tool. The inspection can aid in defect reduction strategies, among other things, when applied to new technology ramp, monitoring of baseline wafer starts, customer returns, etc.

Abstract: A method for manufacturing a semiconductor device having a damascene metal/insulator/metal (MIM)-type capacitor and metal lines including providing a semiconductor device; sequentially forming a first interlayer insulating film and a second interlayer insulating film over the semiconductor substrate; simultaneously forming a vias hole and a lower metal line in a line region and a lower electrode in a capacitor region, wherein the lower metal line and the lower electrode are electrically connected to the semiconductor device; sequentially forming a dielectric film, a third interlayer insulating film, a fourth interlayer insulating film and a fifth interlayer insulating film over the semiconductor substrate; and then simultaneously forming a plurality of upper electrodes, a plurality of second vias holes and a plurality of second upper metal lines in the capacitor region electrically connected to the plurality of upper electrodes, a plurality of third vias holes and a plurality of second upper metal lines in th

Abstract: A method for fabricating a semiconductor device having a metal wiring is provided. The method includes: forming an inter-metal dielectric (IMD) layer on the semiconductor substrate having a first metal wiring formed therein, the IMD layer including a first IMD layer and a second IMD layer; forming a via hole in the IMD layer to expose the first metal wiring; forming an ion barrier layer on sidewalls of the via hole; forming a diffusion barrier layer on the semiconductor substrate, on which the ion barrier layer has been formed; forming a metal layer on the semiconductor substrate in the via hole; and forming a second metal wiring on the semiconductor substrate, the second metal wiring contacting the metal layer in the via hole.

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: An interposer includes a substrate made of an inorganic material; a through wiring including conductors embedded in through holes; and an upper wiring and (or) a lower wiring. The through wiring, the upper wiring and the lower wiring are respectively formed on preliminary wiring patterns that are additionally simultaneously or sequentially formed on layers made of an insulating material applied to at least wiring forming parts of the substrate, and are formed with a metal mold itself used for forming the preliminary wiring patterns or layers made of a wiring material applied by a printing operation, a plating operation or a deposition on the preliminary wiring patterns formed on the layers of the insulating material by transferring a fine structure pattern of the metal mold.

Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.

Abstract: A method to form a barrier layer and contact plug using a touch up RIE. In a first embodiment, we form a first barrier layer over the dielectric layer and the substrate in the contact hole. The first barrier layer is comprised of Ta. A second barrier layer is formed over the first barrier layer. The second barrier layer is comprised of TaN or WN. We planarize a first conductive layer to form a first contact plug in the contact hole. We reactive ion etch (e.g., W touch up etch) the top surfaces using a Cl and B containing etch. Because of the composition of the barrier layers and RIE etch chemistry, the barrier layers are not significantly etched selectively to the dielectric layer. In a second embodiment, a barrier film is comprised of WN.

Abstract: Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.

Abstract: A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure.

Abstract: A wire structure, having: a first insulating layer having a lower layer trench formed in an outer surface thereof; a first diffusion preventing film formed on an inner surface of the lower layer trench; a lower layer wire filled in the lower layer trench over the first diffusion preventing film; an interlayer diffusion preventing film formed on the lower layer wire, the interlayer diffusion preventing film made of a high melt point metal or a high melt point metal compound; a second insulating layer formed over the first insulating layer and the interlayer diffusion preventing film, a second insulating layer having a via hole that penetrates through the second insulating layer and the interlayer diffusion preventing film so as to reach the lower layer wire; a conductive second diffusion preventing film formed on an inner surface of the via hall; a conductor filled in the via hole over the second diffusion preventing film, and an adhering film made of the material that forms the interlayer diffusion preventing

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a patterned metal conductor layer. To provide UV blocking, an overlying separation layer is formed over the substrate, and a UV blocking layer of silicon enriched oxide is formed over the separation layer. The UV blocking layer has a silicon atomic concentration sufficient for ultraviolet blocking. A gap-filling, hydrogen-blocking layer may be formed over the semiconductor substrate, and any the UV blocking layer, to prevent hydrogen from passing therethrough.

Abstract: A semiconductor device provided with: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a barrier layer provided between the first interconnection layer and the interlevel insulation film; and a second interconnection layer of gold provided as an uppermost interconnection layer on the interlevel insulation film. The barrier layer is formed in a region of the first interconnection layer including an interlevel connection opening region of the interlevel insulation, and the region is greater than the interlevel connection opening region. The second interconnection layer is electrically connected to the first interconnection layer via the barrier layer in the interlevel connection opening.

Abstract: A multilayer circuit substrate for multi-chip modules or hybrid circuits includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by shadow mask techniques. Substrates formed in this manner enable significant increases in interconnect density and significant reduction of over-all substrate thickness.

Abstract: The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 ?m2 to about 3.15 ?m2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 ?m to about 5 ?m.

Abstract: A semiconductor device and a method for manufacturing the same include forming a second copper-plated layer over a second IMD layer and inside a second aperture formed in the second IMD by an electroplating process that uses the exposed first copper-plated layer as a seed layer. With the method, the copper-plated layer may be more simply and rapidly formed and achieve superior gap filling characteristics.

Abstract: A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers.