Abstract: For filling an interconnect opening within an insulating layer on a semiconductor wafer, an adhesion skin layer is deposited conformally onto an underlying material comprised of one of a barrier material or a dielectric material at sidewalls and a bottom wall of the interconnect opening. The adhesion skin layer includes a metal alloy doping element. A conformal seed layer is deposited onto the adhesion skin layer using a conformal deposition process, such as an ECD (electrochemical deposition) or a CVD (chemical-vapor-deposition) process. The adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material at the sidewalls and the bottom wall of the interconnect opening. The interconnect opening is filled with a conductive material grown from the conformal seed layer. In this manner, the adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material to minimize electromigration failure of the interconnect.

Abstract: The present invention provides a method of manufacturing an interconnect structure. The method may include forming a nucleation layer, including a first metal, over a barrier layer and within an opening formed in a dielectric layer, forming an intermediate layer, including a second metal such as titanium nitride, over the nucleation layer and within the opening, and forming a plug portion layer, including the first metal, over the intermediate layer and within the opening. The first metal may be tungsten and the second metal may be a titanium nitride layer.

Abstract: A method of fabricating copper damascene. In this invention, only crystalline copper metal layer is formed inside the damascene trench and only amorphous copper metal layer is formed outside the damascene trench. During stacking the copper metal layer, copper metal stacks up to form crystalline copper metal with good lattice packing according to the position of the copper seed layer. Conversely, amorphous copper metal is formed in positions where no copper seed layer exists. Since the amorphous copper metal is softer than the crystalline copper metal, lower pressure and the ordinary slurry are used in chemical mechanical polishing to remove amorphous copper metal layer outside the damascene trench, in order to form a flat-surfaced copper damascene structure.

Abstract: Disclosed is a method for forming selective protection layers on copper interconnects in a damascene process. A copper layer is deposited overlying a dielectric layer and filling interconnect trenches which are previously formed in the dielectric layer. The excess copper layer is polished by a chemical mechanical polishing process with a slurry comprising an aluminum organic substance. The aluminum organic substance reacts with copper via annealing to selectively form aluminum-copper alloys on the copper interconnects. The aluminum-copper alloys are then oxidized to form aluminum oxide protection layers capping the copper interconnects.

Abstract: The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1−x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The low resistance, tunable contact is suitable for CMOS devices.

Abstract: A process is described for depositing a copper film on a substrate surface by chemical vapor deposition of a copper precursor. The process includes treating a diffusion barrier layer surface and/or a deposited film with an adhesion-promoting agent and annealing the copper film to the substrate. Suitable adhesion-promoting agents include, e.g., organic halides, such as methylene chloride, diatomic chlorine, diatomic bromine, diatomic iodine, HCl, HBr and Hl. Processes of the invention provide copper-based films, wherein a texture of the copper-based films is predominantly (111). Such films provide substrates having enhanced adhesion between the diffusion barrier layer underlying the (111) film and the copper overlying the (111) film.

Abstract: One form of the present invention is a method for mask-less selective deposition made up of the steps of contacting a first portion of a substrate with a chemical agent that binds to the substrate to affect the susceptibility of the portion of the substrate to deposition. Following the treatment with the chemical agent, a first layer of a first material is deposited on a second portion of the surface. The first and second portions of the substrate may in fact be the same portion. That is to say, that the chemical agent may enhance or inhibit the deposition of the material of a portion of the substrate.

Abstract: For filling an interconnect opening of an integrated circuit formed on a semiconductor substrate, an underlying material is formed at any exposed walls of the interconnect opening. A sacrificial layer of protective material is formed on the underlying material at the walls of the interconnect opening. The underlying material and the sacrificial layer of protective material are formed without a vacuum break. The protective material of the sacrificial layer is soluble in an acidic catalytic solution used for depositing a catalytic seed layer. The semiconductor substrate having the interconnect opening is placed within an acidic catalytic solution for depositing a catalytic seed layer. The sacrificial layer of protective material is dissolved away from the underlying material by the acidic catalytic solution such that the underlying material is exposed to the acidic catalytic solution.

Abstract: A method of manufacturing a semiconductor device, according to the present invention comprises a step for forming an insulating film over a semiconductor wafer and thereafter subjecting the same to photolithography and etching to thereby define a contact hole, a step for forming an adhesive layer over the insulating film with the contact hole defined therein, a step for placing the interior of a processing chamber under an atmosphere uncontaining oxygen and subjecting the adhesive layer to heat treatment, a step for setting the temperature of the semiconductor wafer to less than or equal to a temperature equivalent to energy of such an extent as to cut the bonding between atoms which form the adhesive layer and thereafter taking the semiconductor wafer out of the processing chamber, and a step for forming an embedding film to be embedded in the contact hole.

Abstract: A method has been provided for improving the adhesion of copper to a nitrided metal diffusion barrier material, such as TiN, in an integrated circuit substrate. The method provided a multilayered diffusion barrier structure, comprising a nitrided metal diffusion barrier layer and an oxy-nitrided metal layer. The formation of an oxy-nitrided metal layer, instead of an oxide layer, permits the optimization of both contact resistance and adhesion property. The oxy-nitrided metal layer is formed either by the partial incorporation of oxygen into the nitrided metal diffusion barrier or by deposition in an oxygen ambient.

Abstract: The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper suicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.

Abstract: A method for forming a contact window with low resistance. The method at least includes the following steps. First of all, a dielectric layer is formed over a substrate, in which the substrate having a contact region where the metal contact will be formed thereon. Then, a first barrier layer is deposited over the dielectric layer, and a patterned photoresist is formed to defined a contact hole. Next, the first barrier layer and the dielectric layer are etched to expose portion of the substrate by using the photoresist as a mask thereby a contact hole is formed in the dielectric layer, wherein the exposed substrate has a conductive region. Then, a second conformal barrier layer is deposited on the first barrier layer and in the contact hole, the second conformal barrier layer is etched to exposed the conductive region to form a spacer on sidewalls of in the contact hole. Finally, the contact region opening is filled with a metal layer to complete electrical connections.

Abstract: A damascene process for forming a via that leads to a conductive layer on a substrate. A low dielectric constant material layer is formed over the substrate. A low temperature hard mask layer is formed over the low dielectric constant material layer. The low temperature hard mask layer is patterned to form an opening above the conductive layer. Using the low temperature hard mask layer as a mask, the exposed low dielectric constant material layer is etched to form a via hole. An adhesion promoter liner is formed on the interior walls of the via hole. Metallic material is deposited into the via hole to form a via.

Abstract: The present invention is to provide an electrical connection material through which an electrical connection via conductive particles can be performed reliably regardless of a little unevenness of an object. The electrical connection material is an electrical connection material 100 for electrically connecting an electrical connection portion of a first object 4 and an electrical connection portion of a second object 2. The electrical connection material 100 comprises a first film-like adhesive layer 6 which is a film-like adhesive layer arranged on the first object 4 and is composed of a plurality of conductive particles 7, a first binder 8 containing the conductive particles 7, and a first filler F1 and a second film-like adhesive layer 9 which is arranged on the first film-like adhesive layer 6 and is composed of a second binder 9A whose viscosity is lower than that of the first binder 8 and a second filler F2.

Abstract: A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is taught with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment, preferably RTP, is used to form a metal silicide contact at the bottom of the contact hole upon semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, metallization layer is deposited with the recess.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is formed over the semiconductor substrate has an opening formed therein. A barrier layer of titanium, tantalum, tungsten, or a nitride of the aforegoing lines the opening, and a copper or copper alloy conductor core fills the channel opening over the barrier layer. After planarization of the conductor core and the barrier layer, an ammonia, nitrogen hydride, or hydrogen plasma treatment is performed below 300° C. and above 3000 watts source power to reduce the residual oxide on the conductor core material. A silicon nitride capping layer is deposited by high density plasma (HDP) deposition with the source power between 2250 and 2750 watts and the bias power between 1800 and 2200 watts to suppress the formation of hillocks.

Abstract: A metal interconnect structure and method of making the same provides a low k dielectric layer on a substrate that contains the first metal line. A plurality of vias are formed in the low k dielectric layer, along with a second metal line. A first set of the plurality of vias are connected between the first and second metal lines, and a second set of the plurality of vias are not connected between the first and second metal lines. The second set of vias form dummy vias that increase the mechanical strength of the via layer and increase the resistance to delamination and scratching during chemical mechanical polishing.

Abstract: The object of the invention is to solve failure in embedding conductive material by electroplating caused because organic insulating material is deformed by the compressive stress of a barrier metal layer such as tantalum nitride used for grooved interconnection, a groove-used for grooved interconnection is deformed and a seed layer is not fully formed in the groove and to enhance reliability upon interconnection. To achieve the object, a semiconductor device according to the invention is based upon a semiconductor device having a groove formed through a second insulating film over a substrate, a barrier metal layer formed at least on the inner wall of the groove and grooved interconnection embedded inside the groove via the barrier metal layer and is characterized in that a concave portion is continuously or intermittently formed along a groove through a second insulating film within a predetermined interval from grooved interconnection.

Abstract: Insulative spacers to be disposed on an active surface of a semiconductor device component and methods of fabricating and disposing the insulative spacers on semiconductor device components. Semiconductor device components including the insulative spacers are also disclosed, as well as assemblies wherein the insulative spacers are disposed between a semiconductor device component and a higher level substrate. One or more of the insulative spacers are disposed on the active surface of a semiconductor device prior to bonding the same to a higher level substrate. Upon assembly of the semiconductor device component face down upon a higher level substrate and joining conductive structures, such as solder structures, between the contact pads of the semiconductor device component and corresponding contact pads of the higher level substrate, the insulative spacers define a minimum, substantially uniform distance between the semiconductor device component and the higher level substrate.

Abstract: An electronic device is provided that compromises a dielectric layer (12) disposed outwardly from a substrate (10). The dielectric layer (12) has at least one contact opening (14) formed through the dielectric layer (12). The device has an adhesion layer (16) disposed outwardly from the exposed surfaces of the dielectric layer (12) and the substrate (10). A first barrier layer (18) is formed outwardly from the adhesion layer (16). A second barrier layer (20) is formed outwardly from the first barrier layer (18). A conductive plug (24) fills the contact opening (14) and is disposed outwardly from the second barrier layer (20).

Abstract: The invention includes a process for copper metallization of an integrated circuit, comprising the steps of forming tantalum on a substrate, forming tantalum nitride over the tantalum, forming titanium nitride over the tantalum nitride, forming copper over the titanium nitride and integrated circuits made thereby. The invention is particularly useful in forming damascene structures with large aspect ratios.

Abstract: According to a disclosed embodiment, the surface of a semiconductor wafer is covered by an etch stop layer. For example, the etch stop layer can be composed of silicon dioxide. A cap layer is then fabricated over the etch stop layer. For example, the cap layer can be a polycrystalline silicon layer fabricated over the etch stop layer. The cap layer is then selectively etched down to the etch stop layer creating an opening in the cap layer according to a pattern. The pattern can be formed, for example, by covering the cap layer with photoresist and selective etching. Selective etching can be accomplished by using a dry etch process which etches the cap layer without substantially etching the etch stop layer. The etch stop layer is then removed using, for example, a hydrogen-fluoride cleaning process. A semiconductor crystal is then grown by epitaxial deposition in the opening. For example, the semiconductor crystal can be silicon-germanium. Moreover, a single crystal semiconductor structure of high quality, i.

Abstract: The present invention pertains to systems and methods for reducing the agglomeration of copper deposited by physical vapor deposition. More specifically, the invention pertains to systems and methods for depositing copper seed layers on a semiconductor wafer. The invention involves the use of an anti-agglomeration agent, so that the copper deposition is completed in an even, continuous and conformal manner.

Abstract: Disclosed are multilevel interconnects for integrated circuit devices, especially copper/dual damascene devices, and methods of fabrication. Methylated-oxide type hardmasks are formed over polymeric interlayer dielectric materials. Preferably the hardmasks are materials having a dielectric constant of less than 3 and more preferably 2.7 or less. Advantageously, both the hardmask and the interlayer dielectric can be spincoated.

Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.

Abstract: A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line.

Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by treating the exposed planarized surface of the Cu or Cu alloy with a plasma containing NH3 and N2 under mild steady state conditions, thereby avoiding sensitizing the Cu or Cu alloy surface before capping layer deposition with an attendant improvement in electromigration resistance and wafer-to-wafer uniformity. Embodiments include treating the Cu or Cu alloy surface with a plasma at a relatively high N2 flow rate of about 8,000 to about 9,200 sccm and a relatively low NH3 flow rate of about 210 to about 310 sccm.

Abstract: The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu at a reduced RF power, e.g., about 400 to about 500 watts and an increased spacing, e.g., about 680 to about 720 mils, to reduce the compressive stress of the deposited silicon nitride layer to below about 2×107 Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NH3 diluted with N2, ramping up the introduction of SiH4 and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure and N2 flow rate during plasma treatment, SiH4 ramp up and silicon nitride deposition.

Abstract: A method of manufacturing multilevel interconnects. A single or dual damascene interconnect structure is formed in a first dielectric layer. A cap layer or middle etch stop layer is formed over the interconnect structure and the first dielectric layer. The cap layer or the middle etch stop layer is treated with nitrogen plasma to convert a hydrophobic surface into a hydrophilic surface. An adhesion promoter layer is formed over the cap layer or middle etch stop layer. A low-k dielectric layer is formed over the adhesion promoter layer. A single or dual damascene structure is formed in the low-k dielectric layer, thereby forming a multilevel interconnect.

Abstract: A method for depositing tungsten nitride uses a source gas mixture having a silicon based gas for depositing the tungsten nitride to overlie a deposition substrate. A non-planar storage capacitor has a tungsten nitride capacitor electrode.

Abstract: In a semiconductor device, a contact layer is provided between a silicon-containing insulating film SiO2, etc. or a metal wiring layer, and a fluorine-containing carbon CF film to increase their adhesion. For this purpose, SiC film deposition gases, such as SiH4 gas and C2H4 gas, are excited into plasma to stack a SiC film [200] as the contact layer on the top surface of a SiO2 film [110]. After that, switching of deposition gases is conducted for about 1 second by introducing SiH4 gas, C2H4 gas, C4F8 gas and C2H4 gas. Subsequently, CF film deposition gases, such as C4F8 gas and C2H4 gas, for example, are excited into plasma to deposit[e] a CF film [120] on the SiC film [200].

Abstract: Interconnects in porous dielectric materials are coated with a SiC-containing material to inhibit moisture penetration and retention within the dielectric material. Specifically, SiC coatings doped with boron such as SiC(BN) show particularly good results as barrier layers for dielectric interconnects.

Abstract: A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A seed layer is deposited over the barrier layer and a conductor core is deposited over the seed layer, filling the opening of in the channel dielectric layer. The seed and barrier layers are then removed above the dielectric layer. A conductive layer is then deposited, filling any voids or depressions in the conductor core, and is subsequently removed above the dielectric layer resulting in a conductive channel of uniform thickness.

Abstract: A method is disclosed to improve copper barrier and adhesion properties of copper interconnections in integrated circuits. It is shown that combining ion metal plasma (IMP) deposition along with in-situ chemical vapor deposition (CVD) of barrier and adhesion materials provides the desired adhesion of and barrier to diffusion of copper in damascene structures. IMP deposition is performed with tantalum or tantalum nitride while CVD deposition is performed with a binary or a ternary compound from a group consisting of titanium nitride, tungsten nitride, tungsten silicon nitride, tantalum silicon nitride, titanium silicon nitride. IMP deposition provides good adhesion of copper to insulator materials, while CVD deposition provides good sidewall coverage in a copper filled trench and a copper seed layer provides good adhesion of bulk copper to adhesion/barrier layer. The IMP/CVD deposited adhesion/barrier layer is thin, thus providing low via resistance.

Abstract: A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure—single, dual, or multi-structure—is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer.

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

Abstract: A semiconductor device has a dielectric film made of a fluorine-added carbon film formed on a substrate, a metallic layer formed on the fluorine-added carbon film and an adhesive layer formed between the dielectric film and the metallic layer. The adhesive layer is made of a compound layer having carbon and the metal (or metal the same as the metal included in the metallic layer), to protect the metallic layer from being peeled-off from the fluorine-added carbon film.

Abstract: A refractory Metal Nitride and a refractory metal Silicon Nitride layer (64) can be formed using metal organic chemical deposition. More specifically, tantalum nitride (TaN) (64) can be formed by a Chemical Vapor Deposition (CVD) using Ethyltrikis (Diethylamido) Tantalum (ETDET) and ammonia (NH3). By the inclusion of silane (SiH4), tantalum silicon nitride (TaSiN) (64) layer can also be formed. Both of these layers can be formed at wafer temperatures lower than approximately 400° C. with relatively small amounts of carbon (C) within the film. Therefore, the embodiments of the present invention can be used to form tantalum nitride (TaN) or tantalum silicon nitride (TaSiN) (64) that is relatively conformal and has reasonably good diffusion barrier properties.

Abstract: A method that enhances performance of copper damascene by embedding TiN layer is proposed. The spirit of the invention is that a CVD TiN layer is inserted between the copper seed layer and the dielectric layer to improve the quality of copper layer. Herein, the TiN layer can either be located between the copper seed layer and the barrier layer or be located between the barrier layer and the dielectric layer. Because the barrier layer and the copper seed layer are formed by physical vapor deposition in current mass product, a higher side wall converge of the CVD TiN layer can be obtained owing to the higher conformity nature of CVD technology. Therefore, a better sidewall CVD TiN converge serves as an extra protection layer for copper self diffusion. Furthermore, it also acts as a copper seed layer to remedy side wall void problems due to copper seed layer discontinuity. Thus, not only the quality of copper layer is improved but also the performance of copper damascene process is enhanced.

Abstract: A semiconductor interconnect structure having a substrate with an interconnect structure patterned thereon, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer. A process for creating such structures is described. The barrier layer is formed using atomic layer deposition techniques. Subsequently, a pre-seed layer is formed to create a heteroepitaxial interface between the barrier and pre-seed layers. This is accomplished using atomic layer epitaxy techniques to form the pre-seed layer. Thereafter, a seed layer is formed by standard deposition techniques to create a homoepitaxial interface between the seed and pre-seed layers. Upon this layered structure further bulk deposition of conducting materials is done. Excess material is removed from the bulk layer and a sealing layer is formed on top to complete the interconnect structure.

Abstract: A new method is provided to replace tungsten plugs for wafers that trigger the WCVD backside alarm. In this new rework process, the original TiN glue layer is sputter etched back and a new (“fresh”) 100-Angstrom thick layer of TiN is deposited. The new tungsten plug is created over the top surface of the refreshed glue layer.

Abstract: The present invention is a new and improved method for fabricating aluminum metal pad structures wherein a thin adhesion layer of aluminum is placed in between the underlying copper metal and the top tantalum nitride pad barrier layer providing improved adhesion to the pad metal stack structure. In summary, present invention teaches a method comprising of forming a copper underlayer, forming the key aluminum adhesion layer, forming the tantalum nitride barrier layer, and finally forming the aluminum pad. The problem of adhesion of metal pad to underlying layers, dielectrics, and polymers in is not unique to the manufacture of multi-layer electronic circuit chips and modules, but is encountered in other technologies involved in other types of electronic elements, e.g., the formation of capacitors or even other technologies entirely unrelated to the fabrication of electrical devices.

Abstract: In forming an interconnection having a structure in which an Al interconnection is covered with an interlayer insulating film, for the purpose of preventing voids to be created in the Al interconnection layer, together with suppressing the current leakage owing to the generation of etching residues, a multi-layered structure comprising a barrier layer, an Al interconnection metal layer, a Ti layer and an anti-reflection layer is formed on a semiconductor substrate having an insulating surface, and thereafter layers of said multi-layered structure are patterned, at least, down to the Ti layer into the shape of an interconnection pattern, and said patterned structure is heated so as to turn the Ti layer into an AlTi alloy layer and, then, the steps of growing an interlayer insulating film to bury said patterned interconnection, planarizing the interlayer insulating film and carrying out another heat treatment to degas the interlayer insulating film are performed.

Abstract: A method of minimizing the volume of the depressions 240 in aluminum cavity filling processes, by-depositing a conformal first layer of aluminum alloy 220 by chemical vapor deposition, long-throw sputtering, collimated sputtering, or ionized physical vapor deposition, to partially fill the cavity 202. This layer is preferably deposited at low temperature (eg. less than 300 degrees C.) and lower deposition pressure (if deposited by sputtering). Subsequently, a second layer of aluminum alloy 230 is deposited by sputtering at temperatures greater than 350 degrees C. and at high power (e.g. greater than 10 kW) to close the mouth of cavity 202. The second layer of aluminum 230 is then forced into the remaining volume of the cavity 202. As part of the cavity 202 is filled with aluminum, alloy 220 before the high pressure aluminum extrusion/reflow, less material is required to be transported into the cavity 202. Therefore, a smaller depression 240 above the cavity is produced.

Abstract: A contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon or of a metal follows.

Abstract: Tungsten nitride adhesion to an underlying dielectric is enhanced by forming a thin layer of silicon over the dielectric before depositing the tungsten nitride. A twenty angstrom layer of amorphous silicon is formed over a silicon oxide dielectric. Tungsten nitride is formed over the silicon layer using a plasma enhanced chemical vapor deposition with tungsten hexafluoride and nitrogen. As the tungsten nitride is formed, the tungsten hexafluorine and nitrogen reacts with the amorphous silicon to produce an adhesion layer that includes silicon nitride and tungsten silicide.

Abstract: A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

Abstract: A hard Al oxide film having a high melting point, which grows on the surface of an Al—Cu film during a wafer is carried in atmospheric air, obstructs the burying of a viahole with the Al—Cu film by high pressure reflow, with a result that a void remains in the hole. The present invention is intended to remove such an Al oxide film grown on the Al—Cu film formed by sputtering, by Ar+ sputtering/etching directly before high pressure reflow. Moreover, when a Ti oxide film is present on the surface of a Ti based underlying film formed by CVD, an Al oxide film is possibly grown at the boundary between the Ti based underlying film and an Al—Cu film laminated thereon. In this case, the Ti oxide film is similarly removed directly before formation of the Al—Cu film, thereby preventing the growth of the Al oxide film.

Abstract: In the presently disclosed invention, a method is provided to avoid damage to a copper interconnect while subjecting the interconnect to chemical-mechanical polishing (CMP). First, a copper barrier layer is formed in a damascene structure. Then, prior to the deposition of copper metal into the damascene openings, a barrier layer is formed on the inside walls of the damascene structure. In a first embodiment, the copper barrier layer is deposited at high temperature. Then, it is cooled down in a prescribed manner. Subsequently, a copper seed layer is formed over the barrier, which is followed by the electro-chemical deposition (ECD) of copper, to form the copper damascene interconnect. Alternatively, in a second embodiment, the copper layer is formed at low temperature. Then it is annealed at a high temperature, followed by wafer cooling. Subsequently, copper seed layer is formed over the barrier layer. Next, ECD copper is formed in the damascene structure.

Abstract: A semiconductor, and manufacturing method therefor, is provided with a barrier/adhesion layer, having cobalt, nickel, or palladium for semiconductors having conductive materials of copper, silver or gold. The barrier/adhesion layer can be alloyed with between about 0.2% and 4% tantalum, molybdenum, or tungsten to increase barrier effectiveness and lower resistivity.