Abstract: Methods and systems for controlling concentration profiles of deposited films using machine learning are provided. Data associated with a target concentration profile for a film to be deposited on a surface of a substrate during a deposition process for the substrate is provided as input to a trained machine learning model. One or more outputs of the trained machine learning model are obtained. Process recipe data identifying one or more sets of deposition process settings is determined from the one or more outputs. For each set of deposition process setting, an indication of a level of confidence that a respective set of deposition process settings corresponds to the target concentration profile for the film to be deposited on the substrate is also determined.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

Abstract: A method of manufacturing a graphene structure, the graphene structure, and a graphene device including the graphene structure, include depositing a metal layer over a silicon carbide substrate; and performing, at a first temperature, a heat treatment on the silicon carbide substrate over which the metal layer is deposited to form a composite layer and a graphene layer on the silicon carbide substrate. The composite layer includes a metal.

Abstract: A lead frame and a semiconductor package including the lead frame are provided. The lead frame includes: a base material; a first metal layer which is formed on at least one side of the base material, of which a surface is roughly formed, and which includes copper or nickel; a second metal layer which is formed on a surface of the first metal layer, of which a surface is roughly formed, and which includes palladium or a palladium alloy; a third metal layer which is formed on a surface of the second metal layer, of which a surface is roughly formed, and which includes gold or a gold alloy; and a fourth metal layer which is formed on a surface of the third metal layer, of which a surface is roughly formed, and which includes metal that includes silver.

Abstract: A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.

Abstract: A method of making a microelectronic connection component is disclosed. A plurality of portions of a conductive, etch-resistant material is provided on a surface of a metallic sheet. The sheet is etched from the surface to form posts extending generally parallel to one another aligned with the portions of the etch-resistant material. A microelectronic device is provided having one of a front face or a rear face overlying first ends of the posts. Second ends of the posts remote from the first ends face away from the microelectronic device as interconnection terminals for the connection component. At least some of the posts are electrically connected to the microelectronic device.

Abstract: A method of treating a component can include providing a component including a plurality of metallic posts extending generally parallel to one another. The providing step can be performed so that the posts have solder on the tips of the posts but not covering other portions of the posts. The method can include reflowing the solder provided on the posts so that the solder coats the posts. The providing step may be performed so that, prior to the reflowing step, the solder covers only the tips of the posts. The providing step can include depositing portions of the solder on a surface of a metallic sheet and etching the sheet from the surface. The plurality of posts may comprise elongated posts.

Abstract: A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.

Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.

Abstract: There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The gate electrodes of tantalum can withstand this heat treatment.

Abstract: In some embodiments, after depositing conductive material on substrates in a deposition chamber, a reducing gas is introduced into as the chamber in preparation for unloading the substrates. The deposition chamber can be a batch CVD chamber and the deposited material can be a metal nitride, e.g., a transition metal nitride such as titanium metal nitride. As part of the preparation for unloading substrates from the chamber, the substrates may be cooled and the chamber is backfilled with a reducing gas to increase the chamber pressure. It has been found that oxidants can be introduced into the chamber during this time. The introduction of a reducing gas has been found to protect exposed metal-containing films from oxidation during the backfill and/or cooling process. The reducing gas is formed of a reducing agent and a carrier gas, with the reducing agent being a minority component of the reducing gas.

Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

Abstract: It is an object of the present invention to provide a method for manufacturing a substrate having film patterns such as an insulating film, a semiconductor film, and a conductive film in simple processes. It is another object of the invention to provide a method for manufacturing a semiconductor device with high throughput and high yield at low cost.

Abstract: A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure c

Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

Abstract: A method for manufacturing an interconnect structure situated on a semiconductor wafer having a substrate assembly thereon. The interconnect structure is formed in a recess such as a trench, a hole, a via, or a combination of a trench and a hole or via within a dielectric material situated on the substrate assembly of the semiconductor wafer. At least one barrier layer is deposited within the recess. A seed layer helping to promote nucleation, deposition, and growth of a material that will be used to fill up the recess is then deposited on the barrier layer. An electrically conductive layer is then formed upon the seed layer. An energy absorbing layer will then be formed upon the conductor layer, where the energy absorbing layer has a greater thermal absorption capacity than that of the electrically conductive layer. The energy absorbing layer is heated, with or without an applied heightened pressure, to cause the conductor layer to flow so as to fill voids that have formed within the dielectric structure.

Abstract: The present invention is directed to a new bonding pad structure having a rugged contact interface that makes it more difficult for a crack to grow from the peripheral edge of the bonding pad. The rugged contact interface also helps to accumulate more solder paste on the edge of the bonding pad, increase the thickness of the solder layer near the pad edge and prevent the pad edge from being oxidized and turning into a crack initiation point.

Abstract: A method for making a film stack containing one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes at least one transfer chamber coupled to at least one load lock chamber, at least one first physical vapor deposition (PVD) chamber configured to deposit a first material layer on a substrate, and at least one second PVD chamber for in-situ deposition of a second material layer over the first material layer within the same substrate processing system without breaking the vacuum or taking the substrate out of the substrate processing system to prevent surface contamination, oxidation, etc. The substrate processing system is configured to provide high throughput and compact footprint for in-situ sputtering of different material layers in designated PVD chambers.

Abstract: A wiring pattern formation method in which a wiring pattern is formed by arranging, in a region which is demarcated by a partition wall, liquid material which includes an electrically conductive material, including: arranging a resin material around the periphery of a region upon which the wiring pattern is to be formed; imparting liquid affinity to a demarcated region which has been demarcated by the resin material; narrowing down the demarcated region by flowing out the resin material towards and into the demarcated region; and forming the partition wall by curing the resin material.

Abstract: A process for forming bumps on electrode pads for a wiring board including a substrate and a plurality of electrode pads. The process (a) forms a laminated two-layer film on the wiring board and forms a pattern of apertures at positions corresponding to the electrode pads, the laminated two-layer film including a lower layer containing an alkali-soluble radiation-nonsensitive resin composition and an upper layer containing a negative radiation-sensitive resin composition; (b) fills a low-melting metal in the aperture pattern; (c) reflows the low-melting metal by pressing or heating to form bumps; and (d) peels and removes the laminated two-layer film from the board. The laminated film including two layers with different properties permits high resolution and easy peeling.

Abstract: The present invention provides nano-patterning based on flow of an ion current within an ionic conductor to bring ions in proximity to a microscope probe tip touching a surface of the conductor. These ions are then electrochemically reduced to form one or more features on the surface. Ion current flow and the electrochemical reaction are driven by an electrical potential difference between the tip and the ionic conductor. Such features can be erased by reversing the polarity of the potential difference. Indentations can be formed by mechanically removing features formed as described above. The ions in the ion current can be provided by the ionic conductor and/or by oxidation at a counter electrode.

Abstract: A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said BARC layer; and, forming at least a first contact opening exposing said etch stop layer by a first etching process.

Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.

Abstract: On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Next, a via hole 211 and an interconnection trench 217 are formed, and on the sacrificial film 213 are then formed a barrier metal film 219 and a copper film 221. CMP for removing the extraneous copper film 221 and barrier metal film 219 are conducted in a two-step process, i. e., the first polishing where polishing is stopped on the surface of the barrier metal film 219 and the second polishing where the remaining barrier metal film 219 and the tapered sacrificial film 213 are polished.

Abstract: One embodiment of the present invention provides a memory cell device. The memory cell device includes a first electrode, a phase-change material adjacent the first electrode, and a second electrode adjacent the phase-change material. The phase-change material has a sublithographic width defined by a pattern shrink material process.

Abstract: In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the insulative layers sandwiched between layers of metal wiring—in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.

Abstract: The present invention provides a semiconductor device including a plurality of wirings or conductive film patterns formed on a semiconductor substrate, and clearances are provided between the wirings or the conductive film patterns. On a corner or an end part of at least one of the wirings or the conductive film patterns, protrusions are formed to protrude, facing the clearances between the wirings or the conductive film patterns. Thereby, defects will not occur in the insulating protective film after an etching step for forming an aperture for exposing a bonding pad, and thus, a semiconductor device is manufactured without being subjected to an additional process that raises the manufacturing cost. The present invention provides also a method of manufacturing the semiconductor device.

Abstract: Nanolithographic deposition of metallic nanostructures using coated tips for use in microelectronics, catalysis, and diagnostics. AFM tips can be coated with metallic precursors and the precursors patterned on substrates. The patterned precursors can be converted to the metallic state with application of heat. High resolution and excellent alignment can be achieved.

Abstract: A scheme for filling plugs through chemical mechanical polishing comprises depositing a malleable conductive layer over a dielectric layer having openings formed therein. The malleable conductive layer is deposited such that a liner is formed within the openings, however the openings are not completely filled. A chemical mechanical polishing process using an alumina based slurry at a neutral or slightly basic pH and no oxidizer is used to smear the malleable conductive layer sufficiently to fill the remainder of the openings in the dielectric layer forming filled or substantially filled plugs.

Abstract: Oxide voiding is eliminated was substantially reduced by laser thermal annealing. Embodiments include fabricating flash memory devices by depositing a BPSG over spaced apart transistors as the first interlayer dielectric with voids formed in gaps between the transistors and laser thermal annealing the BPSG layer in flowing nitrogen to eliminate or substantially reduce the voids by reflowing the BPSG layer.

Abstract: The surface of a solder ball and a conductive wire for a semiconductor package are coated with a predetermined colorant. Various colorants may be used according to the diameter and metal composition of the solder ball and the conductive wire. The colorant is formed by mixing organic compound and dye of a predetermined color. Examples of organic compounds excellent in physicochemical bonding with metal include benzotriazole, alkylimidazole and benzimidazole. The solder ball is fabricated by coating an organic compound of a predetermined color on the surface of a typical solder ball. The conductive wire is fabricated by coating an organic compound of a predetermined color on a general conductive wire between heat process and winding. Moreover, the solder ball is evaporated in a reflowing step after bumped via flux and the conductive wire is evaporated in a wire bonding step so that the solder ball and the conductive wire return to their unique colors.

Abstract: According to the present invention, when a wiring layer using copper is formed, an interlayer insulation film is formed on a semiconductor substrate having a conductive portion of an element. A contact hole, which is connected to at least the conductive portion, is formed in the interlayer insulation film. A wiring groove is formed in the surface of the interlayer insulation film including a region where the contact hole is formed. A barrier metal having a tungsten carbide film on its surface is formed on the surface of the interlayer insulation film and in the wiring groove and contact hole in contact with the conductive portion. A copper film is then formed on the barrier metal in contact with the tungsten carbide film. After that, the contact hole and wiring groove are completely filled with the copper film by heat treatment. An excess portion is removed from the copper film except in the contact hole and wiring groove thereby to form a copper buried wiring layer.

Abstract: The present invention is directed to a method of forming a dual damascene pattern in a fabrication process of a semiconductor device, which is capable of simplifying a fabrication process of a semiconductor device by filling a via hole with a photoresist, using a reflow phenomenon of the photoresist, in an ashing process.

Abstract: A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess region, depositing selectively an anti-nucleation layer on the barrier metal except in the recess region, depositing a CVD-Al layer on the barrier metal in the recess region, depositing a metal or a metal alloy inhibiting aluminum migration on the anti-nucleation layer and the barrier metal except in the recess region, and depositing a PVD-Al layer and re-flowing the PVD-Al layer, for improving the quality of aluminum grooves. The present method inhibits PVD-Al migration and grain growth, which results in preventing abnormal patterning in the semiconductor device.

Abstract: A semiconductor device is constituted by embedding an Al wiring layer in a second object formed on a interlayer-insulating film on one principal plane of a semiconductor substrate and connecting with an Al wiring formed on the substrate and at least, an Nb liner film and NbAl alloy film are formed between the second object and the Al wiring layer.

Abstract: A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor.

Abstract: An aluminum wiring is selectively formed within a contact hole or groove of a substrate. An intermediate layer which includes nitrogen is formed over the main surface of a substrate and over the interior surface of the contact hole or groove. A first surface portion of the intermediate layer which is located over the main surface of the substrate is treated with a plasma to form a passivity layer at the first surface portion of the intermediate layer. Then, without an intervening vacuum break, an aluminum film is CAD deposited only over a second surface portion of the intermediate layer which is located over the interior surface of the contact hole or recess. The plasma treatment of the first surface portion of the intermediate layer prevents the CAD deposition of the aluminum film over the first surface portion of the intermediate layer.

Abstract: A method for making a semiconductor device is provided. The method allows for depositing a layer of a doped dielectric. The method further allows for executing plasma etching so that one or more etchant gases flow over the layer of doped dielectric. A redepositing step allows for redepositing another layer of doped dielectric over the plasma etched layer. The present invention enables to remove crystal defects that may be present in the doped dielectric surface and improve surface planarity.

Abstract: A method of constructing a semiconductor device 10 is disclosed which includes a reflow step. The device 10 comprises a conductive via 20 electrically connected to a conductive interconnect 28. The formation of interconnect 28 can result in damage to conductive via 20 including the removal of material within conductive via 20 to form a void 30. The metal reflow step involves heating the structure to a temperature short of the melting point of the conductive material forming the conductive via 20 and the conductive interconnect 28. The reflow step results in the migration of conductive material into the void 30 and a widening of the conductive interface between the conductive via 20 and the conductive interconnect 28.

Abstract: In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the insulative layers sandwiched between layers of metal wiring—in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: A method of forming a film having enhanced reflow characteristics at low thermal budget is disclosed, in which a surface layer of material is formed above a base layer of material, the surface layer having a lower melting point than the base layer. In this way, a composite film having two layers is created. After reflow, the surface layer can be removed using conventional methods.

Abstract: A manufacturable method for forming a highly reliable electrical interconnection. An electrical interconnection pattern is first formed in a dielectric layer on a semiconductor substrate as recessed regions in the dielectric layer. A conductive layer primarily comprising copper is thereafter deposited over the surface and in the recessed regions of the dielectric layer. The conductive layer is then reflowed to fill the recessed regions of the dielectric layer with substantially no void formation. This reflow process may also be used to improve the step coverage of any such copper layer deposited over the surface of a substrate to be used in conjunction with alternate techniques for forming electrical interconnections including photoresist patterning and etch.

Abstract: Micromachined extrusions on the micrometer scale is realized using compressive stresses resulting from electromigration-induced mass transport in planarized conductors. Extrusions are formed through simple die patterns etched through a passivation layer overlaying the conductors.

Abstract: Metallization process sequences are provided for forming reliable interconnects including lines, vias and contacts. An initial barrier layer, such as Ta or TaN, is first formed on a patterned substrate followed by seed layer formed using high density plasma PVD techniques. The structure is then filled using either 1) electroplating, 2) PVD reflow, 3) CVD followed by PVD reflow, or 4) CVD.

Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.

Abstract: Within a method for forming a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned conductor layer having a topographic variation at a periphery of the patterned conductor layer. There is then formed over the substrate and passivating the topographic variation at the periphery of the patterned conductor layer a planarizing passivation layer formed of a thermally reflowable material. There is then formed upon the planarizing passivation layer a dimensionally stabilizing layer. Finally, there is then thermally annealed the microelectronic fabrication to form from the planarizing passivation layer a thermally annealed planarizing passivation layer. By employing formed upon the planarizing passivation layer the dimensionally stabilizing layer, there is attenuated within the thermally annealed planarizing passivation layer replication of the topographic variation at the periphery of the patterned conductor layer.

Abstract: A process for forming silicate glass layers on substrates is disclosed. A silicate glass layer is first deposited onto a substrate, such as a semiconductor wafer. The wafer is then placed in a thermal processing chamber and heated in the presence of a reactive gas. The object is heated to a temperature sufficient for reflow of the silicate glass. In one embodiment, the atmosphere contained within the processing chamber comprises steam in combination with a reactive gas. The reactive gas can be, for instance, hydrogen, oxygen, nitrogen, dinitrogen oxide, ozone, hydrogen peroxide, atomic and/or molecular hydrogen, or radicals or mixtures thereof.

Abstract: A method for manufacturing a metal interconnection includes the steps of, preparing an active matrix provided with a substrate, an insulating layer and an opening formed through the insulating layer, forming a diffusion barrier layer on surfaces of the opening and the insulating layer, forming a protection layer on the diffusion barrier layer, forming a first metal layer into the opening and upon the protection layer, forming a second metal layer on the first metal layer, and polishing back the first and the second metal layer to a top surface of the insulating layer, thereby forming a metal interconnection.

Abstract: A manufacturable method for forming a highly reliable electrical interconnection. An electrical interconnection pattern is first formed in a dielectric layer on a semiconductor substrate as recessed regions in the dielectric layer. A conductive layer primarily comprising copper is thereafter deposited over the surface and in the recessed regions of the dielectric layer. The conductive layer is then reflowed to fill the recessed regions of the dielectric layer with substantially no void formation. This reflow process may also be used to improve the step coverage of any such copper layer deposited over the surface of a substrate to be used in conjunction with alternate techniques for forming electrical interconnections including photoresist patterning and etch.