Abstract: A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor.

Abstract: A semiconductor device having a conductive layer side surface slope of at least 90° and a method for making the same is provided. An interlayer dielectric film and a conductive layer are formed on a semiconductor substrate. The interlayer dielectric film has a side surface slope defining a hole of less than 90°. A conductive layer having a side surface slope of at least 90° is formed in the hole defined by the interlayer dielectric film. The semiconductor device is manufactured by coating a preliminary film on a semiconductor substrate. Patterning the preliminary film forms a preliminary film pattern having a side surface slope of 90°. The interlayer dielectric film is formed on the semiconductor substrate and the preliminary film pattern. Removing some of the interlayer dielectric film exposes an upper surface of the preliminary film pattern.

Abstract: The present invention is a method of fabricating interconnects. A semiconductor substrate having a dielectric layer is provided. The dielectric layer has a via opening therein, which exposes the semiconductor substrate. Next, the surfaces of the via opening is covered with a conformal titanium layer formed by a sputtering process. The surface of the conformal titanium layer is covered with an Al—Si—Cu alloy layer formed by a sputtering process at a temperature of about 0° C. to 200° C. Then, the surface of the Al—Si—Cu alloy layer is covered with an Al—Cu alloy layer formed by a sputtering process at a temperature of about 380° C. to 450° C., which Al—Cu alloy layer fills the via opening. The Al—Cu alloy layer, the Al—Si—Cu alloy layer and the wetting layer on the dielectric layer are patterned by photolithography and etching process.

Abstract: There is formed on a semiconductor substrate a lamination of a first insulating film of nondoped silicon glass or the like and, on this first insulating film, a second insulating film of boron phosphor silicate glass or the like, with a conductor layer between the two insulating films. A hole is first dry-etched in the second insulating film, leaving the substrate surface covered by the first insulating film. Then the second insulating film is heated to a reflow temperature such that the hole is thermally deformed, flaring as it extends away from the insulating film. Then a second hole is dry-etched in the first insulating film through the first recited hole in the second insulating film, with the consequent exposure of the semiconductor surface. Then a contract electrode is fabricated by filling the first and the second hole with an electroconductive material into direct contact with the substrate surface.

Abstract: The present invention teaches a special annealing process to “heal” electrochemical copper deposited (ECD) defects in a dual damascene via and trench structure. The annealing step is processed after the electrochemical deposition (ECD) of the top excess copper and before the chemical mechanical polishing (CMP) of the copper. The key processing steps of this invention are the special annealing steps at key temperatures, ambient, pressures and times to anneal out the defective copper voids in the dual damascene structure. These annealing conditions are special annealing steps to promote low temperature copper surface diffusion to “heal” the voids and other defectives within the copper trench and via structure. The special annealing conditions of: temperature, ambient, pressure and time are the following: temperature in a range of about 300 to 500° C.

Abstract: On a silicon oxide film covering a gate electrode portion, a reflowed and polished BPSG film is formed. A second interconnection layer is formed on the BPSG film. To cover the second interconnection layer, a silicon oxide film having a thickness of at least the substantial thickness of the second interconnection layer is formed on a silicon oxide film. Thus, the planarity of the base of the interconnection layer is ensured and displacement of the interconnection layer is suppressed. Accordingly, a semiconductor device having a high degree of integration is obtained.

Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.

Abstract: The present invention provides a method of easily planarizing the uneven surface of a substrate having an uneven surface. This method comprises the steps of forming a coating film containing spherical fine particles on a surface of a smooth substrate; sticking the surface of the smooth substrate provided with the coating film containing spherical fine particles to the uneven surface of a substrate having an uneven surface; and transferring the coating film containing spherical fine particles to the uneven surface of the substrate so that the uneven surface is planarized.

Abstract: Impurities are added to a conductor layer in a semiconductor process to prevent formation of void spaces and encourage complete filling of contacts. The impurities reduce the melting point and surface tension of a conductor layer, thereby improving filling characteristics during a reflow step. The impurities may be added at any time during the process, including during conductor deposition and/or reflow.

Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film and causing never melting to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently.

Abstract: A hard Al oxide film having a high melting point, which grows on the surface of an Al—Cu film during a wafer is carried in atmospheric air, obstructs the burying of a viahole with the Al—Cu film by high pressure reflow, with a result that a void remains in the hole. The present invention is intended to remove such an Al oxide film grown on the Al—Cu film formed by sputtering, by Ar+ sputtering/etching directly before high pressure reflow. Moreover, when a Ti oxide film is present on the surface of a Ti based underlying film formed by CVD, an Al oxide film is possibly grown at the boundary between the Ti based underlying film and an Al—Cu film laminated thereon. In this case, the Ti oxide film is similarly removed directly before formation of the Al—Cu film, thereby preventing the growth of the Al oxide film.

Abstract: Multilayer alignment keys in an integrated structure and a method of aligning using the keys are provided. Alignment keys are formed on a semiconductor substrate in a multilayer structure. The length of the alignment key in one layer can be different from that of the alignment key in underlying and/or overlying layer. Alternatively, the number of alignment keys can be different in each layer. Thus alignment weight can be imposed differently on each layer, thereby increasing alignment accuracy.

Abstract: A method is provided for forming improved quality interlevel aluminum contacts in semiconductor integrated circuits. A contact opening is formed through an insulating layer. A barrier layer is deposited over the surface of the integrated circuit. An aluminum layer is then deposited at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

Abstract: A method of manufacturing a semiconductor device utilizing a multi-chamber apparatus comprises the steps of forming a metal film on an insulating layer under the lower pressure within a film forming apparatus and reflowing the metal film on the insulating film, after transferring the semiconductor substrate to a reflow apparatus from the film forming apparatus under the vacuum atmosphere of 1.3×10−6 Pa or less, by simultaneously heating a plurality of semiconductor substrates under the vacuum atmosphere of 1.3×10−6 Pa or less.

Abstract: A method of fabricating a self-aligned metal silicide. Two neighboring gates are formed on a substrate, and each of the gates comprises a cap layer thereon. Source/drain regions are formed in the substrate. The source/drain regions comprise a common source/drain region between these two gates. A metal suicide layer is formed on the source/drain region. A first insulation layer is formed to cover the source/drain regions. The cap layer is removed, followed by a pre-amorphous implantation process. A metal silicide layer is formed on the gate. A passivation is formed to protect the metal silicide layer on the gate. A second insulation layer is formed to cover the passivation layer and the first insulation layer. The second and the first insulation layers are patterned to form a contact window to expose the common source/drain region.

Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.

Abstract: A multistep method for planarizing a silicon oxide insulating layer such as a deposited borophosphosilicate glass (BPSG) layer. The method includes several different planarization stages. During an initial, pre-planarization stage, a substrate having a BPSG layer deposited over it is loaded into a substrate processing chamber. Then, during a first planarization stage after the pre-planarization stage, oxygen and hydrogen are flowed into the substrate processing chamber to form a steam ambient in said chamber and the substrate is heated in the steam ambient from a first temperature to a second temperature. The first temperature is below a reflow temperature of the BPSG layer and the second temperature is sufficient to reflow the layer. After the substrate is heated to the second temperature during a second planarization stage, the temperature of the substrate and the conditions within the substrate processing chamber are maintained at conditions sufficient to reflow the BPSG layer in the steam ambient.

Abstract: Method for forming an inter-level dielectric layer upon a substrate employed within a microelectronics fabrication. There is first provided a substrate. There is then formed upon the substrate a patterned microelectronics layer. There is then formed upon and between the patterned microelectronics layer and substrate a blanket first silicon oxide layer employing high density plasma chemical vapor deposition. There is then an optional exposure of the first blanket silicon oxide layer to a nitrogen plasma treatment prior to formation thereupon of a second blanket silicon oxide dielectric layer employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition, where the nitrogen plasma exposure results in improved gap fill within the silicon oxide dielectric layer, whereas avoidance of exposure to the nitrogen plasma results in formation of voids within the blanket second silicon oxide dielectric layer, leading to lower capacitance.

Abstract: A method of manufacturing a semiconductor device is provided in which a well patterned lead line structure is obtained. In one aspect of the invention, the method comprises steps of:depositing on a semiconductor wafer a metal layer for forming lead lines at a first predetermined temperature of about 400.degree. C., say; anddepositing an anti-reflective layer on the metal layer in the following multi-deposition steps:step 1: a thin anti-reflective layer is deposited on the metal layer near the first predetermined deposition temperature;step 2: the metal layer is cooled to a second predetermined deposition temperature of about 150.degree. C., say while interrupting the deposition of the anti-reflective layer; andstep 3: the anti-reflective layer is grown to a predetermined thickness by resuming the deposition thereof at the second predetermined deposition temperature.

Abstract: Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.

Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches.

Abstract: The present invention is a method and apparatus for filling voids in a substrate with a desired material to form conductive components and/or other features on the substrate. In one embodiment in accordance with the principles of the present invention, a substrate with voids is covered with a first layer of material and then a second layer of material is formed on top of the first layer. The first layer is deformable at a deformation temperature, while the second layer has a higher yield strength than the first layer and is substantially non-deformable at the deformation temperature. The second layer, for example, may be a rigid and/or substantially incompressible layer that distributes a driving force to the first layer. The second layer is then pressed against the first layer at a temperature equal to or greater than the deformation temperature to drive portions of the first layer into the voids in the substrate.

Abstract: A method for improving the planarization of a dielectric layer in the fabrication of metallic interconnects wherein a rapid thermal processing operation is used in order to consolidate exposed surfaces of a dielectric layer after local planarization of the dielectric layer. This method avoids damage to the dielectric layer caused during a pre-metal etching operation, and consequently, prevents residual tungsten from becoming lodged in fissures during subsequent tungsten deposition to produce stringers which may cause short circuiting on coming in contact with metal wiring.

Abstract: A new method of aluminum plug metallization in the manufacture of an integrated circuit device is described. An insulating layer is provided over the surface of a semiconductor substrate. At least one contact opening is provided through the insulating layer to the semiconductor substrate. A barrier metal layer is deposited over the surface of the insulating layer and within the contact opening. An aluminum layer is sputter deposited over the barrier metal layer and within the contact opening wherein a void is left within the contact opening. The aluminum layer is covered with a dielectric layer wherein the expansion coefficient of the dielectric layer is smaller than the expansion coefficient of the aluminum layer. The aluminum layer is reflowed using rapid thermal annealing wherein the overlying dielectric layer forces the aluminum layer to fill the contact opening completing the metallization in the fabrication of an integrated circuit device.

Abstract: A method and system for providing a via structure for a high conductivity metal of a integrated circuit is disclosed. In a first aspect the method and system comprises etching a photoresist material and a dielectric material down to the high conductivity metal to form a via hole. The via hole includes sputtered high conductivity metal on the sidewalls. The method and system further includes providing a via plug material within the via hole. The vial plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the dielectric material. In a second aspect, a via structure for an integrated circuit is disclosed in accordance with the present invention. The via structure includes a high conductivity metal and a dielectric material surrounding the high conductivity metal.

Abstract: An embodiment of the instant invention is a method of fabricating a conductive structure for electrically connecting one portion of a semiconductor device to another portion of the device, the method comprising the steps of: providing a continuous liner layer (step 104) of the semiconductor substrate, the liner layer comprised of CVD Al; forming a first conductor (step 106) on the liner layer, the first conductor formed using a source whose output power is in the range of 1 to 5 kW; and forming a second conductor (step 108) on the first conductor, the second conductor formed using a source whose output power is in the range of 10 to 20 kW. Preferably, the conductive structure is selected from the group consisting of: contact, via, and trench. In an alternative embodiment, a nucleation layer is formed (step 104) beneath the continuous liner layer. The nucleation layer is, preferably, comprised of titanium or a Ti/TiN stack.

Abstract: A method of forming a contact via includes forming a wiring, a first insulator layer, and a spin-on glass layer, respectively, over a semiconductor substrate. Fluorine ions are implanted into the spin-on glass layer. A second insulator layer is formed over the spin-on glass layer. The wiring is exposed by patterning the second insulator layer, the spin-on glass layer, and the first insulator layer, respectively.

Abstract: A method for forming a completely buried contact hole and a semiconductor device having a completely buried contact hole in an interconnection structure is disclosed. The completely buried contact hole includes a first insulating layer of a first thermal conductivity having a contact hole formed therein. A region of material of a second thermal conductivity formed in the first insulating layer adjacent the location of the contact hole. The second thermal conductivity is greater than the first thermal conductivity such that the thermal conductivity of the region of material is greater than the thermal conductivity of the insulating layer. A metal is formed in the hole which completely buries the contact hole.

Abstract: The present invention provides a method for preventing a polycide line situated between two dielectric layers from deformation during a reflow process for one of the dielectric layers by annealing the polycide line and thereby increasing its hardness prior to the reflow process being conducted. The annealing process can be carried out either before or after the polycide line is formed at an annealing temperature in the range between about 700.degree. C. and about 1000.degree. C. in a furnace or by a rapid thermal process.

Abstract: A manufacturing method for semiconductor devices such as dynamic RAM, etc. which removes the layer part more on the high position than an arbitrary position on a step forming a gradation by just a prescribed thickness when flattening a layer with a gradation formed of a high position part and a low position part. Then the projecting part created after the etching existing more on the low position side than at the arbitrary position of the gradation is eliminated by heat treatment.

Abstract: A polycrystalline silicon film is formed on the surface of a semiconductor substrate. An oxide film having a first impurity concentration is formed to cover the polycrystalline silicon film. A polycrystalline silicon film and a refractory metal silicide are formed on the surface of the oxide film having the first impurity concentration. An oxide film having a second impurity concentration higher than the first impurity concentration is formed to cover the polycrystalline silicon film and the refractory metal silicide. The third conductive layer is formed on the surface of the oxide film having the second impurity concentration.

Abstract: The present invention provides a method for minimizing voids in a plug. The process begins by forming a conformal barrier layer within the hole and then forming a metal plug within the hole. Thereafter, a cap layer is formed over the metal plug in which the cap layer has a lower thermal expansion coefficient than the metal plug. The hole is heated such that the metal in the hole flows to eliminate the void as a result of the compressive stress generated by the cap layer on the metal plug.

Abstract: A new method of forming the dielectric layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed overlying the insulating layer wherein the metal line mask is modified so that narrow trenches with constant width and depth are etched surrounding the metal lines and the remaining metal areas are not etched away but are left as dummy metal areas. A dielectric layer is deposited over the metal lines and dummy metal areas wherein voids are formed within the trenches between metal lines and wherein the top surface of the dielectric layer is planarized. The voids act to release system stress and to lower capacitance between the metal lines.

Abstract: A method for forming a dynamic random access memory device includes the step of forming a memory cell access transistor on a semiconductor substrate wherein the memory cell access transistor includes a source/drain region at a surface of the semiconductor substrate. An insulating layer is formed on the semiconductor substrate and on the memory cell access transistor wherein the insulating layer has a contact hole therein exposing a portion of the source/drain region of the substrate. A first conductive layer is chemical vapor deposited on the exposed portion of the source/drain region of the substrate, and a second conductive layer is physical vapor deposited on the first conductive layer opposite the substrate. A dielectric layer is formed on the second conductive layer opposite the substrate, and a third conductive layer is formed on the dielectric layer opposite the substrate.

Abstract: A semiconductor device and a method of manufacture therefor. The semiconductor device includes: (1) a substrate having a recess therein, (2) an aluminum-alloy layer located over at least a portion of the substrate and filling at least a portion of the recess and (3) a protective metal layer at least partially diffused in the aluminum-alloy layer, the metal protective layer having a high affinity for oxygen and acting as a sacrificial target for oxygen during a reflow of the aluminum-alloy layer.

Abstract: An improved and new method for forming stacked polysilicon contacts for use in multilevel conducting interconnection wiring in semiconductor integrated circuits has been developed. The polysilicon contacts are self-aligned between wiring levels and the fabrication process results in a substantially planar top insulating layer surface.

Abstract: A method for formation of a wiring layer in a semiconductor device, which includes the steps of: forming a first conductive layer upon a substrate; forming a second conductive layer on the first conductive layer, the second conductive layer having a melting point lower than that of the first conductive layer; and melting (or flowing) the second conductive layer. The first conductive layer is composed of aluminum or an aluminum alloy, and the impurity may be Si or Cu, while the second conductive layer has a melting point lower than that of the first conductive layer by 10.degree. C. or more.

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free.

Abstract: A method and apparatus for tuning a process recipe to target specific dopant concentrations in a doped layer. The present invention controls the process tuning based on predetermined and easily updatable trend curves for that process. The present invention simplifies the tuning process, shortens the time required to tune the process recipe, and is independent of any personal experience, thereby reducing reliance on the variable skills and experience level of any individual equipment support engineer. The present invention uses a computer program based on process characterization to replace the traditional manual tuning approach. Further, the present invention iteratively corrects for process drift and makes possible efficient tuning of dopant concentration levels in the deposited doped film. Other embodiments of the present method and apparatus provide for storage of the tuning history so as to allow incorporation of the history in order to account for the dopant flow drift.

Abstract: A method of improving the planarity of spin-on glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces on a trace layer of a semiconductor wafer that exceed a predetermined threshold distance are provided with dummy surfaces arranged in a micro-pattern in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined threshold distance is greater than approximately 2 micrometers, as for example in the range of approximately 4.65 to 5 micrometers. In some applications, both the active conductive traces and the dummy surfaces are formed from a metallic material that is deposited in one single step with a dielectric layer being deposited over both the active conductive traces and the dummy surfaces prior to application of the spin-on glass layer.

Abstract: A wiring structure of semiconductor device and a method for manufacturing the same which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole or a via hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plug is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface thereof the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for the semiconductor device of the next generation.

Abstract: A contact hole burying method is provided including the steps of: coating an oxide layer on a substrate and removing the oxide layer except for a portion thereof to form a contact hole extending through the oxide layer in electrical contact with the oxide layer; sequentially forming a metal barrier layer and wet layer on the oxide layer and inside the contact hole to form an electrical connection to the substrate; forming a conductive metal layer on the wet layer; removing impurity ions and oxide material, which remain in the conductive metal layer which decrease mobility of metal atoms on a surface of said conductive layer due to absorption and oxidation, by a cleaning-etching process using a plasma; and reflowing the conductive metal layer at a relatively low temperature in a reactive furnace where the cleaning-etching process is performed to completely fill the contact hole.

Abstract: An object of the present invention is to completely reduce a difference in level in a short time at a convex pattern spreading horizontally on a large scale and obtain a semiconductor device having a planarized surface. An insulating film is formed on a semiconductor substrate to cover a horizontally spreading convex pattern and to fill in a concave portion. A portion of insulating film located on a planarized portion of convex pattern is selectively etched away so as to leave a frame-shaped insulating film having a width of 1-500 .mu.m at least on the outer periphery portion of convex pattern. Insulating film left on semiconductor substrate is etched by chemical/mechanical polishing method, thereby planarizing a surface of the semiconductor substrate.

Abstract: A method of smoothing irregularities in a surface of a semiconductor device using flowable particles which are dispersed onto the surface of the semiconductor device. The irregularities in the surface of the semiconductor device are filled with flowable particles smaller in size than the irregularities which are to be smoothed, and the particles are thereafter heated so that they flow and fill the irregularities, forming a smooth layer of flowable particle material which does not require polishing. The flowable particles may be mixed with non-flowable particles which are encapsulated in the layer of flowable particle material to form a homogeneous layer. The non-flowable particles may be augmentors which modify the properties of the layer. The particles may be dispersed with a spin-on process.

Abstract: A method for forming a metal layer of an ultra-thin film according to metal deposition conditions and a method for forming metal wiring by filling a high aspect-ratio contact hole using cooling step prior to depositing the metal layer. In particular, the additional cooling process is performed before the process of depositing the metal layer and then the deposition process is performed in a state where the temperature of the wafer has been cooled down to a temperature in the range between -25.degree. C. and room temperature. The surface morphology of the deposited metal layer is improved and a continuous ultra-thin film can be obtained. Also, the aluminum filling characteristics in the contact hole having a high aspect-ratio are improved.

Abstract: A method for forming a metal layer including the steps of heat treating a semiconductor substrate for a predetermined time at an intermediate temperature between 200.degree. C. and 400.degree. C., then depositing the metal layer on the semiconductor substrate at a temperature below 200.degree. C., in a vacuum, then thermally treating the metal layer at a temperature between 0.6 Tm-1.0 Tm (where Tm is the melting point of the metal layer), without breaking the vacuum, thereby reflowing the grains of the metal layer, and then gradually cooling the metal layer. Alternatively, the intermediate heat-treatment step can be performed after the metal layer is thermally treated, in which case, the metal layer should thereafter be rapidly cooled.

Abstract: An improved method for forming a planar borophosphosilicate glass (BPSG) insulating layer having a reduced thermal budget was achieved. The method involves forming a multilayer BPSG comprised of four layers with different boron and phosphorus concentrations in each layer. The first layer deposited has the conventional doping range, and therefore would require higher reflow temperatures for leveling. By the method of this invention, a second low-doped BPSG buffer layer is deposited and then a heavily doped third BPSG layer is deposited having a lower reflow temperature, and therefore is planarized at a lower temperature. A low-doped fourth cap BPSG layer is used over the third BPSG layer to minimize moisture absorption and unstable crystal formation prior to the reflow anneal.