Having Planarization Step Patents (Class 438/645)
  • Patent number: 9406560
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: August 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9312203
    Abstract: A dual damascene structure with an embedded liner and methods of manufacture are disclosed. The method includes forming a dual damascene structure in a substrate. The method further includes reflowing a seed layer such that material of the seed layer flows into a via of the dual damascene structure. The method further includes forming a liner material on the material over or within the via of the dual damascene structure. The method further includes filling any remaining portions of the via and a trench of the dual damascene structure with additional material.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: April 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Baozhen Li, Chih-Chao Yang
  • Patent number: 9209299
    Abstract: A transistor and a fabrication method are provided. In an exemplary transistor, a gate structure is formed on a surface of the substrate. A first doped region is formed in the substrate on both sides of the gate structure. An opening is formed in the first doped region. A stress layer is formed in the opening of the first doped region on the both sides of the gate structure. The stress layer has a thickness in the substrate less than a depth of the first doped region. The first doped region has a bottom in the substrate surrounding a bottom of the stress layer. The stress layer further contains a second doped region. The second doped region and the first doped region form a source region or a drain region.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 8, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Meng Zhao
  • Patent number: 8951900
    Abstract: The present disclosure is directed to, among other things, an illustrative method that includes forming an opening in a dielectric material of a contact level of a semiconductor device, and selectively depositing a conductive material in the opening to form a contact element therein, the contact element extending to a contact area of a circuit element and having a laterally restricted excess portion formed outside of the opening and above the dielectric material. The disclosed method further includes forming a sacrificial material layer above the dielectric material and the contact element, the sacrificial material layer surrounding the laterally restricted excess portion. Additionally, the method includes planarizing a surface topography of the contact level in the presence of the sacrificial material so as to remove the laterally restricted excess portion from above the dielectric material.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Axel Preusse, Norbert Schroeder, Uwe Stoeckgen
  • Patent number: 8921229
    Abstract: A method of polishing copper wiring surfaces of in ultra large scale integrated circuit, the method including: a) preparing a polishing solution including between 35 and 80 w. % of a nano SiO2 abrasive, between 12 and 60 w. % of deionized water, between 1 and 3 w. % of an oxidant, between 1 and 4 w. % of an active agent, and between 0.5 and 1.5 w. % of a chelating agent; and b) polishing using the polishing solution under following conditions: between 2 and 5 kPa pressure; between 20 and 50° C.; between 120 and 250 mL/min slurry flow rate; and at between 30 and 60 rpm/min rotational speed.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: December 30, 2014
    Inventors: Yuling Liu, Xiaoyan Liu, Jun Tian
  • Patent number: 8889544
    Abstract: The disclosure provides mechanisms of performing metal chemical-mechanical polishing (CMP) without significant loss of copper and a dielectric film of damascene structures. The mechanisms use a metal CMP stop layer made of a low-k dielectric film with a porogen, which significantly reduces the removal rate of the metal CMP stop layer by metal CMP. The metal CMP stop layer is converted into a porous low-k dielectric film after a cure (or curing) to remove or convert the porogen. The low-k value, such as equal to or less than about 2.6, of the metal CMP stop layer makes the impact of using of the metal CMP stop layer on RC delay from minimum to none. Further the CMP stop layer protects the porous low-k dielectric film underneath from exposure to water, organic compounds, and mobile ions in the CMP slurry.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsu Wu, Hsin-Hsien Lu, Tien-I Bao, Shau-Lin Shue
  • Patent number: 8883654
    Abstract: The present arrangement provides a method of treating an oxidized layer of metal nitride, including oxidizing a layer (2) of metal oxide at the surface of a first layer (1) of nitride of said metal using a plasma of an oxidizing species with an oxidation number that is greater than that of oxygen in order to form a metallic layer (3) of a compound based on said metal; and reducing the metallic layer (3) formed in step i) using a plasma of hydrogen and nitrogen to form a second layer (4) of nitride of said metal.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: November 11, 2014
    Assignee: Altis Semiconductor
    Inventors: Michel Aube, Pierre De Person
  • Patent number: 8865600
    Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. Accordingly, first patterned second hard mask (HM) region is patterned, thus forming the line end space structure associated with an end-to-end space.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 8865013
    Abstract: A method for chemical mechanical polishing of a substrate comprising tungsten using a nonselective chemical mechanical polishing composition.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: October 21, 2014
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Yi Guo, Jerry Lee, Raymond L. Lavoie, Jr., Guangyun Zhang
  • Patent number: 8828246
    Abstract: A new and novel method utilizing current nano-technological processes for fabricating a range of micro-devices with significantly expanded capabilities, unique functionalities at microscopic levels, enhanced degree of flexibilities, reduced costs and improved performance in the fields of bioscience and medicine is disclosed in the within patent application. Micro-devices fabricated using the disclosed nano-technological techniques have significant improvements in many areas over the existing, conventional methods. Such improvements include, but are not limited to reduced overall costs, early disease detection, targeted drug delivery, targeted disease treatment and reduced degree of invasiveness in treatment. Compared with existing, conventional approaches, the said inventive approach disclosed in this patent application is much more microscopic, sensitive, accurate, precise, flexible and effective.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: September 9, 2014
    Assignee: Anpac Bio-Medical Science Co., Ltd.
    Inventor: Chris Yu
  • Patent number: 8772154
    Abstract: Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer dielectric (“ILD”) layer over a semiconductor device, depositing a barrier polish stop layer over the ILD layer, and patterning at least the barrier polish stop layer and the ILD layer to create a plurality of etch features therein. Copper is plated over the barrier polish stop layer and into the plurality of etch features to produce a copper overburden overlying the barrier polish stop layer and a plurality of conductive interconnect features in the ILD layer and barrier polish stop layer. The integrated circuit is polished to remove the copper overburden and expose the barrier polish stop layer.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 8, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Egon Ronny Pfützner, Carsten Peters, Jens Heinrich
  • Patent number: 8759218
    Abstract: A chemical mechanical polishing process includes placing a substrate on a first polishing pad of a first platen, wherein the substrate has a bulk metal layer and a barrier layer; polishing the bulk metal layer by using the first polishing pad having a hardness of above 50 (Shore D) until the barrier layer is exposed; polishing the barrier layer on a second polishing pad of a second platen after removing the bulk metal layer, wherein the second polishing pad has a hardness ranging between 40 and 50 (Shore D) and includes an upper layer and a lower backing layer and the upper layer has a hardness less than 50 (Shore D).
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 24, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Boon-Tiong Neo, Chin-Kun Lin, Lee-Lee Lau
  • Patent number: 8728932
    Abstract: A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8703612
    Abstract: A method includes forming an etch stop layer over and contacting a gate electrode of a transistor, forming a sacrificial layer over the etch stop layer, and etching the sacrificial layer, the etch stop layer, and an inter-layer dielectric layer to form an opening. The opening is then filled with a metallic material. The sacrificial layer and excess portions of the metallic material over a top surface of the etch stop layer are removed using a removal step including a CMP process. The remaining portion of the metallic material forms a contact plug.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shich-Chang Suen, Liang-Guang Chen, He Hui Peng, Wne-Pin Peng, Shwang-Ming Jeng
  • Patent number: 8685853
    Abstract: A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection. The novel method for creating a dual damascene structure allows for a smaller number of processing steps, thus reducing the processing time needed to complete the dual damascene structure. In addition, a lower number of masks may be needed. The exemplary mask or reticle used within the process incorporates different regions possessing different transmission rates. During the exposing step, light from an exposing source passes through the mask to expose a portion of the photoresist layer on top of the wafer.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Fan Chung Tseng, Chi Hsi Wu, Wei Ting Chien
  • Patent number: 8673772
    Abstract: A method of forming a biosensor chip enables a bond pad and detector electrode to be formed of different materials (one is formed of a connection layer such as copper and the other is formed of a diffusion barrier layer such as tantalum or tantalum nitride). A single planarizing operation is used for both the bond pad and the detector electrode. By using the same processing, resist patterning on an already-planarized surface is avoided, and the cleanliness of both the bond pad and detector electrode is ensured. Self-aligned nanoelectrodes and bond pads are obtained.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: March 18, 2014
    Assignee: NXP B.V.
    Inventor: Frans Widdershoven
  • Patent number: 8664766
    Abstract: An interconnect structure including a gouging feature at the bottom of one of the via openings. The structure includes an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein. The conductively filled via is in contact with an exposed surface of the at least one conductive feature of a first interconnect level by an anchoring area. The conductively filled via is separated from the second dielectric material by a first diffusion barrier layer, and the conductively filled line is separated from the second dielectric material by a second continuous diffusion barrier layer thereby the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Terry A. Spooner, Oscar van der Straten
  • Patent number: 8580687
    Abstract: One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 12, 2013
    Assignee: Infineon Technologies AG
    Inventors: Gerald Dallmann, Dirk Meinhold, Alfred Vater
  • Patent number: 8541300
    Abstract: A plurality of projections, respectively given later as cores of a plurality of external connection terminals, are formed first by selectively forming a curable resin layer over a protective insulating film; flat portions are then formed respectively on the top surfaces of the plurality of projections, by pressing a molding jig having a flat opposing surface onto the top surfaces of the plurality of projections, before the projections are cured; the plurality of projections are cured; and the plurality of external connection terminals, and the plurality of interconnects are formed, by selectively forming an electro-conductive film over the plurality of projections, the protective insulating film, and the plurality of electrode pads.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: September 24, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Fumihiro Bekku
  • Patent number: 8491807
    Abstract: An abrasive liquid for a metal comprising (1) an oxidizing agent for a metal, (2) a dissolving agent for an oxidized metal, (3) a first protecting film-forming agent such as an amino acid or an azole which adsorbs physically on the surface of the metal and/or forms a chemical bond, to thereby form a protecting film, (4) a second protecting film-forming agent such as polyacrylic acid, polyamido acid or a salt thereof which assists the first protecting film-forming agent in forming a protecting film and (5) water; and a method for polishing.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: July 23, 2013
    Assignees: Hitachi Chemical Company, Ltd., Hitachi, Ltd.
    Inventors: Takeshi Uchida, Jun Matsuzawa, Tetsuya Hoshino, Yasuo Kamigata, Hiroki Terazaki, Yoshio Honma, Seiichi Kondoh
  • Patent number: 8461040
    Abstract: A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: June 11, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Rodney S. Ridley, Nathan Lawrence Kraft
  • Patent number: 8455350
    Abstract: A method for manufacturing an integrated circuit system that includes: forming a substrate with an active region; depositing a material over the substrate to act as an etch stop and define a source and a drain; depositing a first dielectric over the substrate; processing the first dielectric to form features within the first dielectric including a shield; and depositing fill within the features to electrically connect the shield to the source of the active region by a single process step.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: June 4, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Xavier Seah Teo Leng
  • Patent number: 8450197
    Abstract: Contact elements in the contact level of a semiconductor device may be formed on the basis of a selective deposition technique, such as electroless plating, wherein an efficient planarization of the contact level is achieved without subjecting the contact elements to undue mechanical stress. In some illustrative embodiments, an overfilling of the contact openings may be reliably avoided and the planarization of the surface topography is accomplished on the basis of a non-critical polishing process. In other cases, electrochemical etch techniques are applied in combination with a conductive sacrificial current distribution layer in order to remove any excess material of the contact elements without inducing undue mechanical stress.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: May 28, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Axel Preusse, Norbert Schroeder, Uwe Stoeckgen
  • Patent number: 8435885
    Abstract: Analysis of chemical and physical characteristics of polymer species and etch residues caused in critical plasma-assisted etch processes for patterning material layers in semiconductor devices may be accomplished by removing at least a portion of these species on the basis of a probing material layer, which may be lifted-off from the patterned surface. The probing material layer may substantially suppress a chemical modification of the species of interest and may thus allow the examination of the initial status of these species.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: May 7, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Dmytro Chumakov, Petra Hetzer, Matthias Schaller
  • Patent number: 8373070
    Abstract: Disclosed is a metal structure of a multi-layer substrate, comprising a first metal layer and a dielectric layer. The first metal layer has an embedded base and a main body positioned on the embedded base. The base area of the embedded base is larger than the base area of the main body. After the dielectric layer covers the main body and the embedded base, the dielectric layer is opened at the specific position of the first metal layer for connecting the first metal layer with a second metal layer above the dielectric layer. When the metal structure is employed as a pad or a metal line of the flexible multi-layer substrate according to the present invention, the metal structure cannot easily be delaminated or separated from the contacted dielectric layer. Therefore, a higher reliability for the flexible multi-layer substrate can be achieved.
    Type: Grant
    Filed: July 4, 2010
    Date of Patent: February 12, 2013
    Assignee: Princo Middle East FZE
    Inventor: Chih-Kuang Yang
  • Patent number: 8361832
    Abstract: A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: January 29, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8349729
    Abstract: Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: January 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Karl W. Barth, Ricardo A. Donaton, Spyridon Galis, Kevin S. Petrarca, Shahab Siddiqui
  • Patent number: 8349731
    Abstract: Embodiments of methods for forming Cu diffusion barriers for semiconductor interconnect structures are provided. The method includes oxidizing an exposed outer portion of a copper line that is disposed along a dielectric substrate to form a copper oxide layer. An oxide reducing metal is deposited onto the copper oxide layer. The copper oxide layer is reduced with at least a portion of the oxide reducing metal that oxidizes to form a metal oxide barrier layer. A dielectric cap is deposited over the metal oxide barrier layer.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: January 8, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Errol Todd Ryan
  • Patent number: 8212359
    Abstract: A semiconductor integrated circuit device can be mounted on a circuit board through capacitive coupling even when being miniaturized. A passivation film disposed on a principal surface of a semiconductor substrate provided with a plurality of wirings laminated sequentially with insulating films therebetween has an opening at which at least a portion of the uppermost layer wiring is exposed. An electrode is arranged to cover the uppermost layer wiring exposed at the opening of the passivation film and the periphery of the opening of the passivation film. A dielectric layer is arranged to cover the electrode. An extension portion of the electrode on the surface of the passivation film and an electrode of a circuit board are capacitively coupled with a dielectric layer therebetween.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: July 3, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yuki Ito
  • Patent number: 8188380
    Abstract: A printed wiring board and a method for manufacturing the same are provided. The printed wiring board includes a resin insulation layer having a first surface and a second surface opposite the first surface, and includes an opening for a first via conductor. An electronic-component mounting pad is formed on the first surface of the resin insulation layer. The electronic-component mounting pad includes a portion embedded in the resin insulation layer and a portion protruding from the resin insulation layer. The protruding portion covers the embedded portion and a portion of the first surface of the resin insulation layer that surrounds the embedded portion. A first conductive circuit is formed on the second surface of the resin insulation layer. A first via conductor is formed in the opening of the resin insulation layer and connects the electronic-component mounting pad and the first conductive circuit.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: May 29, 2012
    Assignee: IBIDEN Co., Ltd.
    Inventors: Satoru Kawai, Kenji Sakai, Liyi Chen
  • Patent number: 8129278
    Abstract: A copper/barrier CMP process includes (a) providing a substrate having a bulk metal layer and a barrier layer; (b) polishing the substrate with a first hard polishing pad on a first platen to substantially remove an upper portion of the bulk metal layer, wherein the first hard polishing pad has a hardness of above 50 (Shore D); (c) polishing the substrate with a second hard polishing pad on a second platen to remove residual copper, thereby exposing the barrier layer, wherein the second hard polishing pad has a hardness of above 50 (Shore D); and (d) polishing the substrate with a third hard polishing pad on a third platen to remove the barrier layer, wherein the third hard polishing pad has a hardness ranging between 40-50 (Shore D).
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: March 6, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Boon-Tiong Neo, Chin-Kun Lin, Lee-Lee Lau
  • Patent number: 8105942
    Abstract: An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: January 31, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jihong Choi, Tibor Bolom
  • Patent number: 8097526
    Abstract: Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: January 17, 2012
    Assignee: CrossFire Technologies, Inc.
    Inventors: Kevin Atkinson, Clifford H. Boler
  • Patent number: 8053357
    Abstract: A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG layer prior to patterning and etching the latter to form the via hole and (for a dual damascene structure) the trench. After over-filling with copper, the structure is planarized using CMP. The USG layer acts both to prevent any fluorine from the FSG layer from reaching the copper and as an end-point detector during CMP. In this way defects that result from copper-fluorine interaction do not form and precise planarization is achieved.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: November 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Shau-Lin Shue
  • Patent number: 8043963
    Abstract: A method for manufacturing a semiconductor device that improves the reliability of a metal cap layer and productivity. The method includes an insulation layer step of superimposing an insulation layer (11) on a semiconductor substrate (2) including an element region (2b), a recess step of forming a recess (12) in the insulation layer (11), a metal layer step of embedding a metal layer (13) in the recess (12), a planarization step of planarizing a surface of the insulation layer (11) and a surface of the metal layer (13) to be substantially flush with each other, and a metal cap layer step of forming a metal cap layer (16) containing at least zirconium element and nitrogen element on the surface of the insulation layer (11) and the surface of the metal layer (13) after the planarization step.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: October 25, 2011
    Assignee: Ulvac, Inc.
    Inventors: Masanobu Hatanaka, Kanako Tsumagari, Michio Ishikawa
  • Patent number: 8038898
    Abstract: An abrasive liquid for a metal comprising (1) an oxidizing agent for a metal, (2) a dissolving agent for an oxidized metal, (3) a first protecting film-forming agent such as an amino acid or an azole which adsorbs physically on the surface of the metal and/or forms a chemical bond, to thereby form a protecting film, (4) a second protecting film-forming agent such as polyacrylic acid, polyamido acid or a salt thereof which assists the first protecting film-forming agent in forming a protecting film and (5) water; and a method for polishing.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: October 18, 2011
    Assignees: Hitachi Chemical Company, Ltd., Hitachi, Ltd.
    Inventors: Takeshi Uchida, Jun Matsuzawa, Tetsuya Hoshino, Yasuo Kamigata, Hiroki Terazaki, Yoshio Honma, Seiichi Kondoh
  • Patent number: 8030209
    Abstract: During the formation of metallization layers of sophisticated semiconductor devices, the damaging of sensitive dielectric materials, such as ULK materials, may be significantly reduced during a CMP process by applying a compressive stress level. This may be accomplished, in some illustrative embodiments, by forming a compressively stressed cap layer on the ULK material, thereby suppressing the propagation of micro cracks into the ULK material.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 4, 2011
    Assignee: GLOBALFOUNDDRIES Inc.
    Inventors: Thomas Werner, Kai Frohberg, Frank Feustel
  • Patent number: 7989341
    Abstract: A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection. The novel method for creating a dual damascene structure allows for a smaller number of processing steps, thus reducing the processing time needed to complete the dual damascene structure. In addition, a lower number of masks may be needed. The exemplary mask or reticle used within the process incorporates different regions possessing different transmission rates. During the exposing step, light from an exposing source passes through the mask to expose a portion of the photoresist layer on top of the wafer.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: August 2, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Fan Chung Tseng, Chi Hsi Wu, Wei Ting Chien
  • Patent number: 7972956
    Abstract: A wire structure of a semiconductor device capable of ensuring a process margin for bit line patterning in a 6F2 cell layout of a semiconductor device, and a method for manufacturing the same.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: July 5, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chun Soo Kang, Jeon Kyu Lee
  • Patent number: 7968456
    Abstract: A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul S. McLaughlin, Sujatha Sankaran, Theodorus E. Standaert
  • Patent number: 7960277
    Abstract: An electronic device includes a conductive pattern formed on a first insulating film, a second insulating film formed on the conductive pattern and the first insulating film, a hole formed in the second insulating film on the conductive pattern, carbon nanotubes formed in the hole to extend from a surface of the conductive pattern, and a buried film buried in clearances among the carbon nanotubes in the hole.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: June 14, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Mizuhisa Nihei
  • Patent number: 7935625
    Abstract: A method of forming a metal line of a semiconductor memory device is disclosed. An interlayer insulating layer, an etch-stop layer, a trench oxide layer, a hard mask layer and a photoresist layer are laminated over a semiconductor substrate in which a contact is formed. An exposure process is performed to form a photoresist pattern. The hard mask layer is partially etched by an etch process that employs the photoresist pattern. An etch process using the hard mask layer as an etch mask is performed to partially etch the trench oxide layer, the etch-stop layer and the interlayer insulating layer, thereby forming damascene trenches. Metal material is formed on the entire surface including the trenches. A chemical mechanical polishing process is then performed to expose the etch-stop layer, thereby forming a metal line.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: May 3, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young Mo Kim, Sung Min Hwang
  • Patent number: 7928007
    Abstract: In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: April 19, 2011
    Assignee: SanDisk 3D LLC
    Inventor: Christopher J. Petti
  • Patent number: 7915161
    Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: March 29, 2011
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 7910477
    Abstract: Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: March 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jeannette Michelle Jacques, Deepak A. Ramappa
  • Patent number: 7902068
    Abstract: In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: March 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadayoshi Watanabe, Yoshiaki Shimooka, Naofumi Nakamura, Hayato Nasu
  • Patent number: 7897509
    Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: March 1, 2011
    Assignee: Renesas Electronics Corp.
    Inventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa
  • Patent number: 7867870
    Abstract: A device isolation film in a semiconductor device and a method for forming the same are provided. The method includes etching a middle portion of a device isolation film having a deposition structure including a Spin-On-Dielectric (SOD) oxide film and a High Density Plasma (HDP) oxide film to form a hole and filling an upper portion of the hole with an oxide film having poor step coverage characteristics to form a second hole extending along the middle portion of the device isolation film. The second hole serves as a buffer for stress generated at the interface between an oxide film, which can be a device isolation film, and a silicon layer, which can be a semiconductor substrate, thereby increasing the operating current of a transistor and improving the electrical characteristics of the resulting device.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won Bong Jang
  • Patent number: 7846834
    Abstract: A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: December 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Conal E. Murray
  • Patent number: 7842193
    Abstract: According to an aspect of the invention, there is provided a polishing liquid for polishing a barrier metal material on an interlayer insulation material, the polishing liquid having a pH of from 2.0 to 6.0 and including an aqueous solution containing a compound represented by the following formula (1), and polishing particles containing silicon oxide and dispersed in the aqueous solution: R1—(CH2)m—(CHR2)n—COOH (1) wherein m+n?4; R1 represents a hydrogen atom, a methyl group, an ethyl group or a hydroxyl group; R2 represents a methyl group, an ethyl group, a benzene ring or a hydroxyl group; and when a plurality of R2s are present in the formula (1), they are the same or different from one another.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: November 30, 2010
    Assignee: FUJIFILM Corporation
    Inventor: Kenji Takenouchi