Abstract: Method for fabricating a semiconductor device, including the steps of (1) forming a gate insulating film, a silicon layer, and an insulating film on a substrate in succession, (2) selectively removing a portion of the insulating film on which a gate electrode is to be formed, (3) forming first sidewalls at sides of the insulating film having the portion removed therefrom, (4) forming silicide on a surface of the exposed silicon, (5) forming a cap insulating film on the silicide and the first sidewalls, (6) removing the insulating film, and (7) using the cap insulating film as a mask in removing the exposed silicon layer, to form the gate electrode.

Abstract: A method for forming a thermally stable cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the silicon regions to be silicided. A capping layer is deposited overlying the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. A titanium layer is deposited overlying the cobalt monosilicide layer. Thereafter the substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide. The titanium layer provides titanium atoms which diffuse into the cobalt disilicide thereby increasing its thermal stability.

Abstract: A method of fabricating a MOS transistor. A low step coverage PE-oxide layer is formed between a polygate and a gate spacer. As a result of the characteristic of the PE-oxide layer, an overhang is formed on the top corner of the polygate. A gap, which is broad at the top and narrow at the bottom, is then formed therein by removing a portion of the PE-oxide layer. A salicide process is performed to form a metal silicide layer on the exposed surface of the polygate and the source/drain region of the MOS transistor.

Abstract: A method for making a flexible metal silicide local interconnect structure. The method includes forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon layer, removing a portion of the silicon nitride layer, oxidizing the exposed portion of the silicon layer, removing the remaining portion of the silicon nitride layer, optionally removing the oxidized silicon layer, forming a metal layer over the resulting structure, annealing the metal layer in an atmosphere comprising nitrogen, and removing any metal nitride regions. The local metal silicide interconnect structure may overlie the at least one gate structure. The methods better protect underlying silicon regions (e.g., substrate), as well as form TiSix local interconnects with good step coverage. Intermediate and resulting structures are also disclosed.

Abstract: Bridging between nickel silicide layers on a gate electrode and associated source/drain regions along silicon nitride sidewall spacers is prevented by hydrogen passivation of the exposed surfaces of the silicon nitride sidewall spacers. Embodiments include treating the silicon nitride sidewall spacers with a solution of HF and H2O, at a HF:H2O volume ratio of about 100:1 to about 200:1 for up to about 60 seconds at room temperature. Hydrogen passivation reduces the number of silicon dangling bonds, thereby avoiding reaction with subsequently deposited nickel and, hence, avoiding the formation of a bridging film of nickel silicide on the sidewall spacers.

Abstract: Shorting between a transistor gate electrode and associated source/drain regions due to metal silicide formation on the sidewall spacers is prevented by passivating the sidewall spacer surfaces with a solution of iodine and ethanol. Embodiments of the invention include spraying the wafer with or immersing the wafer in, a solution of iodine in ethanol.

Abstract: A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; forming nickel silicide layers disposed on the source/drain regions and the gate electrode, and two etching steps. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The first etch is performed with a sulfuric peroxide mix to remove unreacted nickel, and the second etch is performed with an ammonia peroxide mix to remove nickel silicide formed over the first and second sidewall spacers.

Abstract: There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.

Abstract: A method for fabricating a semiconductor substrate includes forming a silicide layer at a predetermined portion of a semiconductor substrate, implanting two or more impurity ions before annealing, and forming an impurity region in the semiconductor substrate by annealing the silicide layer and by diffusing the impurity ions from the silicide layer into the semiconductor substrate. Accordingly, the present invention can improve reliability and performance of a semiconductor device by reducing dopant loss and leakage current of a PN junction in the substrate and by decreasing a sheet resistance of the silicide layer. The dose of the second implanter ions is about one hundred to one thousand times less than the dose of the first implanted ions.

Abstract: A method of manufacturing a semiconductor device in which a cobalt silicide layer is formed on a semiconductor substrate. In the method, the semiconductor substrate is prepared, and cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature approximately equal to 200 degrees Celsius. Thereafter, cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature between 300 degrees Celsius and 400 degrees Celsius without exposing the semiconductor substrate to the atmosphere. Preferably, the semiconductor substrate is thereafter rapid thermal annealed at a temperature equal to or higher than 500 degrees Celsius in nitrogen atmosphere for a predetermined time. Further, at least a part of cobalt portion or cobalt oxide portion on the semiconductor substrate is removed by wet etching.

Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming the gate structure over the substrate (step 102 of FIG.

Abstract: Capping layer adhesion to a Cu or Cu alloy interconnect member is enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with a hydrogen plasma to substantially reduce oxides thereon, forming a thin layer of copper silicide on the treated surface and depositing the capping layer thereon. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric layer, chemical-mechianiical polishing, hydrogen plasma treatment, reacting the treated surface with silane or dichlorosilane to form a layer of copper silicide on the treated surface and depositing a silicon nitride capping layer on the thin copper silicide layer.

Abstract: A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip during the Si-ion mixing process, an additional vacuum bake step prior to PAI during the PAI process, an additional vacuum bake step prior to pre-metal HF dip during the PAI process.

Abstract: A tungsten gate electrode and method of fabricating the same are provided. In one aspect, a method of fabricating a gate electrode stack on a substrate is provided that includes forming an insulating film on the substrate and forming a conductor film on the insulating film by initially depositing a film of amorphous silicon and amorphous tungsten, and thereafter depositing a film of polycrystalline tungsten on the film and annealing the substrate to react the amorphous silicon with the amorphous tungsten to form tungsten silicide on the insulating film and to increase the grain structure of the polycrystalline tungsten film. The tungsten silicide film and the polycrystalline tungsten film are patterned to define the gate electrode stack. The method enables the seamless fabrication of an adhesion layer and a tungsten gate in a single chamber and without resort to titanium.

Abstract: A gate oxide layer 11 and a poly-silicon layer 12 are formed on a silicon substrate 10. A tungsten silicide (WSi) layer that includes dopant is formed by a sputtering method or CVD as the metal silicide layer. This layer is designated a first wiring pattern layer 13. Subsequently, a gate G is formed by removing the surrounding portion of the gate oxide layer 11, the poly-silicon layer 12 and the first wiring pattern layer 13, and an insulator film 14 is formed by thermal oxidation. Then, a first insulator layer 15 is formed from BPSG, and a contact hole 16 is formed through the first insulator layer 15. After that, a second wiring pattern layer 17 is formed by CVD for covering the first insulator layer 15 as well as the contact hole 16, BPSG is deposited on the second wiring pattern layer 17, and becomes a second insulator layer 18 through thermal treatment. The concentration of the dopant in the first wiring pattern layer 13 equals or is larger than that in the second wiring pattern layer 17.

Abstract: A method for forming uniform ultrathin silicide features in the fabrication of an integrated circuit is described. A metal layer is deposited over the surface of a silicon semiconductor substrate. An array of heated metallic tips contact the metal layer whereby the metal layer is transformed to a metal silicide where it is contacted by the metallic tips and wherein the metal layer not contacted by the metallic tips is unreacted. The unreacted metal layer is removed leaving the metal silicide as uniform ultrathin silicide features. Alternatively, a metal acetate layer is spin-coated over the surface of a silicon semiconductor substrate. An array of heated metallic tips contacts the metal acetate layer whereby the metal acetate layer is transformed to a metal silicide where the metallic tips contact the metal acetate layer and wherein the metal acetate slayer not contacted by the metallic tips is unreacted.

Abstract: A method of fabricating an improved spacer comprising the steps of providing a semiconductor substrate that has a gate already formed thereon. A PNO spacer is formed on a sidewall of the gate. The method of forming the PNO spacer comprises first forming a PNO layer on the conductive layer and the semiconductor, and performing an anisotropic etching step on the PNO layer to form the PNO spacer. The step of forming the PNO layer includes chemical vapor deposition (CVD) using PH3, O2, NH3 and N2 as reagents. The step of etching the PNO layer includes plasma etching using CFX+O2 as plasma source. The material of the PNO spacer is a chemical compound PXNYOZ containing phosphorous (P), nitrogen (N) and oxygen (O) and does not contain silicon. Therefore, the PNO spacer can avoid erosion during etching and does not react with Ti during the Salicide process.

Abstract: A method for forming an integrated circuit device that incorporate both an array of memory cells and an array of logic circuits on a single chip or substrate is disclosed. The substrate has a transfer field effect transistor (FET) with a first gate electrode and a first source/drain region formed in and on a embedded DRAM region of the substrate and has a logic FET with a second gate electrode and a second source/drain region formed in and on a logic circuit region of the substrate. Next, a dielectric layer was deposited over the exposing surface of said transfer FET and above of the logic FET. Moreover, the dielectric layer was polished until upper surface of the first gate electrode and the second gate electrode is exposed. Subsequently, a photoresist layer is formed over the dielectric layer and the first gate electrode. And then the dielectric layer was etched until upper surface of the logic FET is exposed. Next, the photoresist layer was removed.

Abstract: The proposed invention is a salicide process that is used to avoid bridge phenomena.

Abstract: The invention teaches the addition of copper lines, these copper lines to be added to isolated copper lines or to selected copper lines within a collection of copper lines. The invention also teaches the addition of copper end caps to isolated copper lines or to selected copper lines within a collection of copper lines. The invention further teaches the widening of copper lines for isolated copper lines or selected copper lines within a collection of copper lines.

Abstract: Dopant impurities are ion implanted into active areas assigned to field effect transistors, and, thereafter, titanium silicide layers are formed from a titanium layer on the doped regions; when the dopant impurities are ion implanted into the doped regions, photo resist ion-implantation masks prevent a wide inactive area not assigned to any circuit component from the dopant impurities, and a thick titanium silicide is also grown on the wide inactive area; even when the titanium silicide layers are annealed with heat, the thick titanium silicide layer on the wide inactive area is not seriously coagulated, and an inter-level insulating layer is hardly separated from the titanium silicide layer on the wide inactive area.

Abstract: A nitridization process to form a barrier layer on a substrate is described. The nitridization process includes depositing a layer of metal or metal silicide on a surface of the substrate, placing the substrate into a high density, low pressure plasma reactor, introducing into the high density low pressure plasma reactor a gas including nitrogen, and striking a plasma in the high density, low pressure plasma reactor under conditions that promote nitridization of at least a portion of the layer of metal or metal silicide to produce a composition of metal nitride or metal silicon nitride, respectively.

Abstract: A method of forming a semiconductor device includes separating a semiconductor gate body from the outer surface of the substrate by a gate insulator layer, forming a conductive drain region in the outer surface of the substrate and spaced apart from the gate conductor body, and forming a conductive source region in the outer surface of the substrate and spaced apart from the gate conductor body opposite the conductive drain region to define a channel region in the substrate disposed inwardly from the gate body and the gate insulator layer. The method also includes depositing a metal buffer layer over the conductive source region and conductive drain region, depositing a metal layer over the metal buffer layer, and reacting the metal layer and metal buffer layer with the conductive source region and conductive drain region to form respective first and second silicide regions.

Abstract: A process for forming a low resistance, titanium disilicide layer, on regions of a MOSFET device, has been developed. The process features the deposition of a capping, silicon oxide layer, on first phase, high resistance, titanium disilicide regions. The capping, silicon oxide layer, featuring a compressive stress, reduces the risk of titanium disilicide regions, formed with a tensile stress, from adhesion loss, or peeling, from underlying regions of the MOSFET device, such as from the top surface of a narrow width, polysilicon gate structure. In addition the capping silicon oxide layer protects underlying titanium disilicide regions from the ambient used during the anneal cycle used to convert the first phase, high resistance, titanium disilicide region, to the second phase, low resistance, titanium disilicide region.

Abstract: A method of manufacturing a semiconductor device with a silicide electrode is provided which can form a good contact even at a scaled-down pattern. The method includes the steps of: forming an insulated gate structure with side wall spacer on a p-type region of a silicon (Si) substrate; implanting arsenic ions in source/drain regions at a dose less than 5×1015 cm−2; forming a laminated layer of a Co film and a TiN film on the surface of the substrate; heating the substrate to let the Co film react with an underlying Si region for silicidation; and removing the TiN film.

Abstract: A liner material and method of use is disclosed. The method includes depositing a silicon layer into a deep void, such as a via or trench, and physical vapor depositing a cobalt seed layer onto the silicon. A supplemental cobalt layer is electroplated over the seed layer. The structure is then annealed, forming cobalt silicide (CoSix). The layer can be made very thin, facilitating further filling the via with highly conductive metals. Advantageously, the layer is devoid of oxygen and nitrogen, and thus allows low temperature metal reflows in filling the via. The liner material has particular utility in a variety of integrated circuit metallization processes, such as damascene and dual damascene processes.

Abstract: A method for forming a polycide layer wherein the silicide layer is blanket deposited over a polysilicon layer and selectively ion implanted through a mask to form regions of a higher resistivity than the masked regions. The implanted polycide layer is then annealed by RTA and patterned to form the conductors, gate electrodes and interconnects from the low resistivity regions and resistive components of an integrated circuit from the high resistivity regions. The capability of selecting from high and low resistive regions in a single polycide layer permits the design of resistive components with smaller areas than would be permitted if the resistive components were formed of a single low resistivity layer. This extra degree of freedom permits the designer to optimize device density and device performance without compromising either. The procedure utilizes a additional masking step utilizing a block-out mask.

Abstract: A method of depositing metal silicide onto a semiconductor substrate includes a step of depositing, by a CVD process, a first metal silicide layer with silane gas onto the semiconductor substrate. The method also includes a step of thermally treating and chemically cleaning the semiconductor substrate. The method further includes a step of depositing, by the CVD process, a second metal silicide layer with silane gas onto the semiconductor substrate. By this method, cracks in the metal silicide formed on the semiconductor substrate are minimized.

Abstract: A contact is selectively formed in a contact hole in an insulating layer deposited on a silicon substrate. The contact hole exposes a portion of the substrate. The contact is formed by selectively forming a first layer of titanium silicide in the contact hole on the exposed portion of the substrate. A layer of titanium nitride is then selectively formed on the first layer of titanium silicide. A second layer of titanium silicide is thereafter selectively formed on the layer of titanium nitride to form the contact.

Abstract: High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Emdodiments include forming field oxide regions, gates, spacers, and lightly doped implants, and then depositing a layer of oxide on a substrate. The oxide layer is masked to protect portions of the oxide layer located near the gate, where it is desired to have a shallow junction, then etched to expose portions of the intended source/drain regions where the silicided contacts are to be formed. A high-dosage source/drain implant is thereafter carried out to form deep source/drain junctions with the substrate where the oxide layer has been etched away, and to form shallower junctions near the gates, where the implant must travel through the oxide layer before reaching the substrate. A layer of cobalt is thereafter deposited and silicidation is performed to form metal silicide contacts over only the deep source/drain junctions, while the cobalt on the oxide layer (i.e.

Abstract: The present invention is a method of fabricating void-free and volcano-free tungsten plugs. A silicon film was formed over contact hole surfaces for restricting the reflow of a dielectric layer. A titanium film is formed over the silicon layer. By performing a thermal process to the silicon layer and the titanium layer in a nitride-containing environment, the etching damage to the substrate can be recovered and a silicon silicide and a titanium nitride can be formed. The contact resistance of plugs can be significantly reduced, when compared with known technology. The undesired formation of voids and volcano can be eliminated. The method can be employed to fabricate defect-free advanced ULSI devices.

Abstract: A method of fabricating a semiconductor device includes the steps of providing a semiconductor chip (10) with a memory area (22) and a logic area (26). The memory area (22) and the logic area (26) each have gate structures (50) formed therein. The step of sequentially forming silicided junctions (44) in the logic area (26) and implanted junctions in the memory area (26) is also included.

Abstract: A fabrication method of a semiconductor device is provided, which makes it possible to form a thin and elongated refractory-metal silicide layer while preventing the overgrowth phenomenon. This method is comprised of the steps (a) to (c). In the step (a), a first refractory metal film is formed on a silicon region. In the step (b), a second refractory metal film is formed on the first refractory metal film. The second refractory metal film contains a same refractory metal as the first refractory metal film and nitrogen. A stress of the second refractory metal film is controlled to be a specific value or lower. In the step (c), the first refractory metal film and the second refractory metal film are heat-treated in an atmosphere excluding nitrogen, thereby forming a refractory-metal silicide layer at an interface between the silicon region and the first refractory metal film due to silicidation reaction of the first refractory metal film with the silicon region.

Abstract: A method for use in the fabrication of semiconductor devices includes forming a layer of nitridated cobalt on a surface including silicon. A film cap including titanium is formed over the layer of cobalt and a thermal treatment is performed to form cobalt silicide from the layer of cobalt and the silicon. Further, a layer of cobalt or nickel may be formed over a titanium film on a surface including silicon. The titanium film is formed in an atmosphere including at least one of nitrogen and oxygen and a thermal treatment is performed for reversal and silicidation of the titanium film and the layer of cobalt or nickel to form cobalt silicide or cobalt nickel. The methods may be used for silicidation of a contact area, in forming a polycide line, or in use for other metal silicidation applications.

Abstract: A doped oxide and an undoped oxide are formed on a substrate. Then, the substrate is annealed to re-flow the doped oxide layer. The doped oxide is then etched back. Next, a contact hole is created by etching. An amorphous silicon layer is formed on the surface of the doped oxide layer and along the surface of the contact hole. Next, high temperature is used to recover the etching damage and simultaneously transform or convert the amorphous silicon into a polysilicon layer. A titanium layer and a titanium nitride are respectively formed onto the polysilicon layer. Next, rapid thermal process (RTP) is introduced to form a titanium silicide beneath the titanium nitride layer. A tungsten layer is formed on the titanium nitride layer and refilled into the contact hole. The tungsten layer is then etched back to form a tungsten plug with void-free in the contact hole. A conductive layer is formed on the titanium nitride layer.

Abstract: A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film.

Abstract: A new process for creating a transistor in an integrated circuit provides for two suicide formations, each independent of the other, from two metal depositions and formations steps. The process produces a sufficiently low resistance silicide layer over the source/drain region surfaces of the transistor while also creating a lower resistance silicide over the gate interconnects. In an example embodiment of the invention a near-planar isolation process is used applied such that the gate interconnect surfaces are co-planar. A first silicide layer is formed over the source/drain regions. A dielectric gap-fill material is applied. A planarization method such as chemical mechanical polishing is used to remove the gap fill material down to the top surface of the gate interconnect. A relatively thick suicide is then formed over the top surface of the gate interconnect.

Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

Abstract: A semiconductor process in which a local interconnect, formed above a first transistor level, is connected to the first transistor level through a self-aligned and low resistivity contact structure. A semiconductor substrate is provided and a first transistor level formed on an upper surface of the semiconductor substrate. The first transistor level includes a first transistor. A local interconnect is then formed over the first transistor level. The local interconnect is vertically displaced above the first transistor level such that the local interconnect may traverse a gate of the first transistor without contacting the gate. A contact structure is then formed to connect the first source/drain structure of the first transistor with the local interconnect.

Abstract: Method of fabricating a narrow linewidth transistor having a low sheet resistance. The transistor may be fabricated in a surface of a semiconductor layer (12). A gate body (14) may be formed separated from an outer surface (16) of the semiconductor layer (12) by a gate insulator (18). The gate body (14) may have an inner surface (20) proximate to the semiconductor layer (12) and an opposite outer surface (22). An insulator layer (30) may be deposited outwardly of the semiconductor layer (12) and the gate body (14). The insulator layer (30) may be anisotropically etched to form side walls (32) adjacent to the gate body (14). The anisotropic etch may cause a residual layer of contaminants (34) to form on the outer surface (16) of the semiconductor layer (12) and on the outer surface (22) of the gate body (14). A protective layer (50) may be deposited outwardly of the residual layer of contaminants (34). Dopants may be implanted into the semiconductor layer (12) proximate to the side walls (32).

Abstract: After formation of a connection hole or before deposition of an insulator film, a semiconductor device is placed onto a cathode of a plasma generator. A surface of a metal silicide film such as a silicide of titanium is exposed to a plasma of a nitrogen-containing gas at 550 degrees centigrade or less. As a result of such processing, a barrier compound layer, composed of a compound of nitrogen, oxygen, metal and silicon, is formed at a near-surface region of the metal silicide film of the titanium silicide film. Thereafter, while forming a buried layer from material superior in step coverage such as an Al--Ti compound and an aluminum alloy, reaction between the metal silicide film and the buried layer in a later annealing treatment can be avoided without depositing a barrier metal such as a titanium nitride/nitride film in the connection hole. Accordingly, contact resistance, sheet resistance and junction leakage can be reduced and reliability can be improved.

Abstract: The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.

Abstract: Disclosed is a method for forming a silicide film on bit lines or word lines in a semiconductor device. The method includes the steps of: placing a substrate within a reacting chamber, the substrate having an objective layer on which a metal silicide film is to be formed; and supplying a first source gas for silicon component of the metal silicide and a second source gas for metal component of the metal silicide into the reacting chamber with maintaining a flow rate of the first source gas and with varying a flow rate of the second source gas, wherein the first and second source gases are discretely supplied into the reacting chamber, a reacting zone of the reacting chamber being maintained at a constant temperature range for a selected time.

Abstract: Titanium is deposited onto a semiconductor interconnect to form a salicide structure by plasma-enhanced chemical vapor deposition. The reactant gases, including titanium tetrachloride, hydrogen and optionally argon, are combined. A plasma is created using RF energy and the plasma contacts the rotating semiconductor material. This causes titanium to be deposited which reacts with exposed silicon to form titanium silicide without any subsequent anneal. Other titanium deposited on the surface, as well as titanium-rich silicon compositions (TiSi.sub.X wherein X is <2), are removed by chemical etching. If only about 40 .ANG. of titanium is deposited, it will selectively deposit onto the silicon structure without coating the oxide spacers of the interconnect. In this embodiment the need to chemically etch the substrate is eliminated.

Abstract: A method of reducing the loss of metal silicide in pre-metal etching which includes the following steps. A polysilicon gate electrode and implanted source/drain electrodes are formed on a silicon substrate. A metal silicide layer is formed on the polysilicon gate electrode and the source/drain electrodes. On the surface of the substrate, the polysilicon gate electrode, the source-drain electrodes region and the metal silicide layer, a protecting glass for insulation is formed and then dry etched to form a contact window. The metal silicide layer will form a damaged metal silicide layer in the contact window. Thereafter, a thermal process is conducted to repair the damaged metal silicide layer and finally, pre-metal etching is conducted completing the process. Pursuant to this method, the extremely low resistance of the metal silicide remains.

Abstract: A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.

Abstract: The present invention includes forming gate structures having a nitride cap on the substrate. An ion implantation is used to dope ions into the substrate to form the lightly doped drain (LDD) structures. An oxide layer is formed on the gate structures. Subsequently, the oxide layer is etched back to form oxide spacers on the side walls of the gate structures. Next, an ion implantation with a high dose is carried out to dope nitrogen ions into the oxide spacers, the cap silicon nitride and the silicon substrate. The cap silicon nitride layer is then removed. Then, a refractory or noble metal layer is sputtered on the substrate, nitride doped oxide spacers and the gates. A first step thermal process is performed to form SALICIDE and polycide. Next, an ion implantation is utilized to dope ions into the SALICIDE and polycide films. A second step thermal process is employed to form shallow source and drain junction.

Abstract: Semiconductor devices may be made by forming a silicided layer on a silicon material such as that used to form the extractor of a field emission display. The silicided layer may be self-aligned with the emitter of a field emission display. If the silicided layer is treated at a temperature above 1000.degree. C. by exposure to a nitrogen source, the silicide is resistant to subsequent chemical attack such as that involved in a buffered oxide etching process.

Abstract: A technology of forming a semiconductor integrated device is disclosed. According to the technology, titanium silicide is formed from an interaction between a source of TiCl.sub.2 transformed from TiCl.sub.4, and a source of hydrogen containing gas. The silicide layer includes a relatively planar interface with the gate electrode, the relatively planar interface being substantially free from gouges formed by a redistribution of a portion of the silicon atoms in the gate electrode.

Abstract: In a method of manufacturing a semiconductor device, a silicide layer of a refractory metal is formed in a predetermined region of a semiconductor element formed on a silicon semiconductor substrate. In the first film formation step, a first thin film consisting of the refractory metal is formed on the surfaces of the silicon semiconductor substrate and the semiconductor element. In the first heat treatment step, a heat treatment is performed with respect to the silicon semiconductor substrate, the semiconductor element, and the first thin film to form a silicide layer. In the first removal step, the first thin film is removed by etching. In the second film formation step, a second thin film consisting of a refractory metal of the same kind as that of the first thin film is formed.