Silicide Patents (Class 438/651)
  • Patent number: 5840626
    Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first metal film including a first metal on a surface of a silicon film by sputtering using a gas mixture added with a nitrogen gas, the first metal being one of nickel and cobalt, and causing thermal reaction of the silicon film with the first metal film to form a silicide film of the first metal.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: November 24, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuya Ohguro
  • Patent number: 5824600
    Abstract: A method for forming a silicide layer in a semiconductor device, including the steps of: forming a refractory metal layer on a semiconductor substrate; forming a cobalt layer on the refractory metal layer; implanting impurities in the interface between the refractory metal layer and the cobalt layer; heat treating the semiconductor substrate such that cobalt atoms from the cobalt layer pass through the refractory metal layer and form a cobalt silicide epitaxy layer on the semiconductor substrate; and removing the remaining cobalt layer and the remaining refractory metal layer.
    Type: Grant
    Filed: September 6, 1995
    Date of Patent: October 20, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventors: Jeong Soo Byun, Hyung Jun Kim
  • Patent number: 5783486
    Abstract: A method of forming a transistor having silicide contacts to the gate and source/drain regions. A semiconductor substrate is provided having spaced field oxide regions and active areas. On the active areas, a gate structure is formed having a gate oxide, gate, and gate insulating layer. In an important step, the gate 18 is laterally etched to remove a first width of the gate. A second dielectric layer 22 composed of oxide is deposited over the sidewalls of the gate, the gate 18 and the substrate 10. The second dielectric layer 22 is etched forming sidewall spacers 24 on the sidewalls of the gate 18, the gate insulating layer 20, and the gate oxide layer. The gate insulating layer 20 is then removed with a selective etch. A metal layer 30 is deposited over the resulting surface. The metal layer 30 is heat treated forming a gate silicide contact 36 on the gate 18 and source and drain silicide contacts 34 on the active areas.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: July 21, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Horng-Huei Tseng
  • Patent number: 5753557
    Abstract: A method of forming a transistor having silicide contacts to shallow gate, source and drain regions 18 in a substrate 10 is disclosed. The transistor has an extended sidewall spacer that covers an outer top portion of the gate. The extended sidewall spacers of the invention extend the distance (leakage path) between the gate and the source/drain thereby reducing the leakage current. The transistor is provided having a gate electrode 12,14,16 and spaced lightly doped source and drain regions 18. A key part of the invention is that the gate insulating layer 16 is laterally etched forming a gate cap insulating layer 16A which only covers an inner central portion of the gate 14. Next, a dielectric layer 20 is formed over the lightly doped source and drain regions 18 and the gate electrode 12,14,16A . The dielectric layer 20 is then anisotropically etched forming extended sidewall spacers 20A which cover the outer top portion of the gate 14.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: May 19, 1998
    Assignee: Vanguard International Semiconductor Company
    Inventor: Horng-Huei Tseng
  • Patent number: 5736461
    Abstract: A method of forming cobalt silicide on source/drain regions and polysilicon gate areas of an MOS integrated circuit uses an improved technique to prevent unwanted oxidation of cobalt or growth of silicide on other areas of device. A thin titanium nitride (or titanium tungsten) film is deposited on top of a cobalt film following the steps of patterning the polysilicon gate, source/drain implant and sidewall oxide spacer deposition and etch. The titanium nitride film allows formation of defect-free cobalt silicide during an elevated-temperature anneal. Without the titanium nitride film, the cobalt is likely to oxidize and/or form cobalt silicide in unwanted regions of the device, which can cause device failure.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: April 7, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Antonio Carlo Berti, Stephen Philip Baranowski