Having Noble Group Metal (i.e., Silver (ag), Gold (au), Platinum (pt), Palladium (pd), Rhodium (rh), Ruthenium (ru), Iridium (ir), Osmium (os), Or Alloy Thereof) Patents (Class 438/650)
  • Patent number: 9685608
    Abstract: Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: June 20, 2017
    Assignee: CROSSBAR, INC.
    Inventors: Steven Patrick Maxwell, Sung Hyun Jo
  • Patent number: 9587307
    Abstract: The invention relates generally to processes for enhancing the deposition of noble metal thin films on a substrate by atomic layer deposition. Treatment with gaseous halides or metalorganic compounds reduces the incubation time for deposition of noble metals on particular surfaces. The methods may be utilized to facilitate selective deposition. For example, selective deposition of noble metals on high-k materials relative to insulators can be enhanced by pretreatment with halide reactants. In addition, halide treatment can be used to avoid deposition on the quartz walls of the reaction chamber.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: March 7, 2017
    Assignee: ASM INTERNATIONAL N.V.
    Inventors: Suvi P. Haukka, Marko J. Tuominen, Antti Rahtu
  • Patent number: 9214467
    Abstract: A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: December 15, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin-Hyock Kim, Seung-Jin Yeom, Ki-Seon Park, Han-Sang Song, Deok-Sin Kil, Jae-Sung Roh
  • Patent number: 9048296
    Abstract: Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Fenton Read McFeely, Chih-Chao Yang
  • Patent number: 9018092
    Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Patent number: 8987910
    Abstract: The present invention relates to a method of bonding a copper wire to a substrate, particularly a printed circuit board and an IC-substrate, possessing a layer assembly comprising a copper bonding portion and a palladium or palladium alloy layer and a substrate having a copper wire bonded to aforementioned layer assembly.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: March 24, 2015
    Assignee: Atotech Deutschland GmbH
    Inventors: Mustafa Özkök, Gustavo Ramos, Arnd Kilian
  • Publication number: 20150037973
    Abstract: A method of forming a capping layer over copper containing contacts in a dielectric layer with a liner comprising a noble metal liner around the copper containing contacts is provided. An electroless deposition is provided to deposit a deposition comprising copper on the noble metal liner and the copper containing contacts. A capping layer is formed over the deposition comprising copper.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Inventors: Dries DICTUS, Artur KOLICS
  • Patent number: 8933543
    Abstract: A nitride-based semiconductor device of the present invention includes: a nitride-based semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5°; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x?0, y?0, and z?0) layer 26. The electrode 30 includes a Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: January 13, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Toshiya Yokogawa, Mitsuaki Oya, Atsushi Yamada, Akihiro Isozaki
  • Patent number: 8927433
    Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: January 6, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Jin-Yeong Kang
  • Patent number: 8889546
    Abstract: A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu, Surbhi Mittal
  • Patent number: 8865556
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8841212
    Abstract: A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takeshi Nogami, Thomas M. Shaw, Andrew H. Simon, Jean E. Wynne, Chih-Chao Yang
  • Patent number: 8841210
    Abstract: According to one embodiment, a semiconductor device manufacturing method includes: forming a film to be a first metal layer on a substrate where an element portion is formed; forming a first insulating layer provided with an opening on the film to be the first metal layer; forming a second metal layer in the opening of the first insulating layer; eliminating the first insulating layer; eliminating the film to be the first metal layer with the second metal layer used as a mask so as to form the first metal layer; and forming an electrode portion by covering exposed surfaces of the first metal layer and the second metal layer with a third metal layer including a metal of a smaller ionization tendency than the metal of the second metal layer.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomomi Kuraguchi
  • Patent number: 8822332
    Abstract: A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: September 2, 2014
    Assignees: STMicroelectronics S.A., Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Heimanu Niebojewski, Yves Morand, Cyrille Le Royer, Fabrice Nemouchi
  • Patent number: 8779589
    Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Harsono S. Simka, Daniel J. Zierath, Michael G. Haverty, Sadasivan Shankar
  • Patent number: 8765600
    Abstract: A semiconductor device having a gate on a substrate with source/drain (S/D) regions adjacent to the gate. A first dielectric layer overlays the gate and the S/D regions, the first dielectric layer having first contact holes over the S/D regions with first contact plugs formed of a first material and the first contact plugs coupled to respective S/D regions. A second dielectric layer overlays the first dielectric layer and the first contact plugs. A second contact hole formed in the first and second dielectric layers is filled with a second contact plug formed of a second material. The second contact plug is coupled to the gate and interconnect structures formed in the second dielectric layer, the interconnect structures coupled to the first contact plugs. The second material is different from the first material, and the second material has an electrical resistance lower than that of the first material.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Long Chang, Chih-Ping Chao, Chun-Hung Chen, Hua-Chao Tseng, Jye-Yen Cheng, Harry-Hak-Lay Chuang
  • Patent number: 8716737
    Abstract: An LED includes a first intermetallic layer, a first metal thin film layer, an LED chip, a substrate, a second metal thin film layer, and a second intermetallic layer. The first metal thin film layer is located on the first intermetallic layer. The LED chip is located on the first metal thin film layer. The second metal thin film layer is located on the substrate. The second intermetallic layer is located on the second metal thin film layer, and the first intermetallic layer is located on the second intermetallic layer. Materials of the first and the second metal thin film layer are selected from a group consisting of Au, Ag, Cu, and Ni. Materials of the intermetallic layers are selected from a group consisting of a Cu—In—Sn intermetallics, an Ni—In—Sn intermetallics, an Ni—Bi intermetallics, an Au—In intermetallics, an Ag—In intermetallics, an Ag—Sn intermetallics, and an Au—Bi intermetallics.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 6, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Hsiu Jen Lin, Jian Shian Lin, Shau Yi Chen, Chieh Lung Lai
  • Patent number: 8697565
    Abstract: A method, and an apparatus formed thereby, to construct shallow recessed wells on top of exposed conductive vias on the surface of a semiconductor. The shallow recessed wells are subsequently filled with a conductive cap layer, such as a tantalum nitride (TaN) layer, to prevent or reduce oxidation which may otherwise occur naturally when exposed to air, or possibly occur during an under-bump metallization process.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lin-Ya Huang, Chi-Sheng Juan, Chien-Lin Tseng
  • Patent number: 8673766
    Abstract: Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes forming a trench/via in a layer of insulating material, performing a deposition process to form an as-deposited copper-based seed layer above the layer of insulating material in the trench/via, wherein the copper-based seed layer has a first portion that is positioned above a bottom of the trench/via that is thicker than second portions of the copper seed layer that are positioned above sidewalls of the trench/via, performing an etching process on the as-deposited copper-based seed layer to substantially remove portions of the second portions of the as-deposited copper-based seed layer and performing an electroless deposition process to fill the trench/via with a copper-based material.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sean X. Lin, Ming He, Xunyuan Zhang, Larry Zhao
  • Patent number: 8647976
    Abstract: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: February 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-seok Song, Dong-han Kim, Hee-seok Lee
  • Patent number: 8618677
    Abstract: A semiconductor package including a substrate, a semiconductor device, a protection layer, a bonding wire, and a molding compound is provided. The substrate has a contact pad and a solder mask, and the contact pad is exposed from the solder mask. The semiconductor device is disposed on the substrate. The protection layer is disposed on the contact pad. The bonding wire connects the semiconductor device to the contact pad. An end of the bonding wire penetrates the protection layer and bonds with a portion of a surface of the contact pad to form a bonding region. The protection layer covers an entire surface of the contact pad except the bonding region. The molding compound covers the semiconductor device, the contact pad, and the bonding wire.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: December 31, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Ta-Chun Lee
  • Patent number: 8592820
    Abstract: Disclosed are layers and patterns of nanowire or nanotube using a chemical self assembly for forming a semiconductor layer and a conductive layer of a thin film transistor by using a nanowire and/or nanotube solution and an diamine-based self-assembled monolayer (SAM) material. The Layers and patterns including layers and patterns of nanowire or nanotube using a chemical self assembly include: a substrate having a surface terminated with amine group (—NH2) by using a chemical self-assembled monolayer (SAM) material having at least one end terminated with amine group(—NH2); and a first nanowire or nanotube layer ionically coupled to the amine group (—NH2) of the surface of the substrate.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 26, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Jae-Hyun Kim, Bo-Hyun Lee, Tae-Hyoung Moon
  • Patent number: 8586485
    Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: November 19, 2013
    Assignee: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Tony P. Chiang, Majid Keshavarz
  • Publication number: 20130277845
    Abstract: An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, in which the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, at least one thermal expansion buffer layer, a backside metal layer, and at least one oxidation resistant layer, in which the backside metal seed layer is formed of Pd, and the thermal expansion coefficient of the thermal expansion buffer layer is in the range between the thermal expansion coefficients of the backside metal seed layer and of the backside metal layer. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations.
    Type: Application
    Filed: July 23, 2012
    Publication date: October 24, 2013
    Applicant: WIN SEMICONDUCTORS CORP.
    Inventors: Jason CHEN, Chang-Hwang HUA, Wen CHU
  • Publication number: 20130252419
    Abstract: A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap.
    Type: Application
    Filed: May 11, 2013
    Publication date: September 26, 2013
    Applicant: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Marc A. Bergendahl, Steven J. Holmes, David V. Horak, Charles W. Koburger, Shom Ponoth
  • Patent number: 8421230
    Abstract: Production of a device including: a substrate; multiple components forming an electronic circuit on the substrate; multiple superimposed metal levels of interconnections of the components, wherein the metal levels are located in at least one insulating layer resting on the substrate; and multiple elements made from a positive temperature coefficient conductive polymer material, wherein the elements traverse the insulating layer to a given depth, and are connected to at least one conductive line of a given interconnection level.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: April 16, 2013
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Didier Louis, Jean Du Port De Poncharra
  • Patent number: 8390018
    Abstract: A nitride-based semiconductor light emitting device with improved characteristics of ohmic contact to an n-electrode and a method of fabricating the same are provided. The nitride-based semiconductor light emitting device includes an n-electrode, a p-electrode, an n-type compound semiconductor layer, and an active layer and a p-type compound semiconductor layer formed between the n- and p-electrodes. The n-electrode includes: a first electrode layer formed of at least one element selected from the group consisting of Pd, Pt, Ni, Co, Rh, Ir, Fe, Ru, Os, Cu, Ag, and Au; and a second electrode layer formed on the first electrode layer using a conductive material containing at least one element selected from the group consisting of Ti, V, Cr, Zr, Nb, Hf, Ta, Mo, W, Re, Ir, Al, In, Pb, Ni, Rh, Ru, Os, and Au.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: March 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-hoon Jang
  • Patent number: 8372744
    Abstract: A contact rhodium structure is fabricated by a process that comprises obtaining a substrate having a dielectric layer thereon, wherein the dielectric layer has cavities therein into which the contact rhodium is to be deposited; depositing a seed layer in the cavities and on the dielectric layer; and depositing the rhodium by electroplating from a bath comprising a rhodium salt; an acid and a stress reducer; and then optionally annealing the structure.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: February 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Xiaoyan Shao
  • Patent number: 8367428
    Abstract: The present invention provides a semiconductor device which is characterized as follows. The semiconductor device includes: an interlayer insulating film formed above a semiconductor substrate and provided with a hole above an impurity diffusion region; a conductive plug formed in the hole and electrically connected to the impurity diffusion region; a conductive oxygen barrier film formed on the conductive plug and the interlayer insulating film around the conductive plug; a conductive anti-diffusion film formed on the conductive oxygen barrier film; and a capacitor that has a lower electrode which is formed on the conductive anti-diffusion film and which exposes platinum or palladium on the upper surface, a capacitor dielectric film made of a ferroelectric material, and an upper electrode. The conductive anti-diffusion film is made of a non-oxide conductive material for preventing the diffusion of the constituent element of the capacitor dielectric film.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: February 5, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8349730
    Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsueh Shih, Shau-Lin Shue
  • Publication number: 20120329271
    Abstract: A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.
    Type: Application
    Filed: August 31, 2012
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu, Surbhi Mittal
  • Publication number: 20120329270
    Abstract: A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material.
    Type: Application
    Filed: September 4, 2012
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Conal E. Murray
  • Patent number: 8338950
    Abstract: An electronic component has a substrate, a die bonding pad provided on an upper surface of the substrate, a semiconductor element bonded onto the die bonding pad by a die bonding resin, a conductive pattern disposed adjacent to the die bonding pad, and a coating member covering the conductive pattern. At least an outer peripheral portion of a surface of the die bonding pad is made of an inorganic material. The inorganic material of the outer peripheral portion is exposed. The die bonding pad and the conductive pattern are separated by an air gap such that the coating member does not come into contact with the die bonding pad.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: December 25, 2012
    Assignee: OMRON Corporation
    Inventors: Kazuyuki Ono, Yoshio Tanaka, Kiyoshi Nakajima, Naoto Kuratani, Tomofumi Maekawa
  • Patent number: 8309395
    Abstract: The invention relates to a method for fabricating a high-temperature compatible power semiconductor module in which a power semiconductor chip is bonded by means of a diffusion solder layer to a substrate and said substrate is bonded by means of silver sintered layer to a base plate, after which a bonding element is bonded to the top chip metallization. To prevent oxidation of the predefined bond area when producing the diffusion solder layer and the sintered silver layer 4? an anti-oxidation layer is applied to the top chip metallization at least in the region of the predefined bond area.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: November 13, 2012
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 8288274
    Abstract: A noble metal layer is formed using ozone (O3) as a reaction gas.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: October 16, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Deok-Sin Kil, Kee-Jeung Lee, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do, Kyung-Woong Park, Jeong-Yeop Lee, Ja-Yong Kim
  • Patent number: 8278199
    Abstract: Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
  • Patent number: 8227782
    Abstract: In a resistance change memory (ReRAM) storing data by utilizing change in resistance of a resistance change element, a lower electrode (ground-side electrode) of the resistance change element is formed of a transition metal such as Ni, and an upper electrode (positive polarity-side electrode) is configured of a noble metal such as Pt. In addition, a transition metal oxide film between the lower electrode and the upper electrode is formed of an oxide film (NiOx film) of a transition metal that is of the same kind as the transition metal constituting the lower electrode, for example.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: July 24, 2012
    Assignee: Fujitsu Limited
    Inventor: Hideyuki Noshiro
  • Patent number: 8227335
    Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Valery M. Dubin, Michael L. McSwiney, Peter Moon
  • Patent number: 8198730
    Abstract: A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point metal film. The copper interconnection film is polycrystalline, and crystal grains occupying 40% or more of an area of a unit interconnection surface among crystal grains forming the polycrystal are oriented to (111) in a substrate thickness direction. The copper interconnection film has crystal conformity with the noble metal liner film. In a case where the high-melting-point metal film is formed of Ti and the noble metal liner film is a Ru film, the high-melting-point metal of Ti dissolves into Ru in a solid state to form the noble metal liner. Thus, a copper interconnection is formed with both of Cu diffusion barrier characteristics and Cu crystal conformity.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: June 12, 2012
    Assignee: NEC Corporation
    Inventors: Masayoshi Tagami, Yoshihiro Hayashi, Munehiro Tada, Takahiro Onodera, Naoya Furutake, Makoto Ueki, Mari Amano
  • Patent number: 8178439
    Abstract: A method is provided for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a planarized patterned substrate containing metal surfaces and dielectric layer surfaces with a residue formed thereon, removing the residue from the planarized patterned substrate, and depositing metal-containing cap layers selectively on the metal surfaces by exposing the dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor. The removing includes treating the planarized patterned substrate containing the residue with a reactant gas containing a hydrophobic functional group, and exposing the treated planarized patterned substrate to a reducing gas.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: May 15, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhito Tohnoe, Frank M. Cerio, Jr.
  • Patent number: 8174121
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed. The semiconductor device also includes a first via plug and a first metal line respectively formed by filling the first via hole and the first trench with a first metal, a predetermined scratch being formed on the first metal line; and a second via plug a second metal line respectively formed by filling a second via hole and a second trench with a second metal, the second metal lines being separated.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: May 8, 2012
    Assignee: Dongbu Electronics Co. Ltd.
    Inventor: Min Dae Hong
  • Patent number: 8133812
    Abstract: This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: March 13, 2012
    Assignee: Lam Research Corporation
    Inventors: Yezdi Dordi, John Boyd, Fritz Redeker, William Thie, Tiruchirapalli Arunagiri, Alex Yoon
  • Patent number: 8119518
    Abstract: A film forming method includes the steps of forming a F-doped carbon film by using a source gas containing C and F, and modifying the F-doped carbon film by radicals, the source gas having a F/C ratio larger than 1 and smaller than 2, the F/C ratio being defined as a ratio of a number of F atoms to a number of C atoms in a source gas molecule.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: February 21, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Kenichi Nishizawa, Yasuhiro Terai, Akira Asano
  • Patent number: 8114770
    Abstract: A method for producing on-chip interconnect structures on a substrate is provided, comprising at least the steps of providing a substrate and depositing a ruthenium-comprising layer on top of said substrate, and then performing a pre-treatment of the Ru-comprising layer electrochemically with an HBF4-based electrolyte, and then performing electrochemical deposition of copper onto the pre-treated Ru-comprising layer.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: February 14, 2012
    Assignee: IMEC
    Inventors: Philippe M. Vereecken, Aleksandar Radisic
  • Patent number: 8110411
    Abstract: The present invention provides a semiconductor device which is characterized as follows. The semiconductor device includes: an interlayer insulating film formed above a semiconductor substrate and provided with a hole above an impurity diffusion region; a conductive plug formed in the hole and electrically connected to the impurity diffusion region; a conductive oxygen barrier film formed on the conductive plug and the interlayer insulating film around the conductive plug; a conductive anti-diffusion film formed on the conductive oxygen barrier film; and a capacitor that has a lower electrode which is formed on the conductive anti-diffusion film and which exposes platinum or palladium on the upper surface, a capacitor dielectric film made of a ferroelectric material, and an upper electrode. The conductive anti-diffusion film is made of a non-oxide conductive material for preventing the diffusion of the constituent element of the capacitor dielectric film.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: February 7, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8084348
    Abstract: A method for manufacturing a silicon chip package for a circuit board assembly provides a package with a silicon chip and an array of first contact pads that are provided by a first conductive material. A plurality of second contact pads are provided from a gold material having a hardness different than that of the first contact pads. The second contact pads are soldered to the first contact pads of the package. A circuit board assembly is assembled by providing a circuit board substrate with at least one socket with contact pads. The second contact pads of the package are assembled to the circuit board substrate contact pads.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: December 27, 2011
    Assignee: Oracle America, Inc.
    Inventor: Ashur S. Bet-Shliemoun
  • Patent number: 8062950
    Abstract: A semiconductor device has a semiconductor substrate, and a capacitor which is provided on the upper side of the semiconductor substrate and composed of a lower electrode, an upper electrode and a dielectric film, the dielectric film being placed in between the lower electrode and the upper electrode, the lower electrode including a noble metal film, and a plurality of conductive oxide films formed in an islands arrangement on the noble metal film.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Yamakawa, Soichi Yamazaki
  • Patent number: 8058164
    Abstract: The present invention relates to methods and structures for the metallization of semiconductor devices. One aspect of the present invention is a method of forming a semiconductor device having copper metallization. In one embodiment, the method includes providing a patterned wafer having a diffusion barrier for copper; depositing a copperless seed layer on the diffusion barrier effective for electrochemical deposition of gapfill copper. The seed layer is formed by a conformal deposition process and by a nonconformal deposition process. The method further includes electroplating copper gapfill onto the seed layer. Another aspect of the invention includes electronic devices made using methods and structures according to embodiments of the present invention.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: November 15, 2011
    Assignee: Lam Research Corporation
    Inventors: Hyungsuk Alexander Yoon, Fritz Redecker
  • Publication number: 20110260317
    Abstract: A copper pillar bump has a sidewall protection layer formed of an electrolytic metal layer. The electrolytic metal layer is an electrolytic nickel layer, an electrolytic gold layer, and electrolytic copper layer, or an electrolytic silver layer.
    Type: Application
    Filed: April 22, 2010
    Publication date: October 27, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Hsiung LU, Ming-Da CHENG, Chih-Wei LIN, Jacky CHANG, Chung-Shi LIU, Chen-Hua YU
  • Patent number: 8039378
    Abstract: To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. Subsequently, after removing the unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of the first thermal treatment is set to 10° C./s or more (for example, 30 to 250° C.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba