Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.

Abstract: A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.

Abstract: A semiconductor device is disclosed. The device includes a substrate, a first dielectric layer disposed over the substrate and a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer. The metal structure has a such shape that having an upper portion with a first width and a lower portion with a second width. The second width is substantially larger than the first width. The semiconductor device also includes a sub-structure of a second dielectric positioned between the upper portion of the metal structure and the first dielectric layer.

Abstract: Embodiments of the present invention provide processes to selectively form a metal layer on a conductive surface, followed by flowing a silicon based compound over the metal layer to form a metal silicide layer. In one embodiment, a substrate having a conductive surface and a dielectric surface is provided. A metal layer is then deposited on the conductive surface. A metal silicide layer is formed as a result of flowing a silicon based compound over the metal layer. A dielectric is formed over the metal silicide layer.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in at least the trench/via, after forming said barrier layer, performing at least one process operation to introduce manganese into the barrier layer and thereby define a manganese-containing barrier layer, forming a substantially pure copper-based seed layer above the manganese-containing barrier layer, depositing a bulk copper-based material above the copper-based seed layer so as to overfill the trench/via, and removing excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure.

Abstract: Methods to increase metal interconnect reliability are provided. Methods include forming a conformal barrier layer within an opening in a semiconductor device structure and forming a copper alloy material above the conformal barrier layer. Next, removing the copper alloy material that extends beyond the opening. Removing native oxide from a top surface of the copper alloy material. Further, annealing or applying a plasma treatment to the copper alloy material. Finally, forming a capping layer above the copper alloy material. Notably, near the top of the copper alloy material, smaller copper grain growth may be present. Furthermore, more non-copper alloy atoms are present near the top of the copper alloy material than the bulk of the copper alloy material.

Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.

Abstract: A method for fabricating a through-silicon via comprises the following steps. Provide a substrate. Form a through silicon hole in the substrate having a diameter of at least 1 ?m and a depth of at least 5 ?m. Perform a first chemical vapor deposition process with a first etching/deposition ratio to form a dielectric layer lining the bottom and sidewall of the through silicon hole and the top surface of the substrate. Perform a shape redressing treatment with a second etching/deposition ratio to change the profile of the dielectric layer. Repeat the first chemical vapor deposition process and the shape redressing treatment at least once until the thickness of the dielectric layer reaches to a predetermined value.

Abstract: A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present invention decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g. copper metallurgy or device dielectric. Thus, an improved aspect ratio for metal fill without introducing any excessive trapezoidal cross-sectional character to the defined metal receiving structures of the device will result.

Abstract: A method of fabricating a package substrate including preparing a substrate having at least one conductive pad, forming an insulating layer having an opening to expose the conductive pad on the substrate, forming a separation barrier layer on the conductive pad inside the opening to be higher than the upper surface of the insulating layer along the side walls thereof, forming a post terminal on the separation barrier layer, and forming a solder bump on the post terminal.

Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.

Abstract: Embodiments of the invention provide an improved process for depositing tungsten-containing materials. In one embodiment, the method for forming a tungsten-containing material on a substrate includes forming an adhesion layer containing titanium nitride on a dielectric layer disposed on a substrate, forming a tungsten nitride intermediate layer on the adhesion layer, wherein the tungsten nitride intermediate layer contains tungsten nitride and carbon. The method further includes forming a tungsten barrier layer (e.g., tungsten or tungsten-carbon material) from the tungsten nitride intermediate layer by thermal decomposition during a thermal annealing process (e.g., temperature from about 700° C. to less than 1,000° C.).

Abstract: A novel reversal lithography process without etch back is described. The reversal material comprises nanoparticles that are selectively deposited into the gaps between features without overcoating the tops of the features. As a result, a patterned imaging layer can be removed using solvent, blanket exposure followed by developer washing, or dry etching directly, without an etch-back process, and the original bright field lithography pattern can be reversed into dark field features, and transferred into subsequent layers using the nanoparticle reversal material as an etch mask.

Abstract: A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature.

Abstract: A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.

Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features.

Abstract: A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.

Abstract: An exemplary thin film transistor array substrate (200) includes a substrate (210) and a gate electrode (220) formed on the substrate. The gate electrode includes an adhesive layer (226) formed on the substrate, a conductive layer (224) formed on the adhesive layer and a barrier layer (222) formed on the conductive layer, the adhesive layer and the barrier layer both have sandwich structures. A central core of the adhesive layer, the conductive layer, and a central core of the barrier layer are made of a same material.

Abstract: Methods for fabricating conductive metal lines of a semiconductor device are described herein. In one embodiment, such a method may comprise depositing a conductive material over a substrate, and depositing a first barrier layer on the conductive layer. Such a method may also comprise patterning a mask on the first barrier layer, the pattern comprising a layout of the conductive lines. Such an exemplary method may also comprise etching the conductive material and the first barrier layer using the patterned mask to form the conductive lines. In addition, a low temperature post-flow may be performed on the structure. The method may also include depositing a dielectric material over and between the patterned conductive lines.

Abstract: A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer.

Abstract: Provided are methods of forming a ternary metal nitride film and more specifically, a TaSiN film. A metal nitride film, or TaN film, is deposited on a substrate with plasma treatment. A SiN layer is deposited on the metal nitride, or TaN, film to form a metal-SiN, or TaSiN, film. The film is then annealed to provide a metal nitride film with stable resistivity.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer.

Abstract: Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material.

Abstract: One or more embodiments relate to a method for making a semiconductor structure, the method including: forming a first conductive interconnect at least partially through the substrate; and forming a second conductive interconnect over the substrate, wherein the first conductive interconnect and the second conductive interconnect are formed at least partially simultaneously.

Abstract: A method of manufacturing a tungsten plug is described for producing semiconductor integrated circuits. The method protects the dielectric layer from getting damaged and avoids impact from CMP technology on the electrical RC properties of the semiconductor devices by using a high hardness amorphous carbon layer as an advance pattern film (APF) or barrier layer allowing grinding without altering the dielectric layer, to thereby improve the yield of products.

Abstract: A dielectric layer is formed on a substrate and patterned to form an opening. The opening is filled and the dielectric layer is covered with a metal layer. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is etched back a predetermined thickness from the top of the dielectric layer to expose the inside sidewalls thereof. A sidewall barrier layer is formed on the sidewalls of the dielectric layer. A copper-containing layer is formed over the metal layer, the dielectric layer, and the sidewall barrier layers. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the sidewall barrier layers at approximately the juncture of the sidewall of the dielectric layer and the copper-containing layer and does not etch into the underlying metal layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.

Abstract: An integrated circuit (IC) die has a top side surface providing circuitry including active circuitry configured to provide a function, including at least one bond pad formed from a bond pad metal coupled to a node in the circuitry. A dielectric passivation layer is over a top side surface of a substrate providing a contact area which exposes the bond pad. A metal capping layer includes an electrically conductive metal or an electrically conductive metal compound over at least the contact area to provide corrosion protection to the bond pad metal, which is in electrical contact with the bond pad metal. The metal capping layer can extend over structures other than the bond pads, such as to cover at least 80% of the area of the IC die to provide structures on the IC die protection from incident radiation.

Abstract: The method for the formation of a silicide film herein provided comprises the steps of forming an Ni film on the surface of a substrate mainly composed of Si and then heat-treating the resulting Ni film to thus form an NiSi film as an upper layer of the substrate, wherein, prior to the heat-treatment for the formation of the NiSi film, the Ni film is subjected to a preannealing treatment using H2 gas at a temperature which is less than the heat-treatment temperature and which never causes the formation of any NiSi film in order to remove any impurity present in the Ni film, and the resulting Ni film is then subjected to a silicide-annealing treatment to thus form the NiSi film.

Abstract: A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor.

Abstract: Methods for fabricating semiconductor devices having through electrodes are provided. The method may comprise forming a via hole which opens towards an upper surface of a substrate and disconnects with a lower surface of the substrate; forming a via isolation layer which extends along an inner surface of the via hole and covers the upper surface of the substrate; forming a seed layer on the via isolation layer which extends along the via isolation layer; annealing the seed layer in-situ after forming the seed layer; forming a conductive layer, filling the via hole, by an electroplating using the seed layer; and planarizing the upper surface of the substrate to form a through electrode surrounded by the via isolation layer in the via hole.

Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract: During the production of a semiconductor device having a Cu wiring line of a damascene structure, diffusion of fluorine from a CF film that serves as an interlayer insulating film is prevented in cases where a heat treatment is carried out, thereby suppressing increase in the leakage current. A semiconductor device of the present invention having a damascene wiring structure is provided with: an interlayer insulating film (2) that is formed of, for example, a fluorine-added carbon film; and a copper wiring line (4) that is embedded in the interlayer insulating film. A barrier metal layer (6) close to the copper wiring line and a fluorine barrier film (5) close to the interlayer insulating film are formed between the interlayer insulating film and the copper wiring line.

Abstract: A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material.

Abstract: Formulations and methods of making solar cell contacts and cells therewith are disclosed. The invention provides a photovoltaic cell comprising a front contact, a back contact, and a rear contact. The back contact comprises, prior to firing, a passivating layer onto which is applied a paste, comprising aluminum, a glass component, wherein the aluminum paste comprises, aluminum, another optional metal, a glass component, and a vehicle. The back contact comprises, prior to firing, a passivating layer onto which is applied an aluminum paste, wherein the aluminum paste comprises aluminum, a glass component, and a vehicle.

Abstract: Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support structure comprises an oxide infused silicon layer that is formed within a trench of a dielectric layer on a substrate of a semiconductor device. The oxide infused silicon layer results from a silicon layer that is exposed to oxide during an ultraviolet (UV) curing process. The oxide infused silicon layer is configured to support a barrier layer against a conductive structure formed on the barrier layer within the trench. In this way, the support structure provides pressure against the barrier layer so that the barrier layer substantially maintains contact with the conductive structure, to promote improved performance and reliability of the conductive structure.

Abstract: To achieve the foregoing and in accordance with the purpose of the present invention, a method for filling through silicon vias is provided. A dielectric layer is formed over the through silicon vias. A barrier layer, comprising tungsten, is deposited by CVD or ALD over the dielectric layer. The through silicon vias are filled with a conductive material.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract: An interconnect conductive metal used in forming an interconnect structure can be formed using a method in which deposition of a metal liner and a reflow anneal are performed in a same multi-chambered processing system without exposing the structure to air between the steps of deposition and reflow annealing. In the disclosure, an interconnect dielectric material including an opening is placed within the multi-chambered processing system and then the interconnect dielectric material is transferred, under vacuum, to a deposition chamber in which the metal liner is deposited. The interconnect dielectric material including the metal liner is then transferred, under the same vacuum, to an annealing chamber in which a reflow anneal is performed.

Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

Abstract: The present disclosure relates to a method and apparatus for improving back-end-of-the-line (BEOL) reliability. In some embodiments, the method forms an extreme low-k (ELK) dielectric layer having one or more metal layer structures over a semiconductor substrate. A first capping layer is formed over the ELK dielectric layer at a position between the one or more metal layer structures. A second capping layer is then deposited over the one or more metal layer structures at a position that is separated from the ELK dielectric layer by the first capping layer. The first capping layer has a high selectivity that limits interaction between the second capping layer and the ELK dielectric layer, reducing diffusion of the atoms from the second capping layer to the ELK dielectric layer and improving dielectric breakdown of the ELK dielectric layer.

Abstract: A semiconductor device includes a gate structure on a semiconductor substrate, an impurity region at a side of the gate structure and the impurity region is within the semiconductor substrate, an interlayer insulating layer covering the gate structure and the impurity region, a contact structure extending through the interlayer insulating layer and connected to the impurity region, and an insulating region. The contact structure includes a first contact structure that has a side surface surrounded by the interlayer insulating layer and a second contact structure that has a side surface surrounded by the impurity region. The insulating region is under the second contact structure.

Abstract: Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the opening in the layer of insulating material that exposes a portion of an underlying copper-containing structure, performing a wet etching process to remove the patterned metal hard mask layer, performing a selective metal deposition process through the opening in the layer of insulating material to selectively form a metal region on the copper-containing structure and, after forming the metal region, forming a copper-containing structure in the opening above the metal region.

Abstract: A method for manufacturing semiconductor device includes preparing a structure including a substrate, an insulating layer on the substrate and having a recess, a barrier film on the insulating layer, and a copper film on the barrier such that the copper film is filling the recess with the barrier between the insulating layer and copper film, removing the copper film down to interface with the barrier such that copper wiring is formed in the recess, etching the wiring such that surface of the wiring is recessed from surface of the insulating layer, and removing the barrier from the surface of the insulating layer such that the surface of the insulating layer is exposed. The etching includes positioning the structure removed down to the barrier in organic compound atmosphere having vacuum state, and irradiating oxygen gas cluster ion beam on the surface of the wiring to anisotropically etch the wiring.

Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.

Abstract: The present application provides a method of manufacturing an optoelectronic semiconductor device, comprising the steps of: providing a substrate; forming an optoelectronic system on the substrate; forming a barrier layer on the optoelectronic system; forming an electrode on the barrier layer; and annealing the optoelectronic semiconductor device; wherein the optoelectronic semiconductor device has a first forward voltage before the annealing step and has a second forward voltage after the annealing step, and a difference between the second forward voltage and the first forward voltage is smaller than 0.2 Volt.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece including an insulating material layer disposed thereon. The insulating material layer includes a trench formed therein. The method includes forming a barrier layer on the sidewalls of the trench using a surface modification process and a surface treatment process.

Abstract: An integrated circuit includes a MOS transistor having a gate region and source and drain regions separated from the gate region by insulating spacers. At least two metal contact pads respectively contact with two metal silicide regions (for example, a cobalt silicide) which lie within the source and drain regions. The silicide regions are located at the level of lower parts of the two metal contact pads and are separate by a distance from the insulating spacers.