Having Electrically Conductive Polysilicon Component Patents (Class 438/657)
  • Publication number: 20150037975
    Abstract: Provided is a method of forming a silicon film in a groove formed on a surface of an object to be processed, which includes: forming a first silicon layer on the surface of the object to be processed to embed the groove; doping impurities near a surface of the first silicon layer; forming a seed layer on the doped first silicon layer; and forming a second silicon layer containing impurities on the seed layer.
    Type: Application
    Filed: August 1, 2014
    Publication date: February 5, 2015
    Inventors: Katsuhiko KOMORI, Mitsuhiro OKADA
  • Patent number: 8895435
    Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Yun-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • Patent number: 8815735
    Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: August 26, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Yi Jung Chen, Kuo Hui Su, Chiang Hung Lin
  • Patent number: 8741746
    Abstract: A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20140061867
    Abstract: A method for depositing one or more polycrystalline silicon layers (230c) on a substrate (210) by a chemical vapour deposition in a reactor, includes adjusting a deposition temperature between 605° C.-800° C. in a process chamber of the reactor, and depositing the one or more polycrystalline silicon layers on the substrate by using a silicon source gas including SiH4 or SiH2Cl2, and a dopant gas including BCl3.
    Type: Application
    Filed: March 30, 2012
    Publication date: March 6, 2014
    Applicant: Okmetic OYJ
    Inventors: Veli Matti Airaksinen, Jari Makinen
  • Publication number: 20140015138
    Abstract: Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Applicant: SPANSION LLC
    Inventors: Bradley Marc DAVIS, Mark W. Randolph, Sung-Yong Chung, Hidehiko Shiraiwa
  • Publication number: 20130334565
    Abstract: Source zones of a first conductivity type and body zones of a second conductivity type are formed in a semiconductor die. The source zones directly adjoin a first surface of the semiconductor die. A dielectric layer adjoins the first surface. Polysilicon plugs extend through the dielectric layer and are electrically connected to the source and the body zones. An impurity source containing at least one metallic recombination element is provided in contact with deposited polycrystalline silicon material forming the polysilicon plugs and distant to the semiconductor die. Atoms of the metallic recombination element, for example platinum atoms, may be diffused out from the impurity source into the semiconductor die to reliably reduce the reverse recovery charge.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Michael Hutzler, Ralf Siemieniec, Oliver Blank
  • Patent number: 8486835
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 16, 2013
    Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Tom L. Cadwell, Doris Mytton
  • Patent number: 8471367
    Abstract: A semiconductor device includes a second oxide film and a pad electrode on a first oxide film that is formed on a front surface of a semiconductor substrate, a contact electrode and a first barrier layer formed in the second oxide film and connected to the pad electrode, a silicide portion formed between the contact electrode and a through-hole electrode layer and connected to the contact electrode and the first barrier layer, a via hole extending from a back surface of the semiconductor substrate to reach the silicide portion and the second oxide film, a third oxide film formed on a sidewall of the via hole and on the back surface of the semiconductor substrate, and a second barrier layer (H) and a rewiring layer formed inside the via hole and on the back surface of the semiconductor substrate and connected to the silicide portion.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Daishiro Saito, Takayuki Kai, Takafumi Okuma, Hitoshi Yamanishi
  • Patent number: 8456010
    Abstract: A semiconductor device of an embodiment includes: a semiconductor layer made of p-type nitride semiconductor; an oxide layer formed on the semiconductor layer, the oxide layer being made of a polycrystalline nickel oxide, and the oxide layer having a thickness of 3 nm or less; and a metal layer formed on the oxide layer.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: June 4, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Saito, Maki Sugai, Eiji Muramoto, Shinya Nunoue
  • Patent number: 8409989
    Abstract: A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: April 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Chengwen Pei, Roger Allen Booth, Jr., Kangguo Cheng, Joseph Ervin, Ravi M. Todi, Geng Wang
  • Patent number: 8350344
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Min Son, Woon-Kyung Lee
  • Patent number: 8324099
    Abstract: A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug comprises a first region, a second region, a third region, and a fourth region, wherein the first region is disposed beneath the second region and doped with a first doping concentration, the second region is disposed above the first region and below the third region and is not doped, the third region is disposed above the second region and below the fourth region and is doped with a second doping concentration that is lower than the first doping concentration, and the fourth region is disposed above the third region and is doped with a third doping concentration that is higher than the first doping concentration; and annealing the resulting product formed with the landing
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: December 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyoung Bong Rouh
  • Patent number: 8318556
    Abstract: A method for making contact landing pad structures in a semiconductor integrated circuit device includes forming an isolation region and forming active regions in the semiconductor substrate. The active regions are separated by the isolation region, and each of the active regions includes one or more contact regions. The method includes forming a raised structure overlying the isolation region and disposed between a first and second contact regions. The method includes depositing a cap layer and forming an interlayer dielectric layer overlying the cap layer. The method includes depositing a photoresist layer overlying the interlayer dielectric layer and uses a mask pattern to selectively remove a portion of the photoresist layer to form a line type opening, which exposes a portion of the interlayer dielectric layer overlying at least the first and second contact regions. The method deposits a conductive fill material and performs a planarization process to form multiple conductive landing contact pads.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Ping Ting Wang, Cheng Yang, Seung Hyuk Lee, Jin Gang Wu
  • Patent number: 8298939
    Abstract: A method for fabricating a conductive contact is provided, including: providing a semiconductor substrate with a dielectric layer formed thereover and two conductive regions and an isolation element formed therein, wherein the isolation element isolates the two conductive regions from each other; forming an opening in the dielectric layer, exposing a top surface of the isolation element and a portion of a top surface of each of the conductive regions; performing an epitaxy process and forming a conductive semiconductor layer within the opening, overlying the top surface of the isolation element and the portion of the top surface of each of the conductive regions; and forming a conductive layer in the opening, overlying the conductive semiconductor layer and filling the opening.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 30, 2012
    Assignee: Nanya Technology Corporation
    Inventors: Jar-Ming Ho, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20120193796
    Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 2, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Liang Lin, Yun-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • Patent number: 8143158
    Abstract: Embodiments of the present invention describe a method and device of preventing delamination of semiconductor layers in a semiconductor device. The semiconductor device comprises a substrate with an interlayer dielectric (ILD). A protection layer is deposited on the ILD. Next, a getter layer is formed on the protection layer to remove any native oxides on the protection layer. A capping layer is then deposited on the getter layer to prevent oxidation of the getter layer. Next, a semiconductor layer is formed on the capping layer. An oxide layer is then deposited on the semiconductor layer. Subsequently, a buffered oxide etch solution is used to remove the oxide layer. By removing the native oxides on the protection layer, the getter layer prevents the reaction between the buffered oxide etch solution and the native oxides which may cause delamination of the semiconductor layer and protection layer.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventor: Ajay Jain
  • Publication number: 20120012922
    Abstract: A semiconductor device and a method of manufacturing the same are provided. Upon forming source or drain at a lower part of the pillar pattern, a silicon oxide layer (barrier layer) is formed inside the pillar pattern to prevent the pillar pattern from being electrically floated. Furthermore, impurities are diffused to a vertical direction (longitudinal direction) of the pillar pattern to overlay junction between the semiconductor substrate and source or drain formed at a lower part of the pillar pattern that leads to improvement of a current characteristic.
    Type: Application
    Filed: November 12, 2010
    Publication date: January 19, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Tae Su JANG
  • Patent number: 8076729
    Abstract: Disclosed is a method for forming a dual gate electrode of a semiconductor device, which may improve manufacturing productivity by simplifying a process of forming gate electrodes in PMOS and NMOS regions, respectively, and may provide improvement in performance by making the two gate electrodes have a different thickness and material state in a manner that one of the two gate electrodes has a single-layer structure and the other one has a two-layer structure.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: December 13, 2011
    Assignee: Dongbu Hitek Co., Ltd
    Inventor: Eun Sang Cho
  • Patent number: 8039382
    Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Sunfei Fang, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Renee T. Mo, Balasubramanian Pranatharthiharan, Jay W. Strane
  • Patent number: 8003529
    Abstract: A method of forming an integrated circuit is disclosed. The method includes providing a substrate and forming on the substrate a shield structure comprising a shield member and a ground strap. The shield member comprises a non-metallic portion, and the ground strap comprises a metallic portion.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: August 23, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Suh Fei Lim, Kok Wai Chew, Sanford Shao-Fu Chu, Michael Chye Huat Cheng
  • Patent number: 7989330
    Abstract: After etching a polysilicon film, when a protective film made of a carbon polymer is formed on a sidewall of the polysilicon film using plasma containing carbons, a metallic material as a lower film is etched using plasma containing a halogen gas under an etching condition in which volatility is improved due to the rise in a wafer temperature or the low pressure of a processing pressure, thereby preventing a side etching and unevenness of a sidewall of the polysilicon film. Further, by using the protective film made of a carbon polymer, metallic substances scattered at the time of etching the metallic material are not directly attached to the polysilicon film, but can be simply removed along with the protective film made of a carbon polymer in an asking step.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: August 2, 2011
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takeshi Shima, Kenichi Kuwabara, Tomoyoshi Ichimaru, Kenji Imamoto
  • Patent number: 7943501
    Abstract: A method of forming (and apparatus for forming) tantalum silicide layers (including tantalum silicon nitride layers), which are typically useful as diffusion barrier layers, on a substrate by using a vapor deposition process with a tantalum halide precursor compound, a silicon precursor compound, and an optional nitrogen precursor compound.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: May 17, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Brian A. Vaartstra
  • Patent number: 7935629
    Abstract: An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: May 3, 2011
    Assignee: International Business Machines Corporation
    Inventors: Todd Alan Christensen, Richard Lee Donze, William Paul Hovis, Terrance Wayne Kueper, John Edward Sheets, II
  • Patent number: 7923368
    Abstract: A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nanoparticles include dopant atoms therein. The method also includes heating the non-densified thin film to a first temperature and for a first time period to remove a solvent from the deposited nanoparticle ink; and heating the non-densified thin film to a second temperature and for a second time period to form a densified thin film, wherein at least some of the dopant atoms diffuse into the wafer to form the diffusion region.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: April 12, 2011
    Assignee: Innovalight, Inc.
    Inventors: Mason Terry, Homer Antoniadis, Dmitry Poplavskyy, Maxim Kelman
  • Patent number: 7790611
    Abstract: A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, John J. Ellis-Monaghan, Edward J. Nowak, Jed H. Rankin
  • Patent number: 7754605
    Abstract: The surface of a conductive layer such as a conductive nitride, a conductive silicide, a metal, or metal alloy or compound, is exposed to a dopant gas which provides an n-type or p-type dopant. The dopant gas may be included in a plasma. Semiconductor material, such as silicon, germanium, or their alloys, is deposited directly on the surface which has been exposed to the dopant gas. During and subsequent to deposition, dopant atoms diffuse into the deposited semiconductor, forming a thin heavily doped region and making a good ohmic contact between the semiconductor material and the underlying conductive layer.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: July 13, 2010
    Assignee: SanDisk 3D LLC
    Inventors: S. Brad Herner, Steven J Radigan
  • Patent number: 7737031
    Abstract: Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Ramakanth Alapati, Gurtej Sandhu
  • Patent number: 7723233
    Abstract: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: May 25, 2010
    Assignee: Semequip, Inc.
    Inventors: Wade A Krull, Dale C. Jacobson
  • Publication number: 20100120244
    Abstract: A method of forming an integrated circuit is disclosed. The method includes providing a substrate and forming on the substrate a shield structure comprising a shield member and a ground strap. The shield member comprises a non-metallic portion, and the ground strap comprises a metallic portion.
    Type: Application
    Filed: January 25, 2010
    Publication date: May 13, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Suh Fei LIM, Kok Wai CHEW, Sanford Shao-Fu CHU, Michael Chye Huat CHENG
  • Patent number: 7709372
    Abstract: A method of manufacturing a metal wiring in a semiconductor device includes: forming a via hole by selectively etching an interlayer insulating layer formed on a first metal layer; sequentially forming a first barrier metal layer and a second metal layer on the interlayer insulating layer; etching the first barrier metal layer and the second metal layer in the via hole to a predetermined depth together with selectively etching a surface of the second metal layer; forming a silicon layer on the first barrier metal and the second metal to a predetermined height; forming a second barrier metal layer on the interlayer insulating layer; forming a third metal layer on the second barrier metal layer; and forming a second barrier metal pattern and a third metal layer pattern by patterning the second barrier metal layer and the third metal layer.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: May 4, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Keun Soo Park
  • Patent number: 7701058
    Abstract: Defect density of a polysilicon metal silicide wiring is reduced by employing a block of undoped polysilicon metal silicide in locations in which dopants are not needed in the underlying polysilicon. Furthermore, detection of presence of defects in the polysilicon metal wiring that adversely impacts device performance at high frequency is facilitated by employing a block of undoped polysilicon metal silicide since defects in undoped polysilicon metal silicide is more readily detectable than defects in doped polysilicon metal silicide. Locations wherein undoped polysilicon metal silicide wiring is employed include areas over shallow trench isolation.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: April 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Publication number: 20100035429
    Abstract: A fabricating method of a polysilicon layer is disclosed which can be applied for fabricating a semiconductor device such as a SRAM and so on.
    Type: Application
    Filed: January 18, 2008
    Publication date: February 11, 2010
    Inventors: Taek-Yong Jang, Byung-Il Lee, Young-Ho Lee, Seok-Pil Jang
  • Patent number: 7652335
    Abstract: A semiconductor device having a silicon layer, a transistor having an electrical connection region in the silicon layer; and a conductive plug formed on and in electrical contact with the electrical connection region, the plug having side walls that taper inward away from the silicon layer.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: January 26, 2010
    Assignee: Toshiba America Electronics Components, Inc.
    Inventor: Katsura Miyashita
  • Patent number: 7622383
    Abstract: A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elements as a first reactant and a dopant to a substrate to form a first reactant adsorption layer that is doped with impurities on the substrate and then supplying a second reactant having H (hydrogen) to the first reactant adsorption layer to react the H of the second reactant with the halogen elements of the first reactant to form a doped Si atomic layer on the substrate.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: November 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyun Kim, Ki-Hyun Hwang, Jin-Tae Noh, Hong-Suk Kim, Sung-Hae Lee
  • Patent number: 7611989
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: November 3, 2009
    Assignee: Integrated Materials, Inc.
    Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Robert W. Mytton, Doris Mytton, legal representative, Tom L. Cadwell
  • Patent number: 7611943
    Abstract: A process (200) for making integrated circuits with a gate, uses a doped precursor (124, 126N and/or 126P) on barrier material (118) on gate dielectric (116). The process (200) involves totally consuming (271) the doped precursor (124, 126N and/or 126P) thereby driving dopants (126N and/or 126P) from the doped precursor (124) into the barrier material (118). An integrated circuit has a gate dielectric (116), a doped metallic barrier material (118, 126N and/or 126P) on the gate dielectric (116), and metal silicide (180) on the metallic barrier material (118). Other integrated circuits, transistors, systems and processes of manufacture are disclosed.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: November 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Kaiping Liu
  • Patent number: 7605033
    Abstract: Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided. In some embodiments, the method includes forming a metallized contact to an active area in a silicon substrate in a peripheral circuitry area and a metallized contact to a polysilicon plug in a memory cell array area by forming a first opening to expose the active area at the peripheral circuitry area, chemical vapor depositing a titanium layer over the dielectric layer and into the first opening to form a titanium silicide layer over the active area in the silicon substrate, removing the titanium layer selective to the titanium silicide layer, forming a second opening in the dielectric layer to expose the polysilicon plug at the memory cell array area, and forming metal contacts within the first and second openings to the active area and the exposed polysilicon plug.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: October 20, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Terrence McDaniel, Sandra Tagg, Fred Fishburn
  • Patent number: 7592240
    Abstract: A fabrication method for forming a gate structure through an amorphous silicon layer includes providing a substrate layer, forming an amorphous silicon layer of a selected thickness on the substrate layer at a reaction temperature between about 520° C. and 560° C., and forming a doped amorphous silicon layer in a upper portion of the amorphous silicon layer at a reaction temperature between about 520° C. and 560° C.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: September 22, 2009
    Assignee: Mosel Vitelic, Inc.
    Inventors: Jen Chieh Chang, Shih-Chi Lai, Yi Fu Chung, Tun-Fu Hung
  • Patent number: 7579231
    Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising forming a metal compound film directly or indirectly on a semiconductor substrate, forming a metal-containing insulating film consisting of a metal oxide film or a metal silicate film by oxidizing the metal compound film, and forming an electrode on the metal-containing insulating film.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: August 25, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouji Matsuo, Tomohiro Saito, Kyoichi Suguro, Shinichi Nakamura
  • Patent number: 7573132
    Abstract: A wiring structure of a semiconductor device may have an insulation layer, a spacer and a plug. The insulation layer may be provided on a substrate and may have an opening through which a contact region of the substrate is exposed. The spacer may be provided on a sidewall of the opening. The plug may fill the opening and may include a polysilicon pattern doped with impurities, a metal silicide pattern, and a metal pattern sequentially provided on the substrate.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: August 11, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyuk Chung, In-Seak Hwang
  • Patent number: 7563708
    Abstract: A method for manufacturing a semiconductor device includes implanting metal ions on a residual interlayer dielectric film in a storage contact hole to the residual dielectric film, thereby reducing a contact resistance to prevent failures of the semiconductor device.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: July 21, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Yong Jung
  • Publication number: 20090108356
    Abstract: A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
    Type: Application
    Filed: October 25, 2007
    Publication date: April 30, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Michael P. Chudzik, Rama Divakaruni, Geng Wang, Robert C. Wong, Haining S. Yang
  • Patent number: 7524757
    Abstract: A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dummy layer, wherein the preliminary second SEG layer is formed directly on only the first SEG layer and a portion of the first insulating layer formed on the cell region of the substrate, and wherein the dummy layer is formed on the peripheral region of the substrate. The method further includes planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer, forming a second active region from the second SEG layer formed on a first insulating layer, and forming a second transistor on the second active region.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: April 28, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-jun Kim, Chang-ki Hong, Bo-un Yoon, Jae-kwang Choi
  • Publication number: 20090101943
    Abstract: A semiconductor device having a silicon layer, a transistor having an electrical connection region in the silicon layer; and a conductive plug formed on and in electrical contact with the electrical connection region, the plug having side walls that taper inward away from the silicon layer.
    Type: Application
    Filed: October 17, 2007
    Publication date: April 23, 2009
    Applicant: Toshiba America Electronic Components, Inc.
    Inventor: Katsura Miyashita
  • Patent number: 7476613
    Abstract: A contact for a semiconductor device is made by performing, inter alia, a CMP process on an interlayer insulation layer to expose a first hard mask layer of each conductive line. The interlayer insulation layer is partially removed. A second hard mask layer is formed on a resultant substrate. Another CMP process is performed on the second hard mask layer to expose the first hard mask layer of each conductive line. A hard mask pattern is formed by etching portions of the CMPed second hard mask layer. The interlayer insulation layer is etched by using the hard mask pattern as an etch barrier to open the contact forming regions of the substrate. A conductive layer is deposited on the resultant substrate to fill the opened contact forming regions. The conductive layer and the remaining hard mask pattern are removed to expose the first hard mask layer of each conductive line.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: January 13, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyung Hwan Kim
  • Patent number: 7432198
    Abstract: An example disclosed semiconductor device includes a semiconductor substrate, a lower interlayer insulating layer formed on the substrate, a lower wire formed on the lower interlayer insulating layer, and an upper interlayer insulating layer which is formed on the lower interlayer insulating layer and has a via hole to expose the lower wire. The lower wire includes a metal layer pattern and a conductive layer pattern, and the metal layer pattern has a protruding portion and the conductive layer pattern is formed on the upper part of the protruding portion of the metal layer pattern and has a hole to expose the protruding portion.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: October 7, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang-Kwon Kim
  • Patent number: 7425496
    Abstract: A conducting layer is deposited on an insulating layer disposed on a substrate. A mask is formed on at least one area of the conducting layer, thus delineating in the conducting layer at least one complementary area not covered by the mask. The complementary areas of the conducting layer are rendered insulating by oxidation. Oxidation can comprise oxygen implantation and/or thermal oxidation. The material of the conducting layer and the oxygen can form a volatile oxide evaporating partly or totally. The conducting layer is preferably formed by first and second conducting layers. Thus, oxidation can be performed, after the mask has been removed, so that the surface of the second conducting layer is oxidized on the side walls and on the front face.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: September 16, 2008
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Simon Deleonibus
  • Patent number: 7384877
    Abstract: By reducing the effect of particle bombardment during the sequence for forming a metal silicide in semiconductor devices, the defect rate and the metal silicide uniformity may be enhanced. For this purpose, the metal may be deposited without an immediately preceding sputter etch process, wherein, in a particular embodiment, an additional oxidation process is performed to efficiently remove any silicon contaminations and surface impurities by a subsequent wet chemical treatment on the basis of HF, which is followed by the metal deposition.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: June 10, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Volker Kahlert, Christof Streck, Patrick Press
  • Patent number: 7371681
    Abstract: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: May 13, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Kazuyoshi Maekawa