Abstract: The present invention is directed toward a method for independently doping the gate and the source-drain regions of a semiconductor device. The method is initiated by the provision. of a substrate having isolation regions and a thin insulating layer. Over the substrate is formed a polysilicon layer which is doped with a first type of dopant at a first doping level. Over the polysilicon layer is formed a conducting layer of material that can withstand temperatures of 1000° C., and over the conducting layer is formed a blocking layer. The polysilicon layer, the conducting layer and the blocking layer are etched to form a gate stack. Source-drain regions are subsequently doped with a second type of dopant at a second doping level. Source-drain regions are activated in a 1000° C. heat cycle, and, subsequently, TiSi2 is formed on the source-drain regions. Contacts are then formed.

Abstract: The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a contact to the thermally conducting material. The invention also relates to a semiconductor device. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.

Abstract: There is described a method of manufacturing a semiconductor device, wherein a DRAM memory cell and a logic circuit are fabricated on a single semiconductor substrate, which method enables improvements in the refresh characteristics of the DRAM memory cell by preventing a leakage current from developing and enables improvements in the reliability of the semiconductor device, reduces power consumption, and enables improvements in the performance and processing speed of integrated circuits by assembly of the integrated circuits into a single chip. After formation of a polysilicon layer which is to act as gate electrodes, silicon nitride films are formed so as to cover source/drain regions of the DRAM memory cell and to cause other source/drain regions and the polysilicon layer to be exposed. A metal silicide layer is formed on the semiconductor substrate by means of self-aligned silicide technique.

Abstract: A method used during the formation of a semiconductor device such as a flash memory device comprises the steps of forming a floating gate layer over a semiconductor wafer substrate then forming a first oxide layer over the floating gate layer. An oxidation-resistant layer such as a nitride layer is formed over the first oxide layer wherein a first portion of the oxidation-resistant layer oxidizes more readily than a second portion of the oxidation-resistant layer. To accomplish this the first portion of the oxidation-resistant layer can be formed to have a higher silicon concentration than the second portion. The first portion of the oxidation-resistant layer is oxidized to form a second oxide layer and a control gate layer is formed over the second oxide layer. An in-process semiconductor device is also described.

Abstract: A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack.

Abstract: A new method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which a composite polysilicon top plate electrode is provided which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer and gate oxide layer are etched away where they are not covered by a mask to provide a PMOS gate electrode in a first region of the wafer and a bottom plate electrode for the capacitor in a second region of the wafer. A capacitor dielectric layer is deposited over the surface of the wafer. A composite polysilicon layer is deposited overlying the capacitor dielectric layer wherein the composite polysilcon layer comprises a lower doped polysilcon layer and an upper undoped polysilicon layer.

Abstract: There is described a semiconductor device manufacturing method which enables substantial elimination of oxygen atoms or crystalline imperfections included in a gate oxide film of an element fabricated on a well which is formed in a semiconductor substrate by means of high-energy ion implantation. An element whose gate oxide film has a high degree of reliability is manufactured by combining manufacturing conditions for forming a pad film on the surface of a substrate such as the type and thickness of the pad film, the valence of ions to be implanted, an implantation energy, and ion implantation before or after removal of the pad film. If necessary, post-implantation annealing conditions or conditions for growing a sacrificial oxide film are selected.

Abstract: The invented method can be used to form silicide contacts to an integrated MISFET device. Field isolation layers are formed to electrically isolate a portion of the silicon substrate, and gate, source and drain regions are formed therein. A polysilicon runner(s) that makes an electrical connection to the integrated device, is formed on the isolation layers. The structure is subjected to ion implantation to amorphized portions of the silicon gate, source, drain and runner regions. A metal layer is formed in contact with the amorphized regions, and the metal layer overlying the active region of the integrated device is selectively irradiated using a mask. The light melts part of the gate, and amorphized source and drain regions while the remaining portions of the integrated device and substrate remain in their solid phases. Metal diffuses into the melted gate, source and drain regions which are thus converted into respective silicide alloy regions.

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with hafnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper interstitial positions.

Abstract: A method for forming a titanium polycide gate, comprising the steps of: forming a gate oxide and a doped polysilicon layer over the semiconductor substrate, in turn; implanting impurity ions into the doped polysilicon layer to form an amorphous phase silicon layer in the surface of the polysilicon layer; forming an amorphous phase titanium silicide layer over the amorphous phase silicon layer; carrying out heat-treatment to transform the amorphous phase titanium silicide layer into a crystalline phase titanium silicide layer and to transform the amorphous phase silicon layer into the crystalline silicon layer; and patterning the crystalline phase titanium silicide layer, the polysilicon layer including the crystalline phase silicon layer and the gate oxide to form the titanium polycide gate.

Abstract: A method for making contact with a covered semiconductor layer through a contact hole, includes producing a contact hole in an insulator layer for making contact with at least one covered semiconductor layer. A heavily doped polysilicon layer is produced on the surface of the insulator layer and the contact hole is at least partially filled with heavily doped polysilicon. A metal layer is applied on the heavily doped polysilicon layer for establishing an ohmic connection to the outside. A semiconductor component fabricated according to the method is also provided.

Abstract: A method for forming a low resistance metal/polysilicon gate for use in CMOS devices comprising: (1) a novel anneal step prior to formation of a diffusion barrier layer and (2) a novel diffusion barrier layer composed of titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon. A first insulating layer is formed over a silicon substrate, and a polysilicon layer is formed over the first insulating layer. In a key step, the polysilicon layer is annealed to prevent peeling of the subsequently formed diffusion barrier layer. A diffusion barrier layer comprising titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon is formed over the polysilicon layer. A tungsten layer is formed over the diffusion barrier layer, and a capping layer comprising a silicon nitride layer over an oxide layer can be formed over the tungsten layer.

Abstract: A first convex portion and a second convex portion are formed on a semiconductor substrate at a prescribed interval, an impurity diffusing region is formed on an upper portion of the semiconductor substrate placed between the first and second convex portions, and a thinned first polysilicon film is formed on the impurity diffusing region and the first and second convex portions. Thereafter, arsenic ions are implanted into the first polysilicon film to make the first polysilicon film conductive. Thereafter, a second polysilicon film having a film thickness larger than that of the first polysilicon film is formed, and phosphorus ions are implanted into the second polysilicon film to make the second polysilicon film conductive. Thereafter, a tungsten silicide film is formed on the second polysilicon film, and the tungsten silicide film and the first and second polysilicon films are patterned.

Abstract: A method of forming a silicide region (80) on a Si substrate (10) in the manufacturing of semiconductor integrated devices, a method of forming a semiconductor device (MISFET), and a device having suicide regions formed by the present method. The method of forming a silicide region involves forming a silicide region (80) in the (crystalline) Si substrate having an upper surface (12) and a lower surface (14). The method comprises the steps of first forming an amorphous doped region (40) in the Si substrate at or near the upper surface, to a predetermined depth (d). This results in the formation of an amorphous-crystalline interface (I) between the amorphous doped region and the crystalline Si substrate. The next step is forming a metal layer (60) atop the Si substrate upper surface, in contact with the amorphous doped region. The next step involves performing backside irradiation with a first radiation beam (66).

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact.

Abstract: A method for forming a refractory metal layer that features two-stage nucleation prior to bulk deposition of the same. The method includes placing a substrate in a deposition zone, flowing, into the deposition zone during a first deposition stage, a silicon source, such as a silane gas, and a tungsten source, such as tungsten-hexafluoride gas, so as to obtain a predetermined ratio of the two gases therein. During a second deposition stage, subsequent to the first deposition stage, the ratio of the two gases is varied. Specifically, in the first deposition stage there is a greater quantity of silane gas than tungsten-hexafluoride gas. In the second deposition stage there may be a greater quantity of tungsten-hexafluoride than silane.

Abstract: A method of forming a gate electrode with a titanium polycide which can prevent particle creation and abnormal oxidation of the gate electrode, is disclosed. In the present invention, a gate oxidation process is performed after implanting Si ions into the side wall or overall surface of the titanium silicide layer, thereby preventing abnormal oxidation of the titanium silicide during the gate oxidation process. Furthermore, a titanium silicide layer is deposited to a low mole ratio of Si/Ti, thereby minimizing particle creation.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of forming a silicon oxide film on a semiconductor substrate for defining device isolation regions therewith, forming a gate oxide film over the product resulting from the previous step, forming an electrically conductive film over the product resulting from the previous step, forming a first insulating film over the electrically conductive film, etching the first insulating film and the electrically conductive film to thereby form a first wiring layer comprising a plurality of sections, forming a second insulating film around a sidewall of the sections of the first wiring layer, forming a first interlayer insulating film over the product resulting from the previous step, simultaneously forming a first contact hole reaching the semiconductor substrate and a second contact hole reaching the first wiring layer, forming a second wiring layer over the product resulting from the previous step, forming a second interlayer insulati

Abstract: A semiconductor device and a wiring therefor and a fabrication method thereof are disclosed, which are capable of providing a good current driving capability without degrading the characteristic of the semiconductor device by overcoming the problems encountered in the known semiconductor device, and a wiring is implemented by using e semiconductor device fabricated in accordance with the present invention.

Abstract: A method for forming a metal silicide layer. There is first provided a substrate. There is then formed over the substrate a silicon layer, where the silicon layer has other than an amorphous silicon surface. There is then annealed thermally the silicon layer at a temperature greater than a silicidation temperature for forming a metal silicide layer upon the silicon layer to thus form from the silicon layer a thermally annealed silicon layer. Finally, there is then deposited upon the thermally annealed silicon layer a metal silicide forming metal while employing a metal deposition method such that upon contact with the thermally annealed silicon layer the metal silicide forming metal reacts in-situ to form a metal silicide layer upon a partially consumed thermally annealed silicon layer formed from the thermally annealed silicon layer.

Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: A process is set forth for providing a self-aligned, vertical bipolar transistor. A controlled technique is provided for providing the base and emitter features of the transistor with appropriate dimensions and properties to be useful in high frequency microwave applications. A microwave transistor is provided by this technique.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: A method for forming a contact plug. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening that exposes a thin layer of native oxide. A first and a second conformal doped polysilicon layer are formed over the opening. The first doped polysilicon layer has a dopant concentration greater than that of the second doped polysilicon layer. A third doped polysilicon layer that also fills the opening is formed over second doped polysilicon layer. Dopant concentration of the third doped polysilicon layer is smaller than the second doped polysilicon layer. Last, the first, the second and the third doped polysilicon layer are annealed.

Abstract: A method of forming a metal seed layer, preferably a copper layer, for subsequent electrochemical deposition. The metal seed layer is formed by the oxidation-reduction reaction of a metal salt with a reducing agent present in a layer on the substrate to be plated. Metal interconnects for semiconductor devices may be produced by the method, which has the advantage of forming the metal seed layer by a simple electrochemical plating process that may be combined with the plating of the interconnect itself as a single-bath operation.

Abstract: A method for reducing salicide lateral growth. A substrate having a gate structure and an anti-reflection layer on the gate structure is provided. A spacer is formed on the side wall of the gate structure and the anti-reflection layer. Then, the anti-reflection layer is removed to expose the gate structure; wherein the gate structure and the spacers together form a recess structure. A salicide layer is formed on the gate structure in the recess structure and on the substrate.

Abstract: This invention provides a method for forming a self aligned contact plug with low contact resistance in a semiconductor device using a two step process of (1) forming a high temperature polysilicon film and (2) forming a furnace doped polysilicon layer. The process begins by providing a substrate structure, having a first gate structure and a second gate structure thereon and having a contact area between the first gate structure and the second gate structure. An inter level dielectric layer is formed over the first gate structure and the second gate structure. The interlevel dielectric layer is patterned to form a self aligned contact opening over the contact area. Impurity ions are implanted into the substrate structure through the self aligned contact opening to form source and drain regions. In the key steps, a high temperature polysilicon film is formed over the source and drain regions, and a furnace doped polysilicon layer is formed over the high temperature polysilicon film.

Abstract: In a method for manufacturing a semiconductor device, a first insulating layer is formed on a semiconductor substrate, and a gate electrode is formed on the first insulating layer. Then, a second insulating layer is formed over the gate electrode. The second insulating layer has a high ability to stop the diffusion of hydrogen atoms therethrough. Then, hydrogen passivation is performed upon an interface between the semiconductor substrate and the first insulating layer at a first temperature. Then, a metal wiring layer is formed over the insulating layer, and the metal wiring layer is heated at a second temperature lower than the first temperature.

Abstract: Planarized polycide structures and methods for making the same. One embodiment includes a semiconductor structure having an irregular upper surface caused, for example, by the presence of field oxide surrounding an active region of an FET. A layer of polysilicon is located over the irregular upper surface of the semiconductor structure. The polysilicon layer has a substantially flat upper surface. A metal silicide layer is located over the flat upper surface of the polysilicon layer to form a polycide structure. This planarized polycide structure can be used, for example, as a gate electrode in an FET. In another embodiment, the planarized polycide structure includes a first polysilicon layer located over a semiconductor substrate. The polysilicon layer has an irregular upper surface.

Abstract: A method of forming a gate electrode in a semiconductor device which can easily perform gate re-oxidation process without transforming the morphology of the gate electrode, is disclosed. According to the present invention, a gate oxide layer, a doped polysilicon layer, a barrier metal layer and a refractory metal layer are formed on a semiconductor substrate, in sequence. A hard mask is then formed on the refractory metal. Next, the refractory metal layer, the barrier metal layer and the polysilicon layer are etched using the hard mask as an etch mask to form a gate electrode. A spacer for oxidation barrier is then formed on the side wall of the gate electrode and the hard mask. Thereafter, gate re-oxidation process is performed using the spacer as an oxidation mask to form a re-oxidation layer on the substrate of both sides of the spacer. The spacer is formed of a nitride layer such as a SiON layer or a Si4N3 layer. Furthermore, the spacer is formed to the thickness of 50 to 300 Å.

Abstract: A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area conductive structures of thin spacer width pillars or having edges without sharp corners that lead to electric field breakdown of the high dielectric constant material. The combination of high dielectric constant material in a memory cell along with a relatively large surface area conductive structure is achieved through the use of a buffer material as caps on the thin edge surfaces of the relatively large surface area structures to dampen or eliminate the intense electric field which would be generated at the corners of the conductive structures during the operation of the memory cell capacitor had the caps not been present.

Abstract: Insulated electrodes are formed by first forming on an integrated circuit substrate, an insulating layer, a conductive layer on the insulating layer, and a metal silicide layer on the conductive layer, and then forming a metal silicon nitride layer on the metal silicide layer. The metal silicon nitride layer acts as a silicon protrusion-preventing layer on the metal silicide layer that prevents formation of silicon protrusions from the metal silicide layer during subsequent processing. Reliability and/or yield problems that are caused by undercutting of an insulation layer in an insulated electrode may also be reduced by forming on an integrated circuit substrate, an insulating layer, conductive layer on the insulating layer and a metal silicide layer on the conductive layer.

Abstract: The present invention is a method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the gate having low resistivity. The MOSFET has a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and the MOSFET initially has a gate comprised of a first metal silicide on polysilicon disposed on a gate dielectric over the channel region. Generally, the method of the present invention includes a step of depositing a first dielectric layer over the drain region, the source region, and the gate of the MOSFET. The present invention also includes steps of polishing down the first dielectric layer over the drain region and the source region, and of polishing down the first dielectric layer over the gate until the first metal silicide or the polysilicon of the gate is exposed.

Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for minimizing the localized mechanical stress problems that can occur when silicided polysilicon gates are used to fabricate narrow channel CMOS devices. The invention addresses the avoidance of typical stress-induced problems in polysilicon gates, such as non-uniform silicide (including bowing, thinning edges, etc.) and voids, which are becoming increasingly worse as gate lengths continue to be reduced. The key to this invention is to spread the highly detrimental mechanical stresses, in narrow silicided gates, over a larger vertical surface area. This is accomplished by using a thin/thick double polysilicon stack for the gate, whereby, the lower thin polysilicon gate layer is not silicided and the upper thick polysilicon layer is subsequently silicided. An insulating layer is used to prevent silicidation of the lower thin polysilicon gate, during silicidation of active source-drain regions.

Abstract: The invention encompasses a semiconductor processing method of depositing polysilicon. A substrate is provided. The substrate comprises a first material and a second material which join at a junction, and which are different from one another. The substrate is exposed to a SiH4-comprising source gas to form a nucleation layer consisting of Si. After the exposing, a polysilicon layer is chemical vapor deposited atop the nucleation layer.

Abstract: A method for forming a multilevel interconnection between a polycide layer and a polysilicon layer is disclosed. The multilevel interconnection comprises: forming a first impurity-containing conductive layer on a semiconductor substrate; forming a first silicide layer, having a first region thinner than a second region, on the first impurity-containing conductive layer; forming an interlayer dielectric layer in other than the first region; forming a contact hole for exposing the first silicide layer of the first region; and connecting a second impurity-containing conductive layer to the first silicide layer through the contact hole.

Abstract: A method of fabricating a self-align-contact is provided. A first gate and a second gate are formed on a semiconductor substrate. A spacer is formed on the sidewalls of the first gate and the second gate, and a source/drain region is formed between the first gate and the second gate. A dielectric layer is formed on the first gate, the second gate, the source/drain region, the spacer, and the semiconductor substrate. A self-align-contact opening is formed in the dielectric layer to expose the source/drain region. A metal silicide layer is formed on the source/drain region. A first conductive layer, such as doped polysilicon, is formed on the metal silicide layer and in the self-align-contact opening. A second conductive layer is formed on the first conductive layer, and the first conductive layer and the second conductive layer are patterned.

Abstract: A method for fabricating a type of bit line is able to form a small-sized bit line. In this method a first dielectric layer, a first conductive layer, and a second conductive layer are formed on a substrate in sequence. The first dielectric layer is exposed, then a second conducting wire and a first conducting wire are formed, respectively. A portion of the second conducting wire is removed by a cleaning liquid, so that the feature size of the second conducting wire is less than the feature size of the first conducting wire. An oxide layer is formed on the second conducting wire and the first conducting wire by performing a thermal treatment. The feature size of the second conducting wire is approximately equal to the feature size of the first conducting wire.

Abstract: Gate electrodes for integrated circuit field effect transistors are fabricated by forming a polysilicon layer on a gate insulating layer opposite an integrated circuit substrate, forming an amorphous impurity layer on the polysilicon layer opposite the gate insulating layer, and forming an amorphous silicon layer on the amorphous impurity layer opposite the polysilicon layer. The amorphous silicon layer, the amorphous impurity layer and the polysilicon layer are patterned to define a gate electrode pattern. The polysilicon layer, the amorphous impurity layer and the amorphous silicon layer then are converted into a polysilicon gate having a first surface adjacent the gate insulating layer, a second surface opposite the gate insulating layer, and a buried doped layer within the polysilicon gate electrode that is spaced apart from the first and second surfaces thereof. The converting preferably takes place by thermally treating the gate electrode pattern.

Abstract: A retardation layer of a copper damascene process and the fabrication method thereof, to replace the conventional barrier layer with a laminated layer. The laminated layer combines the conventional barrier layer with a porous layer, wherein the porous layer can be formed either above or below the barrier layer to improve the retardation of the copper atom diffusion. Preferably, the porous layer is formed above the barrier layer.

Abstract: A method is disclosed for forming a low resistance poly landing pad which is achieved by shunting the polysilicon of a landing pad with metallic conductors. A window is opened through a first dielectric layer to expose a conducting region over a semiconductor substrate. A metallic layer, deposited overall, is followed by an overall deposition of a polysilicon layer, with the layers being sufficient to fill the window completely. Metal and polysilicon outside the window is removed by chemical/mechanical polishing which also provides global planarization. Salicidation provides a silicide cover over the exposed surface of polysilicon, which was formed by the polishing. A second dielectric is deposited and an opening is formed to the landing pad.

Abstract: A method for producing a low-impedance contact between a metallizing layer and a semiconductor material of a first conductivity type having a semiconductor surface, an insulation layer on the semiconductor surface and a semiconductor layer on the insulation layer, includes applying a first insulating layer with a predetermined content of dopants on the semiconductor layer, and structuring the first insulating layer by anisotropic etching, forming first and second openings. The semiconductor layer is anisotropically etched by using the first insulating layer as a mask. A first dopant of a second conductivity type is implanted and driven through the first opening into the semiconductor material with a first phototechnique, forming a first zone in the semiconductor material. A second dopant of the first conductivity type is implanted through the second opening into the semiconductor material with a second phototechnique. A second doped insulating layer is applied over the entire surface.

Abstract: A semiconductor apparatus having at least a compound film containing nitrogen and a method for production of the same, wherein the compound film containing nitrogen is formed under conditions where the ratio of the flow rates of the nitrogen with respect to an inert gas is 0.125 to 1.0.

Abstract: A semiconductor topography including integrated circuit gate conductors incorporating dual polysilicon layers is provided. The semiconductor topography includes a semiconductor substrate. A first gate conductor is arranged upon a first gate dielectric and above the semiconductor substrate, and a second gate conductor is arranged upon a second gate dielectric and above the semiconductor substrate. The semiconductor substrate may contain a first active region laterally separated from a second active region by a field region. The first gate conductor may be arranged within the first active region, and the second gate conductor may be arranged within the second active region. Each gate conductor preferably includes a second polysilicon layer portion arranged upon a first polysilicon layer portion. The thicknesses of the first gate conductor and the second gate conductor are preferably equal.

Abstract: The present invention relates to a method of formation of an Si.sub.1-x Ge.sub.x MOS transistor gate where x is higher than 50%, on an silicon oxide gate insulator layer, consisting of depositing an Si.sub.1-y Ge.sub.y layer of thickness lower than 10 nm, where 0<y<30%; and depositing an Si.sub.1-z Ge.sub.z layer of desired thickness, where z>50%. The desired thickness ranges, for example, between 20 nm and 200 nm. x and z range, for example, between 80% and 90%.

Abstract: A method for producing a MIS structure on silicon carbide is provided. Given application of a known CVD method for occupying the surface of a SiC substrate provided with a gate oxide with the silicon serving as gate material, stationary positive charges arise in the region of the oxide/SiC boundary surface whose extremely high effective density (Q.sub.tot >10.sup.12 cm.sup.-2) disadvantageously influences the electrical properties of the finished component. The present method modifies the deposition conditions for the silicon serving as a gate material. Thus, the silicon is deposited from the vapor phase at a temperature of T<580.degree. C. and is thus amorphously applied. During the subsequent doping (drive-in of phosphorous at T>800.degree. C.), the amorphous silicon converts into the polycrystalline condition.

Abstract: A method of forming a contact in a thin film transistor with a gate electrode and an interconnect formed on a substrate, in an SRAM device comprises the following steps. Form a gate oxide layer over device. Form a split amorphous silicon layer over gate oxide layer. Form a cap layer over split amorphous silicon layer. Form a contact opening down to interconnect. Form contact metallization in opening on the surface of interconnect either as a blanket titanium layer followed by rapid thermal anneal to form a silicide and stripping unreacted titanium or by selective formation of a tungsten metal silicide in the opening. Strip cap layer from device. Form a second amorphous silicon layer on split silicon layer. Recrystallize silicon layers to form a polysilicon channel layer from amorphous silicon layers. Dope regions of polysilicon channel layer aside from a channel region above gate electrode.

Abstract: A method for forming a polycide-gate structure is disclosed. The method comprises forming a gate oxide layer on a substrate. Then a polysilicon layer is formed on the gate oxide layer. Next a silicide layer is formed over the polysilicon layer. Thereafter, an amorphous silicon layer is formed on the silicide layer. Then, the amorphous silicon layer, the silicide layer, the polysilicon layer and the gate oxide layer are patterned and etched to define a gate region by using a photoresist mask. Source/drain regions are formed using the gate region as an implant mask. Finally, a cap silicon nitride layer is formed over the amorphous silicon layer.

Abstract: A method of fabricating a gate having a barrier layer of titanium silicide is comprised of the steps of forming a layer of gate oxide. The gate oxide may be formed using a standard LOCOS process. A layer of doped polysilicon is deposited over the layer of gate oxide. A layer of titanium silicide is formed in a predetermined relationship with respect the layer of doped polysilicon, i.e., it may be deposited on top of the polysilicon or formed in a top surface of the polysilicon layer. A layer of tungsten silicide is deposited on top of the layer of titanium silicide. The layers of gate oxide, doped polysilicon, titanium silicide, and tungsten silicide are etched to form the gate. A gate thus fabricated is also disclosed.

Abstract: A method of forming a poly-silicide gate electrode (102). The polysilicon deposition is broken into two steps. After the first polysilicon layer (102a) is formed, a very thin oxide (102b) is formed thereover. Polysilicon deposition then continues to form a second polysilicon layer (102c). The oxide layer (102b) inhibits grain growth resulting in a smaller grain size for the second polysilicon layer (102c). Prior to silicide formation, a pre-amorphization implant is performed to amorphize the second polysilicon layer (102c) and possibly some of the first polysilicon layer (102a) as well. Titanium is deposited and reacted with the polysilicon layers to form a silicide. The silicide process consumes the interface between polysilicon layers (102a & 102c) and possibly a portion of the first polysilicon layer (102a). The resulting silicide layer has a more uniform sheet resistance.