Abstract: An improved self-aligned silicide manufacturing method in which prior to the formation of a heat resistant metallic layer on top of a silicon substrate, a treatment of exposed surfaces of a gate terminal and source/drain diffusion regions is performed to increase surface roughness enabling an increase in crystallization nucleus number, as well as lowering crystallization temperature.

Abstract: In order to form an ohmic contacts to both the n+ and the p+ doped regions of complementary metal oxide semiconductor substrate regions of the an integrated circuit device, wells (contact holes) are formed in the insulating using a hard mask poly-Si layer on an insulating region exposing the doped substrate regions. A TiSi.sub.x layer is formed on the walls and base of the well either by physical vapor deposition or is formed by combining a layer of poly-Si with a layer of Ti. The TiSi.sub.2 is diffused into the doped region during an annealing step. In addition, the TiSi.sub.2 layer is converted into the low resistivity C54 configuration in an annealing step.

Abstract: The method of this invention produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented method includes the steps of producing an amorphous region on the silicon body using ion implantation, for example, forming or positioning a metal such as titanium, cobalt or nickel in contact with the amorphous region, and irradiating the metal with intense light from a laser source, for example, to cause metal atoms to diffuse into the amorphous region. The amorphous region thus becomes an alloy region with the desired silicide composition. Upon cooling after irradiation, the alloy region becomes partially crystalline. To convert the alloy region into a more crystalline form, the invented method preferably includes a step of treating the alloy region using rapid thermal annealing, for example.

Abstract: A method of forming a buried contact junction without forming a buried contact trench and without a disconnection gap in the current path by using a tapered polysilicon profile and a large angle tilt buried contact implant is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate wherein the first polysilicon layer is tapered such that the bottom of the opening has a width the size of the planned buried contact and wherein the top of the opening has a width larger than the size of the planned buried contact. Ions are implanted at a tilt angle into the substrate within the opening whereby the ions penetrate the substrate laterally underlying with said first polysilicon layer to form the buried contact.

Abstract: An intentionally undoped amorphous silicon layer, a phosphorous doped amorphous silicon layer and a tungsten silicide layer are successively laminated on a gate oxide layer, and are patterned into a gate electrode of a field effect transistor; while a phosphosilicate glass layer over the gate electrode is being reflowed, the amorphous silicon layers are crystallized to a polysilicon layer, and phosphorous is less segregated at the boundary between the gate oxide layer and the polysilicon layer during the heat treatment.

Abstract: A method of forming self-aligned silicide devices which includes providing a silicon substrate having shallow trench isolation regions for defining a device area formed therein; then, forming sequentially a gate oxide layer, a polysilicon layer, a first titanium nitride layer, a titanium silicide layer, a second titanium nitride layer and a silicon nitride layer over the substrate. After a gate electrode is etched out from the above layers, a titanium layer is deposited over the device, and then a self-aligned titanium silicide layer is formed using a heating process.

Abstract: A manufacturing method of fabricating a polysilicon conductive wire suitable for an integrated circuit and which can avoid pattern transfer errors caused by reflection of ultraviolet light during photolithographic processing and that results in constriction in width or the bottlenecking effect in part of the conductive wore. A polysilicon layer is formed above a semiconductor substrate having a preformed device. A cap insulting layer is formed above the polysilicon layer. A micro-roughness structure is formed on the surface of the cap insulating layer. A photoresist layer is coated over the micro-roughened surface of the cap insulating layer. A pattern is transferred onto the photoresist layer by selective light exposure followed by the removal of unexposed photoresist. Then the cap insulating layer and the polysilicon layer are etched in sequence in regions not covered by photoresist. The residual photoresist is then removed to leave behind a polysilicon conductive wire.

Abstract: The present invention provides a method of forming an oxide dielectric layer on a tungsten silicide gate structure in a furnace oxidation process by first depositing a thin layer of amorphous silicon on top of the refractory metal silicide gate structure such that the refractory metal silicide is not damaged by the oxidant during the furnace oxidation process. For a tungsten silicide gate structure, a thin layer of amorphous silicon between about 10 .ANG. and about 100 .ANG. thick can be suitably used for such purpose.

Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion.

Abstract: This is a method of forming an SRAM transistor cell on a well in a doped semiconductor substrate. Form a gate oxide layer and a split gate layer with buried contact regions in the well and openings through the split gate layer and the gate oxide layer to the well. Form an intermediate conductor layer and a hard silicon oxide mask layer and define gate conductors. Form lightly doped source/drain regions, form spacers and source/drain regions in the well. Form a first inter-conductor dielectric layer on the cell. Define a self-aligned contact region in the cell above source/drain regions. Form a second conductor layer over the cell and patterning the second conductor layer to form a via in the self-aligned contact region. Form a second inter-conductor dielectric layer on the cell, a third conductor layer over the cell and patterning the third conductor layer to form a first resistor connected to the self-aligned contact region.

Abstract: A method of forming a polycide thin film. First, a silicon layer is formed. Next, a thin barrier layer is formed on the first silicon layer. A second silicon layer is then formed on the barrier layer. Next, a metal layer is formed on the second silicon layer. The metal layer and the second silicon layer are then reacted together to form a silicide.

Abstract: A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

Abstract: A method for patterning a polysilicon layer includes creating a TiN layer above an amorphous silicon (a-Si) layer forming a TiN/a-Si stack. The TiN/a-Si stack is formed above the polysilicon layer. The TiN layer serves as an ARC to reduce overexposure of the photoresist used to pattern the polysilicon layer, while the a-Si layer prevents contamination of the layer below the polysilicon layer.

Abstract: A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer on the surface of a substrate, forming a second undoped layer on the doped layer, while maintaining the work piece under a vacuum environment, moving the substrate to a second chamber and thereafter forming a silicide containing layer on the undoped polysilicon layer. Various techniques may be used to deposit either the polysilicon or the silicide layer such as sputtering may also be used. Practice of the method eliminates separation of silicide from polysilicon and increases product yield.

Abstract: A process has been developed which allows contact between levels of interconnect metallization structures, to occur without the use of via holes, etched in interlevel insulator layers. The process features creation of a raised tungsten plug structure, used to provide contact between underlying active device regions and an overlying interconnect metallization structure. The tungsten plug structure is formed by photolithographic masking and dry etching procedures, thus avoiding increasing the size of a tungsten seam, in the center of the plug structure. In addition the tungsten definition process, also results in a raised plug structure, allowing subsequent contact of interconnect metallization levels to proceed without the use of etched via holes in interlevel insulator layers.

Abstract: A semiconductor device including a bipolar transistor is provided, which can reduce the base resistance of the transistor. This device includes a semiconductor base region having a first semiconductor active region of a first conductivity type in its inside. A first insulating layer is formed on the main surface of the substructure to cover the first active region. The first insulating layer has a first penetrating window exposing the first active region. A semiconductor contact region of a second conductivity type is formed on the first insulating layer. The contact region has an overhanging part which overhangs the first window. The second window is defined by the inner end of the overhanging part to be entirely overlapped with the first window. The contact region is made of a polycrystalline semiconductor. A second semiconductor active region of the second conductivity type is formed on the first active region in the first window.

Abstract: A method for forming an interconnect of a semiconductor device including the steps of: sequentially forming an interlevel insulating layer and auxiliary layer on a substrate supporting a lower conductive line; doping impurity ions into the auxiliary layer, and selectively removing the auxiliary layer and interlevel insulating layer to thereby form a contact hole sufficient to the lower conductive line; and depositing and growing a conductive material in the contact hole and on the auxiliary layer to thereby form an upper conductive line.

Abstract: A uniformly doped polysilicon gate electrode of an MOS device forming a part of an integrated circuit structure on a semiconductor substrate is formed by first depositing a very thin layer of amorphous or polycrystalline silicon, e.g., from about 2 nm to about 10 nm, over a gate oxide layer. The thin layer of silicon layer is then exposed to a nitrogen plasma formed from N.sub.2 at a power level sufficient to break the silicon--silicon bonds in the thin layer of silicon, but insufficient to cause sputtering of the silicon to cause a barrier layer of silicon and nitrogen to form at the surface of the thin silicon layer. Further silicon, e.g., polysilicon, is then deposited over the barrier layer to the desired thickness of the polysilicon gate electrode. The gate electrode is then conventionally doped, i.e.

Abstract: A method of forming an MOS gate includes providing a silicon substrate having a gate oxide formed thereon, forming a polysilicon layer on the gate oxide, defining a gate area including forming an oxide mask by positioning a light mask adjacent a surface of the polysilicon layer and exposing the surface through the light mask to a deep ultra violet light in an ambient containing oxygen. A layer of metal is deposited and annealed to form a silicide only where the layer of metal and polysilicon layer are in contact. The remaining metal layer and mask are removed, using the silicide as a mask, wherein the remaining polysilicon and the silicide form an MOS gate. Sidewall spacers are formed on opposing sides of the MOS gate and used in forming self aligned source and drain regions.

Abstract: A buried interconnect structure which is stable at the high temperatures involved in BiCMOS, bipolar, and CMOS transistor process flows, and a method of making the same. The interconnect structure is fully insulated and can be used to form stable, doped structures suitable for use as electrodes and gate structures in a CMOS process, or to form low resistance contacts to N or P-type silicon as part of a bipolar process. Because the interconnect structure is buried and fully insulated from surrounding structures, it may be used to form complex, multi-level devices having a minimized geometry and increased circuit density.

Abstract: The present invention provides a method of fabrication for semiconductor devices which enables a photolithography technique in a fabrication process to have a maximal effect on the transistor characteristics. Polysilicon film 16 and silicon nitride film 17 are formed to active transistor 11 and field shield isolation transistor 12, with isotropic etching of silicon nitride film 17 carried out using a resist pattern 20 which was patterned within the minimum processing width as the mask. Then, using the pattern of silicon nitride film 17 as a mask, thermal oxidation of polysilicon film 16 is carried out. Next, after eliminating silicon nitride film 17, anisotropic etching of polysilicon film 16 is carried out using silicon oxide film 21 as a mask, silicon oxide film 21 being formed by thermal oxidation of polysilicon film 16. In this way, a contact pad 22 formed of polysilicon film 16 is completed.

Abstract: A method is provided for forming silicide surfaces on source, drain, and gate electrodes in active devices to decrease the resistance of the electrode surfaces, without consuming the silicon of the electrodes in the process. Silicide is directionally deposited on the electrodes so that a greater thickness accumulates on electrode surfaces, and a lesser thickness accumulates on the gate sidewall surfaces isolating the gate from the source/drain electrodes. Then, the electrodes are isotropically etched so that the lesser thickness on the sidewalls is removed, leaving at least some thickness of silicide covering the electrodes. In further steps, the electrodes are masked with photoresist, and any silicide deposited in the region of field oxide around the electrodes is removed.

Abstract: The present invention provides a method for preventing a polycide line situated between two poly-metal dielectric layers from drifting or deformation during a reflow process conducted for the dielectric layers by forming a dummy polycide gate and a dummy contact at a suitable location in the polycide line such that the dummy contact is anchored through the bottom dielectric layer to a dummy gate located on a field oxide isolation in the silicon substrate. The number of dummy contacts and the location for placing such contacts are determined by the length and the configuration of the polycide line and the topography of the dielectric layer that the polycide line is situated on.

Abstract: A method of fabricating a gate having a barrier layer of titanium silicide is comprised of the steps of forming a layer of gate oxide. The gate oxide may be formed using a standard LOCOS process. A layer of doped polysilicon is deposited over the layer of gate oxide. A layer of titanium silicide is formed in a predetermined relationship with respect the layer of doped polysilicon, i.e., it may be deposited on top of the polysilicon or formed in a top surface of the polysilicon layer. A layer of tungsten silicide is deposited on top of the layer of titanium silicide. The layers of gate oxide, doped polysilicon, titanium silicide, and tungsten silicide are etched to form the gate. A gate thus fabricated is also disclosed.

Abstract: A method is described for making an array of dynamic random access memory (DRAM) cells having both a trench and a stacked capacitor within each cell. The method involves forming a trench in the silicon substrate at the capacitor node contact area of the DRAM cell, and depositing an N+ doped polysilicon layer to form an N+/P diode capacitor in the trench. Another N+ doped polysilicon layer is deposited and anisotropically etched back over a patterned silicon nitride/silicon oxide layer in the trench areas to form the bottom electrodes of stacked capacitors with vertically extending sidewalls. An interelectrode dielectric layer is formed on the bottom electrodes and top electrodes are formed from a patterned N+ doped polysilicon layer to complete the array DRAM trench/stacked capacitors. The trench diode capacitor electrically connected in parallel with the stacked capacitor increase the cell capacitance. The vertical extensions on the stacked capacitor further increase the capacitance of the DRAM cell.

Abstract: A method for forming a residue free patterned polysilicon layer upon a high step height patterned substrate layer. First, there is provided a semiconductor substrate having formed thereon a high step height patterned substrate layer. Formed upon the high step height patterned substrate layer is a polysilicon layer, and formed upon the polysilicon layer is a patterned photoresist layer. The patterned photoresist layer exposes portions of the polysilicon layer at a lower step level of the high step height patterned substrate layer. The polysilicon layer is then patterned through the patterned photoresist layer as an etch mask employing an anisotropic first etch process to yield a patterned polysilicon layer upon the surface of the high step height patterned substrate layer and polysilicon residues at the lower step level of the high step height patterned substrate layer.

Abstract: A method for forming a structure of a split gate flash memory is provided. The method includes steps of: a) preparing a substrate having an oxide layer; b) forming a first conducting layer over the oxide layer; c) etching a portion of the first conducting layer to form a word line structure for the flash memory; d) forming a spacer layer over the word line structure to be a side-wall portion of a word-line protecting layer; e) oxidizing the word-line protecting layer to form a dielectric layer; and f) forming a floating gate layer over the dielectric layer.

Abstract: According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers. According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage.

Abstract: A multilayer structure having an oxygen or dopant diffusion barrier fabricated of an electrically conductive, thermally stable material of refractory metal-silicon-nitrogen which is resistant to oxidation, prevents out-diffusion of dopants from silicon and has a wide process window wherein the refractory metal is selected from Ta, W, Nb, V, Ti, Zr, Hf, Cr and Mo.

Abstract: A semiconductor processing method of forming a buried contact to a substrate region includes, a) providing a stress relief layer over a bulk semiconductor substrate; b) etching the stress relief layer to expose a desired buried contact area of the substrate; c) masking over the stress relief layer and over the desired buried contact area; d) with the masking in place, exposing the substrate to oxidation conditions effective to grow field oxide regions in unmasked areas of the substrate; e) after forming the field oxide regions, removing the masking from the substrate and effectively leaving the buried contact area exposed; f) providing a layer of electrically conductive material over field oxide and exposed buried contact area; and g) patterning the conductive material layer into a conductive line which overlies both field oxide and the buried contact area.

Abstract: A semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening includes, a) providing a node location and a plug molding layer outwardly thereof; b) providing a contact opening through the plug molding layer to the node location; c) providing a first layer of semiconductive material over the molding layer to within the contact opening, the first layer thickness being less than one-half the contact opening width to leave a first remaining opening, the first layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; d) after providing the first layer, increasing the average conductivity enhancing dopant concentration of the first layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.

Abstract: An method for the formation of polycide used for the gate electrode or interconnection metallization in semiconductor integrated circuit devices has been developed. The polycide is formed from doped amorphous silicon deposited from SiH.sub.4 and PH.sub.3 and tungsten silicide deposited from dichlorosilane (SiH.sub.2 Cl.sub.2 and WF.sub.6, followed by conventional RIE patterning. The key feature, annealing of the polycide structure by a combination of RTA (Rapid Thermal Anneal) in a nitrogen ambient, and then a furnace anneal in an oxygen ambient prevents deleterious sidewall growth on the polycide structure and results in a highly manufacturable process having high yield.

Abstract: Fabricating a DRAM memory cell with increased capacitance by increasing the surface area of a storage electrode of a storage capacitor includes forming transfer transistor having a gate electrode and source-drain electrode areas on a semiconductor substrate. First, second and third insulating layers are formed in sequence on the semiconductor substrate and the transfer transistor. The third, second and first insulating layers are selectively etched through to form a contact opening exposing one of the source-drain electrode areas as a contact area. An upper portion of the third insulating layer is etched to form a plurality of first trenches. A first conductive layer is formed over the insulating layer filling the contact opening and the first trenches. An upper portion of the first conductive layer is etched to form a plurality of second trenches, and selectively etched to define a pattern area of a storage electrode of a capacitor.

Abstract: The present invention discloses a method for forming a tungsten silicide layer in a semiconductor device. A wafer to be deposited with a tungsten silicide layer is loaded into a chamber. The tungsten silicide layer is primarily deposited, thinner than desired in the device by a Chemical Vapor Deposition utilizing WF.sub.6 and SiH.sub.4 gases. The fluorine contained in the primarily deposited tungsten silicide layer is removed by introducing a large quantity of SiH.sub.4 gas into the chamber. Again the tungsten silicide layer is secondarily deposited, thinner than desired in the device, on the tungsten silicide layer from which the fluorine is removed and, thereafter, the fluorine contained in the secondarily deposited tungsten silicide layer is removed by introducing a large quantity of SiH.sub.4 gas. Such a process is repeated until the tungsten silicide layer of the thickness desired in the device is deposited.

Abstract: In a method for fabricating a ULSI MOSFET with SOI structure, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

Abstract: This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening.

Abstract: A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a storage node electrode, for the STC structure, consisting of an upper polysilicon shape, comprised of polysilicon columns, with a narrow space between polysilicon columns, and an underlying lower polysilicon shape, residing in a contact hole, and making contact to underlying transistor regions. The polysilicon columns, and the narrow space, between polysilicon columns are formed via creation of a narrow trench in a top portion of a polysilicon layer, followed by an anisotropic etch to create the exterior shape of the storage node electrode. A key feature of this invention is the use of a photoresist plug, in the trench, used to protect the lower portion of the storage node electrode during the exterior shape, patterning process.

Abstract: A new method of forming improved buried contact junctions is described. A first layer of polysilicon is deposited overlying a gate silicon oxide layer on a semiconductor substrate. These layers are etched away to provide an opening to the semiconductor substrate where the planned buried contact junction will be formed. A second polysilicon layer is deposited overlying the first polysilicon layer and the planned buried contact junction. Dopant is driven in from the second polysilicon layer to form the buried contact junction. The second polysilicon layer is etched away to provide a polysilicon contact overlying the buried contact junction and providing an opening to the semiconductor substrate where a planned source/drain region will be formed adjacent to the buried contact junction wherein a portion of the second polysilicon layer remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the buried contact junction.

Abstract: A method for fabricating conductive structures in integrated circuits. A conductive layer is formed over an underlying region in an integrated circuit. The conductive layer is then doped with impurities, and a thin amorphous silicon layer is formed over the conductive layer. A photoresist layer is then deposited and exposed to define a masking pattern. During exposure of the photoresist layer, the amorphous silicon layer acts as an anti-reflective layer. Portions of the photoresist layer are then removed to form a masking layer, and the insulating layer and amorphous silicon layer are then etched utilizing the masking layer to form conductive structures. During subsequent thermal processing, impurities from the conductive layer diffuse into the amorphous silicon layer causing the amorphous silicon layer to become conductive.