Utilizing Laser Patents (Class 438/662)
  • Patent number: 5840627
    Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with standard precision masking techniques to define all possible connections, vias or cut-points, and 2) using a non-precision targeting energy beam to select the desired connections, vias or cut-points for customization. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: November 24, 1998
    Assignee: Clear Logic, Inc.
    Inventor: Alan H. Huggins
  • Patent number: 5827775
    Abstract: Phase mask laser machining procedures for fabricating high density fine pattern feature electrical interconnection structures. Conductor patterns are fabricated using a phase mask laser patterned dielectric layer as a conductor wet etch masking layer, or by subtractively removing metal using holographic phase mask laser micromachining. In accordance with the present invention, a substrate is provided, a first layer of dielectric material is formed on the substrate, a metal layer is formed on the first layer of dielectric material, and a second layer of dielectric material is then formed on the metal layer. A phase mask is disposed above the second layer of dielectric material that has a predefined phase pattern therein defining a metal conductor pattern that corresponds to an interconnect structure. The second layer of dielectric material is then processed using the phase mask to form the interconnect structure.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: October 27, 1998
    Assignee: Raytheon Comapny
    Inventors: Robert S. Miles, Philip A. Trask, Vincent A. Pillai
  • Patent number: 5633195
    Abstract: A method of laser planarizing metallic thin films minimizes the laser fluences required to melt or nearly melt the metalization. This is accomplished by reducing the optical reflectivity of the metallic lines and vias by using textured thin films. This reduction of optical reflectivity, in turn, reduces the minimum fluence needed to melt or nearly melt the metal using a laser, thus improving the process window and minimizing the damage to the surrounding media.
    Type: Grant
    Filed: September 22, 1995
    Date of Patent: May 27, 1997
    Assignee: International Business Machines, Corp.
    Inventors: William L. Guthrie, Naftali E. Lustig