Utilizing Laser Patents (Class 438/662)
  • Patent number: 9190275
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: November 17, 2015
    Assignee: SONY CORPORATION
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
  • Patent number: 9162254
    Abstract: A method for applying a coating (4) on a substrate (1), includes: —scanning a laser beam (2) along a line on the surface of said substrate. The method also includes supplying a coating forming material from a supply system (3), the system moving along the same line as the laser beam but coming up behind the laser beam, so that the coating forming material is deposited on a spot which has previously been heated by the laser beam to a temperature above the melting temperature of the coating forming material. Substantially no physical contact occurs between the laser beam and the coating forming material. Preferably, the method further includes a second step of scanning the surface a second time with the laser beam, without adding coating forming material during the second step.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: October 20, 2015
    Assignee: VLAAMSE INSTELLING VOOR TECHNOLOGISCH ONDERZOEK N.V. (VITO)
    Inventors: Rosita Persoons, Eric Geerinckx, Jan Gedopt
  • Patent number: 8984466
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 8928105
    Abstract: A method to fabricate monolithically-integrated optoelectronic module apparatuses (100) comprising at least two series-interconnected optoelectronic components (104, 106, 108). The method includes deposition and scribing on an insulating substrate or superstate (110) of a 3-layer stack in order (a, b, c) or (c, b, a) comprising: (a) back-contact electrodes (122, 124, 126, 128), (b) semiconductive layer (130), and (c) front-contact components (152, 154, 156, 158). Via holes (153, 155, 157) are drilled so that heat of the drilling process causes a metallization at the surface of said via holes that renders conductive the semi-conductive layer's surface (132, 134, 136, 138) of said via holes, thereby establishing series-interconnecting electrical paths between optoelectronic components (104, 106, 108) by connecting first front-contact components (154, 156) to second back-contact electrodes (124, 126).
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: January 6, 2015
    Assignee: Flisom AG
    Inventors: Roger Ziltener, Roland Kern, David Bremaud, Björn Keller
  • Patent number: 8865568
    Abstract: Fractures (17a, 17b) are generated from modified regions (7a, 7b) to front and rear faces (12a, 12b) of a object to be processed (1), respectively, while an unmodified region (2) is interposed between the modified regions (7a, 7b). This can prevent fractures from continuously advancing in the thickness direction of a silicon substrate (12) when forming a plurality of rows of modified regions (7). By generating a stress in the object (1), the fractures (17a, 17b) are connected to each other in the unmodified region (2), so as to cut the object (1). This can prevent fractures from meandering in the rear face (12b) of the object (1) and so forth, whereby the object (1) can be cut accurately along a line to cut the object (5).
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: October 21, 2014
    Assignee: Hamamatsu Photonics K.K
    Inventors: Takeshi Sakamoto, Aiko Nakagawa
  • Patent number: 8853590
    Abstract: A device for irradiating a laser beam onto an amorphous silicon thin film formed on a substrate. The device includes: a stage mounting the substrate; a laser oscillator for generating a laser beam; a projection lens for focusing and guiding the laser beam onto the thin film; a reflector for reflecting the laser beam guided onto the thin film; a controller for controlling a position of the reflector; and an absorber for absorbing the laser beam reflected by the reflector.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: October 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun-Jae Kim, Myung-Koo Kang
  • Patent number: 8835800
    Abstract: The present invention provides a laser irradiation apparatus which can accurately control positions of beam spots of laser beams emitted from laser oscillators and the distance between the adjacent beam spots. A laser irradiation apparatus of the present invention includes a first movable stage with an irradiation body provided, two or more laser oscillators emitting laser beams, a plurality of second movable stages with the laser oscillators and optical systems provided, and a means for detecting at least one alignment maker. The first stage and the second stages may move not only in one direction but also in a plurality of directions. Further, the optical systems are to shape the laser beams emitted from the laser oscillators into linear beams on the irradiation surface.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Yoshiaki Yamamoto
  • Patent number: 8802557
    Abstract: A method for forming a micro bump includes forming a first nano-particle layer on a substrate and forming a second nano-particle layer on the first nano-particle layer. The first and second nano-particle layers include a plurality of first nano particles and a plurality of second nano particles, respectively. The method further includes irradiating a laser beam onto the second nano-particle layer, where the laser beam penetrates through the second nano-particle layer and is at least partially absorbed by at least some of the first nano particles to generate heat. The first nano particles and the second nano particles have different absorption rates with respect to the laser beam.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: August 12, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Ruoh-Huey Uang, Yi-Ting Cheng
  • Patent number: 8772161
    Abstract: A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Gregory M. Fritz, Christian Lavoie, Conal E. Murray, Kenneth P Rodbell
  • Patent number: 8765525
    Abstract: A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 1, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: In Sang Yoon, DeokKyung Yang, Sungmin Song
  • Patent number: 8741749
    Abstract: The present invention relates generally to semiconductors, material layers within semiconductors, a production method of semiconductors, and a manufacturing arrangement for producing semiconductors. A semiconductor according to the invention includes at least one layer with a surface, produced by laser ablation, wherein the uniform surface area to be produced includes at least an area 0.2 dm2 and the layer has been produced by employing ultra short pulsed laser deposition wherein pulsed laser beam is scanned with a rotating optical scanner including at least one mirror for reflecting the laser beam.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: June 3, 2014
    Assignee: Picodeon Ltd Oy
    Inventors: Reijo Lappalainen, Vesa Myllymäki, Lasse Pulli, Jari Ruuttu, Juha Mäkitalo
  • Patent number: 8728914
    Abstract: Fractures (17a, 17b) are generated from modified regions (7a, 7b) to front and rear faces (12a, 12b) of a object to be processed (1), respectively, while an unmodified region (2) is interposed between the modified regions (7a, 7b). This can prevent fractures from continuously advancing in the thickness direction of a silicon substrate (12) when forming a plurality of rows of modified regions (7). By generating a stress in the object (1), the fractures (17a, 17b) are connected to each other in the unmodified region (2), so as to cut the object (1). This can prevent fractures from meandering in the rear face (12b) of the object (1) and so forth, whereby the object (1) can be cut accurately along a line to cut the object (5).
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: May 20, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Takeshi Sakamoto, Aiko Nakagawa
  • Patent number: 8697534
    Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 15, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Motohiko Sato, Kazuhiro Hayashi, Kenji Murakami, Motonobu Kurahashi, Yusuke Kaieda, Jun Otsuka, Manabu Sato
  • Patent number: 8679972
    Abstract: The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 25, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Robert Rozbicki, Michal Danek, Erich Klawuhn
  • Patent number: 8642458
    Abstract: A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Hong Chung, Young-Hee Kim, In-Sun Yi, Han-Mei Choi
  • Patent number: 8536054
    Abstract: Provided herein are methods of polishing and texturing surfaces thin-film photovoltaic cell substrates. The methods involve laser irradiation of a surface having a high frequency roughness in an area of 5-200 microns to form a shallow and rapidly expanding melt pool, followed by rapid cooling of the material surface. The minimization of surface tension causes the surface to re-solidify in a locally smooth surface. the high frequency roughness drops over the surface with a lower frequency bump or texture pattern remaining from the re-solidification.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: September 17, 2013
    Assignee: MIASOLE
    Inventors: Dallas W. Meyer, Jason Stephen Corneille, Steven Thomas Croft, Mulugeta Zerfu Wudu, William James McColl
  • Patent number: 8497450
    Abstract: A laser-based workpiece processing system includes sensors connected to a sensor controller that converts sensor signals into focused spot motion commands for actuating a beam steering device, such as a two-axis steering mirror. The sensors may include a beam position sensor for correcting errors detected in the optical path, such as thermally-induced beam wandering in response to laser or acousto-optic modulator pointing stability, or optical mount dynamics.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: July 30, 2013
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Kelly Bruland, Mark Unrath, Stephen Swaringen, Ho Wai Lo, Clint Vandergiessen, Keith Grant
  • Patent number: 8461011
    Abstract: The present disclosure relates to a method for manufacturing a back electrode-type solar cell. The method for manufacturing a back electrode-type solar cell disclosed herein includes: A method for manufacturing a back electrode-type solar cell, comprising: preparing an n-type crystalline silicon substrate; forming a thermal diffusion control film on a front surface, a back surface and a side surface of the substrate; forming a p-type impurity region by implanting p-type impurity ions onto the back surface of the substrate; patterning the thermal diffusion control film so that the back surface of the substrate is selectively exposed; and forming a high-concentration back field layer (n+) at an exposed region of the back surface of the substrate and a low-concentration front field layer (n?) at the front surface of the substrate by performing a thermal diffusion process, and forming a p+ emitter region by activating the p-type impurity region.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: June 11, 2013
    Assignee: Hyundai Heavy Industries Co., Ltd.
    Inventors: Min Sung Jeon, Won Jae Lee, Eun Chel Cho, Joon Sung Lee
  • Patent number: 8446924
    Abstract: In the case of a lens array type homogenizer optical system, the incident angle and intensity of a laser beam 1 entering a large-sized lens (long-axis condenser lens 22) of a long-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while long-axis lens arrays 20a and 20b are reciprocated in a direction corresponding to a long axial direction of a linear beam (X-direction). Therefore, vertical stripes are significantly reduced. Further, the incident angle and intensity of a laser beam 1 entering a large-sized lens (projection lens 30) of a short-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while short-axis lens arrays 26a and 26b are reciprocated in a direction corresponding to a short axial direction of a linear beam (Y-direction). Therefore, horizontal stripes are significantly reduced.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: May 21, 2013
    Assignee: IHI Corporation
    Inventors: Norihito Kawaguchi, Ryusuke Kawakami, Kenichiro Nishida, Miyuki Masaki, Masaru Morita
  • Patent number: 8426964
    Abstract: A method for forming a micro bump includes forming a first nano-particle layer on a substrate and forming a second nano-particle layer on the first nano-particle layer. The first and second nano-particle layers include a plurality of first nano particles and a plurality of second nano particles, respectively. The method further includes irradiating a laser beam onto the second nano-particle layer, where the laser beam penetrates through the second nano-particle layer and is at least partially absorbed by at least some of the first nano particles to generate heat. The first nano particles and the second nano particles have different absorption rates with respect to the laser beam.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: April 23, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Ruoh-Huey Uang, Yi-Ting Cheng
  • Patent number: 8361873
    Abstract: It is an object of the present invention is to provide a method of manufacturing an SOI substrate provided with a single-crystal semiconductor layer which can be practically used even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like, is used, and further, to manufacture a semiconductor device with high reliability by using such an SOI substrate. A semiconductor layer which is separated from a semiconductor substrate and bonded to a supporting substrate having an insulating surface is irradiated with electromagnetic waves, and the surface of the semiconductor layer is subjected to polishing treatment. At least part of a region of the semiconductor layer is melted by irradiation with electromagnetic waves, and a crystal defect in the semiconductor layer can be reduced. Further, the surface of the semiconductor layer can be polished and planarized by polishing treatment.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: January 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Ryota Imahayashi, Yoichi Iikubo, Kenichiro Makino, Sho Nagamatsu
  • Patent number: 8357598
    Abstract: The present invention provides an antenna with low resistance and a semiconductor device having an antenna whose communication distance is improved. A fluid containing conductive particles is applied over an object. After curing the fluid containing the conductive particles, the fluid is irradiated with a laser to form an antenna. As a method for applying the fluid containing the conductive particles, screen printing, spin coating, dipping, or a droplet discharging method is used. Further, a solid laser having a wavelength of 1 nm or more and 380 nm or less is used as the laser.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: January 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Daiki Yamada
  • Patent number: 8329556
    Abstract: A process for the fabrication of semiconductor devices on a substrate, the semiconductor devices including at least one metal layer. The process includes, removing the substrate and applying a second substrate; and annealing the at least one metal layer by application of a beam of electromagnetic radiation on the at least one metal layer.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: December 11, 2012
    Assignee: Tinggi Technologies Private Limited
    Inventors: Shu Yuan, Jing Lin
  • Publication number: 20120273936
    Abstract: A method for forming a micro bump includes forming a first nano-particle layer on a substrate and forming a second nano-particle layer on the first nano-particle layer. The first and second nano-particle layers include a plurality of first nano particles and a plurality of second nano particles, respectively. The method further includes irradiating a laser beam onto the second nano-particle layer, where the laser beam penetrates through the second nano-particle layer and is at least partially absorbed by at least some of the first nano particles to generate heat. The first nano particles and the second nano particles have different absorption rates with respect to the laser beam.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 1, 2012
    Inventors: Ruoh-Huey Uang, Yi-Ting Cheng
  • Patent number: 8298905
    Abstract: A method for forming a functional element includes a first step of forming an insulating layer composed of an insulator phase of a transition metal oxide serving as a metal-to-insulator transition material, the transition metal oxide being mainly composed of vanadium dioxide, and a second step of causing part of the insulating layer to transition to a metallic phase, in which the insulator phase differs from the metallic phase in terms of electrical resistivity and/or light transmittance.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: October 30, 2012
    Assignee: Sony Corporation
    Inventor: Daisuke Ito
  • Publication number: 20120164765
    Abstract: A method of forming an ohmic contact for a semiconductor device can be provided by thinning a substrate to provide a reduced thickness substrate and providing a metal on the reduced thickness substrate. Laser annealing can be performed at a location of the metal and the reduced thickness substrate at an energy level to form a metal-substrate material to provide the ohmic contact thereat.
    Type: Application
    Filed: March 12, 2012
    Publication date: June 28, 2012
    Inventors: David B. Slater, JR., John Edmond, Matthew Donofrio
  • Patent number: 8173473
    Abstract: An apparatus and method for processing the solar cell substrates is provided. In one embodiment, a laser firing chamber for processing solar cell substrates placed in a carrier, comprising a laser module located at a side of the carrier, the laser module being adapted to generate and direct multiple laser beams over an entire surface of a plurality of solar cell substrates, and a transport adapted to convey the carrier through an outputting region of the laser beams.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: May 8, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Derek Aqui, Steven M. Zuniga, Venkateswaran Subbaraman, Kirk Liebscher, John Alexander, Zhenhua Zhang, Virendra V. S. Rana
  • Patent number: 8170072
    Abstract: In the case of a lens array type homogenizer optical system, the incident angle and intensity of a laser beam 1 entering a large-sized lens (long-axis condenser lens 22) of a long-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while long-axis lens arrays 20a and 20b are reciprocated in a direction corresponding to a long axial direction of a linear beam (X-direction). Therefore, vertical stripes are significantly reduced. Further, the incident angle and intensity of a laser beam 1 entering a large-sized lens (projection lens 30) of a short-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while short-axis lens arrays 26a and 26b are reciprocated in a direction corresponding to a short axial direction of a linear beam (Y-direction). Therefore, horizontal stripes are significantly reduced.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: May 1, 2012
    Assignee: IHI Corporation
    Inventors: Norihito Kawaguchi, Ryusuke Kawakami, Kenichiro Nishida, Miyuki Masaki, Masaru Morita
  • Patent number: 8158513
    Abstract: A method for manufacturing an integrated circuit system includes: providing a first material; forming a second material over a first side of the first material; and exposing a second side of the first material to an energy source to form an electrical contact at an interface of the first material and the second material.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: April 17, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Zhihong Mai, Suey Li Toh, Pik Kee Tan, Jeffrey C. Lam, Liang-Choo Hsia
  • Patent number: 8138085
    Abstract: A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Howard H. Chen, Louis C. Hsu, Lawrence S. Mok, J. Campbell Scott
  • Publication number: 20120012854
    Abstract: In an active matrix substrate (29), a part of the drain electrode (15) of a TFT (10), which corresponds to an auxiliary capacitor electrode (26), is overlapped with a capacitor signal line (25). The auxiliary capacitor electrode (26) includes a notch (27).
    Type: Application
    Filed: December 28, 2009
    Publication date: January 19, 2012
    Inventor: Toshihiro Kaneko
  • Patent number: 8008171
    Abstract: Disclosed is a method of providing a poly-Si layer used in fabricating poly-Si TFT's or devices containing poly-Si layers. Particularly, a method utilizing at least one metal plate covering the amorphous silicon layer or the substrate, and applying RTA (Rapid Thermal Annealing) for light illuminating process, then the light converted into heat by the metal plate will further be conducted to the amorphous silicon layer to realize rapid thermal crystallization. Thus the poly-Si layer of the present invention is obtained.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: August 30, 2011
    Assignees: Tatung Company, Tatung University
    Inventors: Chiung-Wei Lin, Yi-Liang Chen
  • Patent number: 8003499
    Abstract: An object of the present invention is to provide a method and a device for constantly setting the energy distribution of a laser beam on an irradiating face, and uniformly irradiating the laser beam to the entire irradiating face. Further, another object of the present invention is to provide a manufacturing method of a semiconductor device including this laser irradiating method in a process. Therefore, the present invention is characterized in that the shapes of plural laser beams on the irradiating face are formed by an optical system in an elliptical shape or a rectangular shape, and the plural laser beams are irradiated while the irradiating face is moved in a first direction, and the plural laser beams are irradiated while the irradiating face is moved in a second direction and is moved in a direction reverse to the first direction.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: August 23, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Tanaka
  • Publication number: 20110201199
    Abstract: A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.
    Type: Application
    Filed: April 25, 2011
    Publication date: August 18, 2011
    Applicant: International Business Machines Corporation
    Inventors: Howard H. Chen, Louis C. Hsu, Lawrence S. Mok, J. Campbell Scott
  • Patent number: 7994030
    Abstract: The present invention provides an antenna with low resistance and a semiconductor device having an antenna whose communication distance is improved. A fluid containing conductive particles is applied over an object. After curing the fluid containing the conductive particles, the fluid is irradiated with a laser to form an antenna. As a method for applying the fluid containing the conductive particles, screen printing, spin coating, dipping, or a droplet discharging method is used. Further, a solid laser having a wavelength of 1 nm or more and 380 nm or less is used as the laser.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 9, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Daiki Yamada
  • Patent number: 7985665
    Abstract: Provided is a method of forming a polycrystalline silicon thin film with improved electrical characteristics. The method includes forming an amorphous silicon thin film on a substrate, partially melting a portion of the amorphous silicon thin film by irradiating the portion of the amorphous silicon thin film with a laser beam having a low energy density, forming polycrystalline silicon grains with a predetermined crystalline arrangement by crystallizing the partially molten portion of the amorphous silicon thin film, completely melting a portion of the polycrystalline silicon grains and a portion of the amorphous silicon thin film by irradiation of a laser beam having a high energy density while repeatedly moving the substrate by a predetermined distance, and growing the polycrystalline silicon grains by crystallizing the completely molten silicon homogeneously with the predetermined crystalline arrangement.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: July 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-byum Kim, Se-jin Chung
  • Patent number: 7947599
    Abstract: A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: May 24, 2011
    Assignee: International Business Machines Corporation
    Inventors: Howard H. Chen, Louis C. Hsu, Lawrence S. Mok, J. Campbell Scott
  • Patent number: 7943533
    Abstract: A method for surface modification is disclosed. The method includes the step of irradiating a material with ultrashort pulse laser light to form a modified region including an amorphous region and/or a strain region on a surface of the material.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: May 17, 2011
    Assignee: Sony Corporation
    Inventor: Takeshi Mizuno
  • Patent number: 7897513
    Abstract: The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: March 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Haowen Bu, Shashank Ekbote, Juanita Deloach
  • Patent number: 7838397
    Abstract: In a laser annealing process: the first to fourth sections of a bandlike area of a nonmonocrystalline semiconductor film are consecutively scanned and irradiated with laser light so as to produce a fused region in the bandlike area, where the fourth section contains a portion required to have higher crystallinity than other portions of the bandlike area. In the first section, the width of the fused region is substantially uniform. In the second section, the width of the fused region is stepwise or continuously decreased from the width of the fused region in the first section. In the third section, the width of the fused region is stepwise or continuously increased from the width of the fused region at the boundary between the second and third sections. In the fourth section, the width of the fused region at the boundary between the third and fourth sections is substantially uniformly maintained.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: November 23, 2010
    Assignee: FUJIFILM Corporation
    Inventor: Atsushi Tanaka
  • Patent number: 7796845
    Abstract: Provided is a circuit board which suppresses abnormal formation of plated layer inside a via, caused by core materials of glass fibers or the like projected from a side wall of the via and which helps to improve the connection reliability of the via. An insulating layer, which is formed of thermoset resin and embedded with glass fibers, is provided between a first wiring layer and a second wiring layer. The glass fibers projected into a via hole side from a side wall of the via hole in different positions are embedded into a via conductor in such a state that the glass fibers are jointed with each other.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: September 14, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Makoto Murai, Ryosuke Usui
  • Patent number: 7759177
    Abstract: A method for manufacturing a semiconductor device of the present invention is provided including the steps of forming a first conductive layer over a substrate; forming a second conductive layer containing a conductive particle and resin over the first conductive layer; and increasing an area where the first conductive layer and the second conductive layer are in contact with each other by irradiating the second conductive layer with a laser beam. By including the step of laser beam irradiation, the portion where the first conductive layer and the second conductive layer are in contact with each other can be increased and defective electrical connection between the first conductive layer and the second conductive layer can be improved.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: July 20, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Takahashi, Eiji Sugiyama
  • Patent number: 7737036
    Abstract: Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: June 15, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Yi Ma, Philip Allan Kraus, Christopher Sean Olsen, Khaled Z. Ahmed, Abhilash J. Mayur
  • Patent number: 7732349
    Abstract: The invention provides a manufacturing method of an insulating film having a plurality of pores, as well as a manufacturing method of a highly integrated semiconductor device with high yield. According to the invention, a porous insulating film is formed by forming a plurality of pores in an interlayer insulating film using a laser beam, which results in lower dielectric constant of the interlayer insulating film. In addition, a composition containing conductive particles is discharged onto the porous insulating film by a droplet discharge method typified by an ink jet printing method, and then baked to form a wire. As the laser beam, an ultrashort pulse laser beam is preferably used.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: June 8, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroko Yamamoto
  • Patent number: 7727853
    Abstract: A processing method for selectively reducing or removing the region to be exposed with energy ray in a film formed on a substrate, comprising relatively scanning a first exposure light whose shape on the substrate is smaller than the whole first region to be exposed against the whole first region to be exposed to selectively remove or reduce the first region to be exposed, and exposing a whole second region to be exposed inside the whole first region to be exposed with a second exposure light to selectively expose the whole second region to be exposed.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: June 1, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoyuki Takeishi, Kenji Kawano, Hiroshi Ikegami, Shinichi Ito, Riichiro Takahashi
  • Patent number: 7727846
    Abstract: It is an object of the present invention is to provide a method of manufacturing an SOI substrate provided with a single-crystal semiconductor layer which can be practically used even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like, is used, and further, to manufacture a semiconductor device with high reliability by using such an SOI substrate. A semiconductor layer which is separated from a semiconductor substrate and bonded to a supporting substrate having an insulating surface is irradiated with electromagnetic waves, and the surface of the semiconductor layer is subjected to polishing treatment. At least part of a region of the semiconductor layer is melted by irradiation with electromagnetic waves, and a crystal defect in the semiconductor layer can be reduced. Further, the surface of the semiconductor layer can be polished and planarized by polishing treatment.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: June 1, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Hideto Ohnuma, Ryota Imahayashi, Yoichi Iikubo, Kenichiro Makino, Sho Nagamatsu
  • Patent number: 7709398
    Abstract: The invention relates to a method and device for depositing at least one layer, particularly a semiconductor layer, onto at least one substrate, which is situated inside a process chamber of a reactor while being supported by a substrate holder. The layer is comprised of at least two material components provided in a fixed stoichiometric ratio, which are each introduced into the reactor in the form of a first and a second reaction gas, and a portion of the decomposition products form the layer, whereby the supply of the first reaction gas, which has a low thermal activation energy, determines the growth rate of the layer, and the second reaction gas, which has a high thermal activation energy, is supplied in excess and is preconditioned, in particular, by an independent supply of energy. The first reaction gas flows in a direction toward the substrate holder through a multitude of openings, which are distributed over a surface of a gas inlet element, said surface being located opposite the substrate holder.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: May 4, 2010
    Assignee: Aixtron AG
    Inventors: Gerhard Karl Strauch, Johannes Kaeppeler, Markus Reinhold, Bernd Schulte
  • Patent number: 7709378
    Abstract: A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern defined by a mask to have shadow regions and beamlets. Each region of the metal layer overlapped by a beamlet is melted throughout its entire thickness, and each region of the metal layer overlapped by a shadow region remains at least partially unmelted. After completion of resolidification of the melted regions following irradiation by the first excimer laser pulse, the metal layer is irradiated by a second excimer laser pulse having a shifted intensity pattern so that the shadow regions overlap regions of the metal layer having fewer and larger grains.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: May 4, 2010
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 7709379
    Abstract: An electrical device having carbonized conductors and a method and a device for the production thereof is disclosed. The electrical device has electrical components having connections. Furthermore, there are situated between the electrical components regions made of plastic with conductors having carbonized plastic and/or agglomerated nanoparticles. The conductors are connected to the connections of the components and/or to external connections of the electronic device.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: May 4, 2010
    Assignee: Infineon Technologies AG
    Inventors: Michael Bauer, Thomas Bemmerl, Markus Fink, Edward Fuergut, Horst Groeninger, Hermann Vilsmeier
  • Patent number: 7704856
    Abstract: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: April 27, 2010
    Assignee: Fujitsu Limited
    Inventors: Kanae Nakagawa, Masataka Mizukoshi, Kazuo Teshirogi