Plug Formation (i.e., In Viahole) Patents (Class 438/675)
  • Patent number: 10707242
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 7, 2020
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Masayoshi Fuchi
  • Patent number: 10700009
    Abstract: A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 30, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Nicholas Joy, Eric Chih Fang Liu, David L. O'Meara, David Rosenthal, Masanobu Igeta, Cory Wajda, Gerrit J. Leusink
  • Patent number: 10685880
    Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Sheng-Hsiung Wang, Mei-Yun Wang
  • Patent number: 10651289
    Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-De Chiou, Janet Chen, Jeng-Ya Yeh
  • Patent number: 10553600
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Patent number: 10546862
    Abstract: Some embodiments include an integrated assembly having active-region-pillars extending upwardly from a base. Each of the active-region-pillars has a pair of storage-element-contact-regions, and a digit-line-contact-region between the storage-element-contact-regions. The integrated assembly includes, along a cross-section, a first digit-line-contact-region adjacent a first storage-element-contact-region. The first digit-line-contact-region is recessed relative to the first storage-element-contact-region. A first digit-line is coupled with the first digit-line-contact-region. A second digit-line is laterally offset from the first digit-line. An insulative material is between the first digit-line and the first storage-element-contact-region. A cup-shaped indentation extends into the insulative material and the first storage-element-contact-region. Insulative spacers are along sidewalls of the first and second digit-lines, and include first material.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Guangjun Yang, Suraj J. Mathew
  • Patent number: 10464325
    Abstract: A method for processing a silicon substrate includes forming a structure having a bottom surface and a depth of 200 ?m or more or 300 ?m or more from a first surface of a silicon substrate, forming a protective film on an inner wall of the structure, and performing plasma etching so as to selectively remove the protective film disposed on the bottom surface of the structure with respect to the protective film disposed on the substantially perpendicular side wall of the structure, wherein the plasma etching is performed under the condition in which plasma with a sheath length at least 10 times the depth when the depth is 200 ?m or more, or at least 5 time the depth when the depth is 300 ?m or more, is generated and a mean free path of ions generated in the plasma is longer than the sheath length.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: November 5, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Atsunori Terasaki
  • Patent number: 10403573
    Abstract: A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; foil ling a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 3, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Wei-Che Chang
  • Patent number: 10363585
    Abstract: A cleaning liquid which includes 3-alkoxy-3-methyl-1-butanol represented by the following general formula (1); at least one of diethylene glycol monomethyl ether and triethylene glycol monomethyl ether; and quaternary ammonium hydroxide: in which R1 represents an alkyl group having 1 to 5 carbon atoms.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 30, 2019
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Yuriko Shirai, Ryusuke Uchida
  • Patent number: 10332788
    Abstract: Provided herein may be a method of manufacturing a semiconductor device. The method may include: forming a first stack in which a first pad region, a second pad region and first dummy region are successively defined; forming a second stack on the first stack; forming a first pad structure and a first reference pattern by patterning the second stack, the first pad structure being disposed on the first pad region and having a stepped shape, the first reference pattern being disposed on the first dummy region of the first stack; forming a first pad mask pattern on the first stack, the first pad mask pattern being aligned by measuring the distance from the first reference pattern thereto and covering the first and second pad regions; and forming a second pad structure having a stepped shape by patterning the second pad region while shrinking the first pad mask pattern.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 25, 2019
    Assignee: SK hynix Inc.
    Inventor: Yoo Hyun Noh
  • Patent number: 10211054
    Abstract: Embodiments of the invention are directed to methods and resulting structures for forming a storage element using phase change memory (PCM). In a non-limiting embodiment of the invention, a PCM layer is formed over a surface of a bottom electrode. A top electrode is formed over the PCM layer using a tone inversion process that includes a sacrificial layer. A PCM pillar is then formed by patterning the PCM layer to expose a surface of the bottom electrode. The tone inversion process enables a sub-50 nm PCM pillar diameter.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew J. BrightSky, Robert L. Bruce, John M. Papalia, HsinYu Tsai
  • Patent number: 10199353
    Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Navneet K. Singh, Ranjul Balakrishnan
  • Patent number: 10177174
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 8, 2019
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Masayoshi Fuchi
  • Patent number: 10170543
    Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hari V. Mallela, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 10042246
    Abstract: A photomask includes a transparent substrate, a mask pattern formed on the substrate, and a protective layer pattern covering side walls of the mask pattern, wherein a top of the protective layer pattern is exposed.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Keun Oh, Hyung-Ho Ko, Byung-Gook Kim, Jae-Hyuck Choi, Jun-Youl Choi
  • Patent number: 9978639
    Abstract: Methods for forming layers on a substrate having a feature are provided herein. In some embodiments, a method for forming layers on a substrate having a features may include depositing a copper layer within the feature, wherein a thickness of the copper layer disposed on upper corners of an opening of the feature and on an upper portion of a sidewall proximate the upper corners of the feature is greater than the thickness of the copper layer disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature; and exposing the substrate to a plasma formed from a process gas comprising hydrogen (H2) gas to selectively etch the copper layer proximate the upper corners of the opening and the upper portion of the sidewall proximate the upper corners, without substantially etching the copper layer proximate the lower portion of the sidewall proximate the bottom of the feature.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: May 22, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Siew Kit Hoi, Arvind Sundarrajan, Jiao Song
  • Patent number: 9966530
    Abstract: A resistive random access memory device and a method for fabricating the same are presented. The resistive random access memory device includes a first electrode having a first dopant within. A second electrode is disposed on the first electrode. A resistive switching layer is disposed between the first electrode and the second electrode.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 8, 2018
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Wen-Yueh Jang, Chia Hua Ho
  • Patent number: 9935194
    Abstract: A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 3, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jin Ha Kim, Jun Kwan Kim, Kang Sik Choi, Su Jin Chae, Young Ho Lee
  • Patent number: 9899320
    Abstract: An interconnection and a method for manufacturing thereof are provided. The interconnection includes a first conductive layer, a dielectric layer, a second conductive layer, an insulation layer, and a plurality of air gaps. The first conductive layer is disposed over a semiconductor substrate. The dielectric layer is disposed over the first conductive layer. The second conductive layer penetrates through the dielectric layer to electrically connect with the first conductive layer. The insulation layer is located between a portion of the dielectric layer and the second conductive layer, and a material of the insulation layer and a material of the dielectric layer are different. The air gaps are located between another portion of the dielectric layer and the second conductive layer.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9842766
    Abstract: A semiconductor device according to an embodiment, includes a plurality of wires, a first dielectric film, and a second dielectric film. The plurality of wires are arranged above a semiconductor substrate so as to extend in a first direction and aligned via a first cavity. The first dielectric film has a plurality of portions arranged above the plurality of wires so as to extend in a second direction substantially perpendicular to the plurality of wires and aligned along the first direction via a second cavity leading to the first cavity. The second dielectric film is formed above the first dielectric film so as to cover the second cavity.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: December 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masato Endo, Kazunori Masuda, Yukio Nishida, Naoya Kami, Yuuichi Tatsumi, Naoyuki Kondo
  • Patent number: 9825009
    Abstract: An interconnect substrate having vertical connection channels around a cavity is characterized in that contact pads are exposed from the cavity and the vertical connection channels are made of a combination of metal posts and metallized vias. The cavity includes a recess in a core layer and an aperture in a stiffener. The metal posts, disposed over the top surface of the core layer, are sealed in the stiffener and are electrically connected to a buildup circuitry adjacent to the bottom surface of the core layer. The minimal height of the metal posts needed for the vertical connection can be reduced by the amount equal to the depth of the recess. The buildup circuitry is electrically connected to the metal posts through the metallized vias and provides the contact pads exposed from the cavity for device connection.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: November 21, 2017
    Assignee: BRIDGE SEMICONDUCTOR CORPORATION
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 9799550
    Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: October 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hao Huang, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen, Shang-Yuan Tsai
  • Patent number: 9716103
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body which is provided on a substrate and in which an insulating film and an electrode film are alternately stacked. The semiconductor memory device also includes an insulating member which penetrates the stacked body in a stacking direction of the insulating film and the electrode film to thereby separate the stacked body. The semiconductor memory device also includes a semiconductor pillar which penetrates the stacked body in the stacking direction. A maximum portion of the insulating member where a first distance from a side surface of the insulating member to a central plane of the insulating member becomes maximum and a maximum portion of the semiconductor pillar where a second distance from a side surface of the semiconductor pillar to a center line of the semiconductor pillar becomes maximum being provided in different positions in the stacking direction.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: July 25, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kotaro Noda
  • Patent number: 9691655
    Abstract: Described herein is a method of forming semiconductor devices. The method comprises depositing an etch stop layer of titanium aluminum carbide in a cavity of a semiconductor device; depositing a first layer of metal on the etch stop layer; etching the first layer of metal to create an etch-modified surface of the first layer of metal; and depositing a second layer of metal on the etch-modified surface of the first layer of metal.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Keith Kwong Hon Wong
  • Patent number: 9627387
    Abstract: A semiconductor device includes a semiconductor substrate including active portions including first and second dopant regions, word lines on the substrate and extending in a first direction to intersect the active portions, first and second bit lines on the substrate and extending in a second direction to intersect the word lines, and contact structures in regions between the word lines and between the first and second bit lines when viewed from a plan view. The first and second bit lines are connected to the first dopant regions. The contact structures are in contact with the second dopant regions, respectively. The contact structures each include a contact plug and a contact pad. The contact pads contact the second dopant regions. A separation distance between the contact plugs and the first bit lines is less than separation distance between the contact pads and the first bit lines.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: April 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeonok Jung, Chan Ho Park, Chan-Sic Yoon, Kiseok Lee, Wonwoo Lee, Sunghee Han
  • Patent number: 9601420
    Abstract: A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoo-Sang Hwang, Hyun-Woo Chung, Dae-Ik Kim
  • Patent number: 9553181
    Abstract: The present disclosure presents a novel structure for a dielectric material for use with Group III-V material systems and a method of fabricating such a structure. More specifically, the present disclosure describes a novel dielectric layer that is formed on the top surface of a III-V material where the dielectric layer comprises a first region in contact with the top surface of the III-V material crystalline and a second region adjacent to the first region and at the upper side of the dielectric layer. The dielectric layer has material properties different from traditional dielectric layers as it is composed of both crystalline and amorphous structures. The crystalline structure is at the interface with the III-V material (such as AlGaN or GaN) but gradually transitions into an amorphous structure, both within the same layer and both comprising the same material.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: January 24, 2017
    Assignee: Toshiba Corporation
    Inventor: Long Yang
  • Patent number: 9530729
    Abstract: A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: December 27, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-gyu Choi, Hyun-chul Kim, Seung-hee Ko
  • Patent number: 9263389
    Abstract: A method of forming a semiconductor structure including a barrier layer between a metal line and an air gap oxide layer. The barrier layer may be formed in-situ or by a thermal annealing process and may prevent diffusion or electrical conduction.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Takeshi Nogami
  • Patent number: 9252043
    Abstract: A film deposition method is provided. A first metal compound film is deposited by performing a first cycle of exposing a substrate to a first source gas containing a first metal, and of exposing the substrate to a reaction gas reactive with the first source gas. Next, the first source gas is adsorbed on the first metal compound film by exposing the substrate having the first metal compound film deposited thereon to the first source gas. Then, a second metal compound film is deposited on the substrate by performing a second cycle of exposing the substrate having the first source gas adsorbed thereon to a second source gas containing a second metal, and of exposing the substrate to the reaction gas reactive with the second source gas.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: February 2, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroaki Ikegawa, Masahiko Kaminishi, Jun Ogawa
  • Patent number: 9214357
    Abstract: The present invention disclosed herein relates to a substrate treating apparatus and method. The substrate treating method includes: providing a substrate on which an oxide layer is formed; treating the oxide layer with a first process gas in a plasma state to substitute the treated oxide layer with a by-product layer; and heating the substrate to remove the by-product layer at a temperature which is above a first heating temperature at which the by-product layer is decomposed and is above a second heating temperature that is a boiling point of an additive by-product generated while the by-product layer is decomposed.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: December 15, 2015
    Assignee: PSK INC.
    Inventors: Young Yeon Ji, Won Bum Seo, Byoung Hoon Kim
  • Patent number: 9209077
    Abstract: Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, Kanwal Jit Singh, Robert L. Bristol, Jasmeet S. Chawla
  • Patent number: 9177938
    Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: November 3, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Motoaki Tani, Keishiro Okamoto
  • Patent number: 9099403
    Abstract: Methods for forming a semiconductor device including fine patterns are provided. The method may include forming a mask layer including first holes spaced apart from each other in a first direction and a second direction. The method may also include forming local mask patterns on the mask layer and forming a sacrificial layer on the mask layer filling the first holes and surrounding the local mask patterns. The local mask patterns may be offset from the first holes in the first direction and the second direction. The method may further include removing the local mask patterns to form openings in the sacrificial layer exposing the mask layer and etching the mask layer through the opening to form second holes in the mask layer.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: August 4, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Kyungho Jang
  • Patent number: 9058980
    Abstract: Embodiments of the invention generally provide methods for sealing pores at a surface of a dielectric layer formed on a substrate. In one embodiment, the method includes exposing a dielectric layer formed on a substrate to a first pore sealing agent, wherein the first pore sealing agent contains a compound with a general formula CxHyOz, where x has a range of between 1 and 15, y has a range of between 2 and 22, and z has a range of between 1 and 3, and exposing the substrate to UV radiation in an atmosphere of the first pore sealing agent to form a first sealing layer on the dielectric layer.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: June 16, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bo Xie, Kelvin Chan, Alexandros T. Demos
  • Publication number: 20150145027
    Abstract: A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Jia-Rong Wu, Ching-Wen Hung
  • Publication number: 20150147882
    Abstract: A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the second mandrel being between the first mandrel and the second mandrel, and etching the second mandrel to cut the second mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the mandrel, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Yung-Hsu Wu, Tien-I Bao, Shau-Lin Shue
  • Patent number: 9040346
    Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Edward Fuergut
  • Publication number: 20150140815
    Abstract: An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 21, 2015
    Applicant: INVENSAS CORPORATION
    Inventor: Cyprian Emeka Uzoh
  • Publication number: 20150140814
    Abstract: Prior to electrodeposition, a semiconductor wafer having one or more recessed features, such as through silicon vias (TSVs), is pretreated by contacting the wafer with a pre-wetting liquid comprising a buffer (such as a borate buffer) and having a pH of between about 7 and about 13. This pre-treatment is particularly useful for wafers having acid-sensitive nickel-containing seed layers, such as NiB and NiP. The pre-wetting liquid is preferably degassed prior to contact with the wafer substrate. The pretreatment is preferably performed under subatmospheric pressure to prevent bubble formation within the recessed features. After the wafer is pretreated, a metal, such as copper, is electrodeposited from an acidic electroplating solution to fill the recessed features on the wafer. The described pretreatment minimizes corrosion of seed layer during electroplating and reduces plating defects.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: Lam Research Corporation
    Inventor: Matthew Thorum
  • Publication number: 20150140774
    Abstract: A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first trench in the first etch stop layer and the first dielectric layer. The method further comprises filling the first trench with a conductive material. The method additionally comprises forming a second etch stop layer over the first etch stop layer. The method also comprises forming a second dielectric layer over the second etch stop layer. The method further comprises forming a second trench to expose the conductive material. The second trench is formed having a depth less than a total thickness of the first etch stop layer, the second etch stop layer and the second dielectric layer. The method additionally comprises depositing a first metal layer over sidewalls of the second trench and in contact with the conductive material.
    Type: Application
    Filed: January 27, 2015
    Publication date: May 21, 2015
    Inventors: Chih-Yang PAI, Kuo-Chi TU, Wen-Chuan CHIANG, Chung-Yen CHOU
  • Patent number: 9034755
    Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo A. Vega
  • Patent number: 9034753
    Abstract: A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: May 19, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Till Schloesser, Peter Baars
  • Patent number: 9034768
    Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials are provided. The method involves providing a partially fabricated semiconductor substrate and depositing a tungsten-containing layer on the substrate surface to partially fill one or more high aspect ratio features. The method continues with selective removal of a portion of the deposited layer such that more material is removed near the feature opening than inside the feature. In certain embodiments, removal may be performed at mass-transport limited conditions with less etchant available inside the feature than near its opening. Etchant species are activated before being introduced into the processing chamber and/or while inside the chamber. In specific embodiments, recombination of the activated species is substantially limited and/or controlled during removal, e.g., operation is performed at less than about 250° C. and/or less than about 5 Torr.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: May 19, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang
  • Patent number: 9034759
    Abstract: A method for forming an interlevel dielectric (ILD) layer includes the following steps. A MOS transistor on a substrate is provided. A first undoped oxide layer is deposited to cover the substrate and the MOS transistor. The first undoped oxide layer is planarized. A phosphorus containing oxide layer is deposited on the first undoped oxide layer. A second undoped oxide layer is deposited on the phosphorus containing oxide layer.
    Type: Grant
    Filed: January 13, 2013
    Date of Patent: May 19, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jei-Ming Chen, Yuh-Min Lin
  • Publication number: 20150129986
    Abstract: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.
    Type: Application
    Filed: December 23, 2014
    Publication date: May 14, 2015
    Inventors: Byron Neville Burgess, John K. Zahurak
  • Patent number: 9029260
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Chieh Lin, Hung-Wen Su, Minghsing Tsai, Syun-Ming Jang
  • Patent number: 9029193
    Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: May 12, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Kock Liang Heng
  • Publication number: 20150126030
    Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Ching-Fu Yeh, Tz-Jun Kuo, Hsiang-Huan Lee, Ming Han Lee
  • Patent number: 9023711
    Abstract: A method of forming a conductive material comprises forming at least one opening extending through an organic material and an insulative material underlying the organic material to expose at least a portion of a substrate and a conductive contact in the substrate. The method further comprises lining exposed surfaces of the insulative material, the conductive contact, and the at least a portion of the substrate in the at least one opening with a conductive material without forming the conductive material on the organic material.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: May 5, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh