Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate.

Abstract: According to an embodiment, a non-volatile memory device includes a first wiring provided on an underlayer, a first memory cell array provided on the first wiring and including a plurality of memory cells, a first select element including a first control electrode provided between the first wiring and the first memory cell array. The device also includes a second wiring provided at the same level as the first wiring and electrically connected to the first control electrode, and a first plug electrically connecting the first control electrode and the second wiring, one end of the first plug being in contact with the second wiring, and a side surface of the first plug being in contact with the first control electrode.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires.

Abstract: The process for smoothing a rough surface of a first substrate made of a semiconductor alloy based on at least two elements chosen from Ga, As, Al, In, P and N is implemented by placing a second substrate facing the first substrate so that the rough surface is placed facing a surface of the second substrate. The first and second substrates are separated by a distance d of at least 10 ?m, the facing portions of the two substrates defining a confinement space. The first substrate is then heated so as to partially desorb one of the elements of said alloy and to reach the saturated vapor pressure of this element in the confinement space and to obtain a surface atom mobility that is sufficient to reduce the roughness of the rough surface.

Abstract: A method for mask optimization, the method including moving any features of a gate contact mask that are in violation of a spacing rule to a second layer contact mask, splitting an elongated feature of the second layer mask that is too close to a feature moved to the second layer mask from the gate contact mask, and connecting two split features of a first layer contact mask, the split features corresponding to the elongated feature of the second layer mask.

Abstract: Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening.

Abstract: To achieve the foregoing and in accordance with the purpose of the present invention, a method for forming copper filled through silicon via features in a silicon wafer is provided. Through silicon vias are etched in the wafer. An insulation layer is formed within the through silicon vias. A barrier layer is formed within the through silicon vias. An oxide free silicon, germanium, or SiGe adhesion layer is deposited over the barrier layer. A seed layer is deposited over the adhesion layer then the wafers is annealed. The features are filled with copper or copper alloy. The stack is annealed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for using projection patterning in making an electronic substrate with an embedded die. In one embodiment, a method may include providing a die embedded in dielectric material of a substrate, and projecting a laser beam through a mask with a preconfigured pattern to create a projected mask pattern on a surface of the dielectric material in accordance with the preconfigured pattern. The projected mask pattern may include a via disposed over the die. Other embodiments may be described and/or claimed.

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings. The method further includes forming a metal layer including metal plugs within the openings and excess metal. The excess metal and the excess dielectric material are simultaneously chemically-mechanically removed using a slurry including ceria and ammonium persulfate. The slurry is selected to cause selectivity for removing the excess dielectric material relative to the stop layer greater than about 5:1 as well as selectivity for removing the excess dielectric material relative to the excess metal from about 0.5:1 to about 1.5:1.

Abstract: A method for manufacturing a semiconductor device, comprises forming an organic planarization layer on a plurality of gates on a substrate, wherein the plurality of gates each include a spacer layer thereon, forming an oxide layer on the organic planarization layer, removing a portion of the oxide layer to expose the organic planarization layer, stripping the organic planarization layer to form a cavity, patterning a direct lithographically-patternable gap dielectric on at least one of the gates in the cavity, and depositing a conductive contact in a remaining portion of the cavity.

Abstract: A wiring substrate includes a semiconductor substrate, an insulator and a plurality of columnar conductors. The insulator is made of an insulating material filled in a groove or hole provided in the semiconductor substrate. The plurality of columnar conductors are filled in grooves or holes provided in the insulator. The grooves or holes are arranged at a narrow pitch in a plane of the insulator. The insulating material has a Si—O bond obtained by reacting Si particles with an organic Si compound.

Abstract: A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.

Abstract: A contact may be fabricated by a method including depositing a dielectric layer on a substrate having a transistor, etching a first opening in the dielectric layer that extends to a source region, forming an insulator on the source region, forming a contact metal on the insulator, the insulator separating the contact metal from the source region, and filling substantially all of the first opening, wherein the contact metal remains separated from the source region after the first opening is filled.

Abstract: Embodiments described herein generally provide methods for reducing undesired low-k damages during a damascene process using a sacrificial dielectric material and optionally a barrier/capping layer. In one embodiment, a damascene structure is formed through a sacrificial dielectric material deposited over a dielectric base layer. The damascene structure is filled with a suitable metal such as copper. The sacrificial dielectric material filled in trench areas between the copper damascene is then removed, followed by a barrier/cap layer which conformally or selectively covers exposed surfaces of the copper damascene structure. Ultra low-k dielectric materials may then fill the trench areas that were previously filled with sacrificial dielectric material. The invention prevents the ultra low-k material between the metal lines from exposing to various damaging processes during a damascene process such as etching, stripping, wet cleaning, pre-metal cleaning or CMP process.

Abstract: A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.

Abstract: Some embodiments include methods of forming a pattern. First lines are formed over a first material, and second lines are formed over the first lines. The first and second lines form a crosshatch pattern. The first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein. In some embodiments, spacers may be formed along the first and second lines to narrow the openings in the crosshatch pattern.

Abstract: A method for providing metal filled features in a layer is provided. A metal seed layer is deposited on tops and bottoms of the features. Metal seed layer on tops of the features and overhangs is removed without removing metal seed layer on bottoms of features. An electroless deposition of metal is provided to fill the features, wherein the electroless deposition first deposits on the metal seed layer on bottoms of the features.

Abstract: In a substrate wiring method, copper is embedded all the way to the lowest parts of a wiring pattern formed on a substrate. The method is used to wire a substrate in a processing chamber kept in a vacuum state, the substrate having a wiring pattern formed thereon. The method includes a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas and an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas.

Abstract: Methods of depositing tungsten in different sized features on a substrate are provided herein. The methods involve depositing a first bulk layer of tungsten in the features, etching the deposited tungsten, depositing a second bulk tungsten, which is interrupted to treat the tungsten after the smaller features are completely filled, and resuming deposition of the second bulk layer after treatment to deposit smaller, smoother tungsten grains into the large features. The methods also involve depositing tungsten in multiple cycles of dep-etch-dep, where each cycle targets a group of similarly sized features using etch chemistry specific for that group, and depositing in groups from smallest sized features to the largest sized features. Deposition using methods described herein produce smaller, smoother grains with void-free fill for a wide range of sized features in a substrate.

Abstract: The present invention relates to a method for forming a via in a substrate which includes the flowing steps of: (a) providing a substrate having a first surface and a second surface; (b) forming an accommodating groove and a plurality of pillars on the first surface of the substrate, the accommodating groove having a side wall and a bottom wall, the pillars remaining on the bottom wall of the accommodating groove; (c) forming a first insulating material in the accommodating groove and between the pillars; (d) removing the pillars so as to form a plurality of grooves in the first insulating material; and (e) forming a first conductive metal in the grooves. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even.

Abstract: A semiconductor structure includes a molding compound, a conductive plug, and a cover. The conductive plug is in the molding compound. The cover is over a top meeting joint between the conductive plug and the molding compound. The semiconductor structure further has a dielectric. The dielectric is on the cover and the molding compound.

Abstract: A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by virtue of a conductive via that intersects a wire bond molded within a package substrate. The via provides a direct electrical connection between an external signal transmitter or receiver and the points connected by the wire bond, and thereby avoiding the need for the signal to transit built up interconnects in the semiconductor device package. Conductive vias can provide connectivity through or to a package substrate, and can be through vias or blind vias. The conductive via is formed by either mechanical or laser drilling, and is filled using standard fill techniques, and is therefore readily incorporated into a package production flow.

Abstract: On a wiring conversion part connected to a first conductive film and a second conductive film each functioning as a wiring, a hollow portion is formed inside the second conductive film. A first transparent conductive film provided on the second conductive film is formed so as to cover an upper surface of the second conductive film and an end surface thereof exposed on the hollow portion, and so as not to cover an outer peripheral end surface of the second conductive film. A second transparent conductive film which is a layer above the first transparent conductive film is connected to the second conductive film and the first conductive film, so that the first conductive film and the second conductive film are electrically connected.

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

Abstract: Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components.

Abstract: Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second width narrower than the first width; forming a first conductive layer buried in the second cavities and formed on bottom and side surface of the semiconductor substrate defined by the first cavity so that a third cavity is defined by the first conductive layer formed on the bottom and side surface of the semiconductor substrate; subjecting an etch back process to the first conductive layer so that a first conductive portion is formed at a bottom corner of the first cavity, further a fourth cavity is formed on the semiconductor substrate uncovered with the first conductive portion in the first cavity; and forming a first insulating layer in the fourth cavity and in the second cavity.

Abstract: After stacking m wafers in each of which a plurality of semiconductor chips are formed, the m wafers are diced to semiconductor chips to form a first chip stack having m of the semiconductor chips stacked, and, after stacking n wafers, the n wafers are diced to semiconductor chips to form a second chip stack having n of the semiconductor chips stacked. Next, the first chip stack is sorted according to the number of defective semiconductor chips included in the first chip stack, and the second chip stack is sorted according to the number of defective semiconductor chips included in the second chip stack. Furthermore, the first chip stack or the second chip stack after sorting are combined to form a third chip stack.

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract: Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.

Abstract: Provided is a method for manufacturing a stretchable thin film transistor. The method for manufacturing a stretchable thin film transistor includes forming a mold substrate, forming a stretchable insulator on the mold substrate, forming a flat substrate on the stretchable insulator, removing the mold substrate, forming discontinuous and corrugated wires on the stretchable insulator, forming a thin film transistor connected between the wires, and removing the flat substrate.

Abstract: A packaging substrate includes a first wiring layer, a first dielectric layer formed on the first wiring layer, a second wiring layer formed on the first dielectric layer, and a number of copper pillar bumps. Each copper pillar bump includes a base portion and a protruding portion. The base portion is connected to the first wiring layer, and the protruding portion is formed on the base portion. A size of the protruding portion is less than a size of the base portion, and a size of the copper pillar bump gradually increases from the protruding portion to the base portion.

Abstract: Processes for forming integrated circuits and integrated circuits formed thereby are provided in which a first dielectric layer including a first dielectric material is formed on an underlying substrate. A first etch mask having at least two patterned recesses is patterned over the first dielectric layer. At least one first-level via is etched in the first dielectric layer through one patterned recess in the first etch mask with a first etchant, and the first-level via is filled with electrically-conductive material. A second dielectric layer including a second dielectric material is formed over the first dielectric layer. A second etch mask having patterned recesses corresponding to the patterned recesses of the first etch mask is patterned over the second dielectric layer. Second-level vias are etched in the second dielectric layer through the patterned recesses in the second etch mask with a second etchant and exposed to the first etchant.

Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

Abstract: Circuit structures and methods of fabrication are provided with enhanced electrical connection between, for instance, a first metal level and a contact surface of a conductive structure. Enhanced electrical connection is achieved using a plurality of contact vias which are differently-sized, and disposed over and electrically coupled to the contact surface. The differently-sized contact vias include at least one center region contact via disposed over a center region of the contact surface, and at least one peripheral region contact via disposed over a peripheral region of the contact surface, where the at least one center region contact via is larger than the at least one peripheral region contact via.

Abstract: A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n?1 first recesses penetrating 20 through 2n?1 deposited sacrificial layers and forming a buried insulating layer group including 2n?1 buried insulating layers filling the 2n?1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n?1 buried insulating layers may be formed.

Abstract: A method for providing a shrink etch in which the features to be etched in a target layer have major and minor dimensions with the major dimension larger than the minor dimension. In the shrink etch of a mask, the dimensions are reduced from that of a patterned resist of the mask, however, with conventional techniques, the shrink etch undesirably shrinks by a greater amount in the major axis dimension. By treating the resist prior to the shrink etch, the shrinking is made more uniform, and if desired in accordance with processes herein, the amount of shrinkage in the major axis can be the same as or less than that in the minor axis direction.

Abstract: A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV.

Abstract: A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region.

Abstract: A contact may be fabricated by a method including depositing a dielectric layer on a substrate having a transistor, etching a first opening in the dielectric layer that extends to a source region, forming an insulator on the source region, forming a contact metal on the insulator, the insulator separating the contact metal from the source region, and filling substantially all of the first opening, wherein the contact metal remains separated from the source region after the first opening is filled.

Abstract: A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.

Abstract: Forming a dual damascene structure includes forming a first insulation layer and a second insulation layer, forming a resist mask, forming a via hole down to a lower end of the first insulation layer, forming a hardmask layer in the via hole and on the second insulation layer using a spin-coating method, forming a resist mask, forming a first trench hole down to a lower end of the second insulation layer, respectively removing a part of the hardmask layer in the via hole and a part of the hardmask layer on the second insulation layer, forming a second trench hole by removing a part of the first insulation layer between a top corner of the hardmask layer remaining in the via hole and a bottom corner of the first trench hole, removing the hardmask layer, and filling the via hole and the second trench hole with a conductive material.

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract: A method of fabricating a through silicon via (TSV) structure is provided, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the second dielectric layer covers a sidewall of the via hole. A conductive material layer is formed to fill the via hole and the second opening. The conductive material layer is planarized to form a TSV within the via hole. A TSV structure is also provided, in which, the second dielectric layer is disposed within the first opening and on the sidewall of the via hole.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Abstract: A method for fabricating a semiconductor device including a semiconductor substrate having a trench formed therein. A migration assist layer is formed in the trench and on the substrate. A buried layer in formed in the trench by migrating material from the migration assist layer and the semiconductor substrate.

Abstract: A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV.

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract: A method includes providing a semiconductor chip having a first main surface and a second main surface opposite to the first main surface. An electrically insulating material is deposited on the first main surface of the semiconductor chip using a plasma deposition method. A first electrically conductive material is deposited on the second main surface of the semiconductor chip using a plasma deposition method.