Abstract: Provided are M1 muscarinic acetylcholine receptor (mAChR) agonists, for use in the treatment of a neurological or neurodegenerative disease by promoting microglia and/or macrophage viability and/or activation. Microglia and macrophage survival and activation are thereby achieved by increasing levels of sTREM2 released by microglia cells. In addition, pharmaceutical compositions and methods of preparing the same are described, which are suitable for the treatment or prevention of conditions or diseases that require microglia and/or macrophage modulation, as well as methods for monitoring treatments and enhancing microglia and/or macrophage survival and/or activation.

Abstract: Described is a method for manufacturing a radio frequency (RF) absorber. The method includes first determining a set of desired RF absorption properties for a RF absorber. A computer model for the RF absorber having the determined set of desired RF absorption properties is then produced. Using a three-dimensional (3D) printing process, melted plastic filament loaded with a RF absorber material is deposited in in computer controlled patterns according to the computer model, thereby producing the RF absorber having the set of desired RF absorption properties.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes providing a substrate, forming a pad structure above the substrate, and forming a top groove on a top surface of the pad structure.

Abstract: Provided herein are methods and apparatuses for filling features metal-containing materials. One aspect of the disclosure relates to a method for filling structures with a metal-containing material, the method including: providing a structure to be filled with a metal-containing material, exposing the structure to multiple deposition cycles, with each deposition cycle including exposure to one or more alternating reducing agent (e.g. hydrogen (H2)) dose/inert gas purge pulses pulse followed by exposure to one or more alternating metal precursor dose pulses and inert gas purge pulses. The metal may be tungsten (W) or molybdenum (Mo) in some embodiments. In some embodiments, the structure is a partially fabricated (3-D) NAND structure. Apparatuses to perform the methods are also provided.

Abstract: There is provided a technique that includes executing a process recipe for processing a substrate; and executing a correction recipe for checking a characteristic value of a supply valve installed at a process gas supply line, wherein the act of executing the correction recipe comprises: supplying an inert gas into the process gas supply line for a certain period of time in a state where an adjusting valve that is installed at an exhaust portion of a process furnace and adjusts an internal pressure of the process furnace is fully opened; detecting a pressure value in a supply pipe provided with the supply valve while supplying the inert gas into the process gas supply line in the state where the adjusting valve is fully opened; and calculating the characteristic value of the supply valve based on the detected pressure value.

Abstract: An extreme ultraviolet (EUV) photolithography system generates EUV light by irradiating droplets with a laser. The system includes a droplet generator with a nozzle and a piezoelectric structure coupled to the nozzle. The generator outputs groups of droplets. A control system applies a voltage waveform to the piezoelectric structure while the nozzle outputs the group of droplets. The waveform causes the droplets of the group to have a spread of velocities that results in the droplets coalescing into a single droplet prior to being irradiated by the laser.

Abstract: An electronic component includes a substrate comprising a die attach region and a perimeter region on a front side of the substrate; and at least one thermal indicator disposed within the perimeter region for monitoring the cumulative heat exposure of the substrate. The thermal indicator signals when the predetermined thermal budget limit that correlates with the decline in the condition of the OSP layer or the degradation of the adhesion of the die attach films is reached.

Abstract: Techniques are disclosed that enable independent control of interconnect lines and line end structures using a single mask. The techniques provided are particularly useful, for instance, where single mask lithography processes limit the scaling of line end structures. In some embodiments, the techniques can be implemented using a liner body and multiple angled etches of the liner body to provide a line end structure comprised of a remaining portion of the liner body. In such cases, the line end structure material enables an etch rate that is slower than the etch rate of surrounding insulator materials. Furthermore, the line end structure can be of minimal size not attainable using conventional single mask processes. In other embodiments, the techniques can be implemented using a hardmask that includes hardmask features defining lines, and one or more angled etches of the hardmask to provide line end structure(s) of minimal size.

Abstract: A method of forming a patterned hard mask includes: forming first photoresist features on a hard mask layer; forming at least one sacrificial feature between immediately-adjacent two of the first photoresist features on the hard mask layer; performing a trimming process to the first photoresist features to form second photoresist features; and using the at least one sacrificial feature and the second photoresist features as etching mask, and performing a first etching process to the hard mask layer, in which a plurality of trenches are formed in the hard mask layer to obtain the patterned hard mask.

Abstract: A four signal line unit cell is formed on a substrate using a combination of an extreme ultraviolet photolithography process and one or more self aligned deposition processes. The photolithography process and the self aligned deposition processes result in spacers on a hard mask above the substrate. The spacers define a pattern of signal lines to be formed on the substrate for a unit cell. The photolithography process and self aligned deposition processes result in signal lines having a critical dimension much smaller than features that can be defined by the extreme ultraviolet photolithography process.

Abstract: Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes; a plurality of islands, disposed between the first and second S/D electrodes; and dielectric material disposed between adjacent ones of the islands, between the first S/D electrode and an adjacent one of the islands, and between the second S/D electrode and an adjacent one of the islands.

Abstract: The application relates to a method for producing a sterilized subcutaneous access device, the method comprising: producing a device carrier unit, comprising providing a carrier, producing a subcutaneous access part on the carrier, the subcutaneous access part being provided with at least one of a sensor device for detecting an analyte present in a bodily fluid and an infusion device for infusion of a substance, and producing an electronic assembly on the carrier, the producing comprising printing a battery on a carrier material, and sterilizing the device carrier unit by radiation sterilization, the sterilizing comprising exposing the printed battery to the radiation applied for sterilization. Furthermore, the application relates to a sterilized subcutaneous access device.

Abstract: A lead frame includes a plurality of leads formed from a metal plate having a front side and a back side, a first resin member, and a second resin member. The leads have side faces thereof fixed with the first resin member. Faces serving as internal connectors of the leads are uncovered on the side of the front-side surface of the first resin member, and faces serving as external connectors of the leads are uncovered on the side of the back-side surface of the first resin member. The second resin member is formed on the front-side surface of the first resin member to be at a level higher than the faces serving as the internal connectors, and has openings for leaving the faces serving as the internal connectors uncovered.

Abstract: Implementations of the present disclosure generally relate to apparatus and methods for uniform deposition of thin films on substrates. In one implementation, a plasma-processing chamber comprises a chamber body including chamber walls, a chamber floor, and a lid support. The plasma-processing chamber further comprises a substrate support assembly at least partially disposed within the chamber body and configured to support a substrate. The plasma-processing chamber further comprises a lid assembly disposed over the support assembly and positioned on the lid support wherein the lid assembly and the chamber body define a first processing volume. The plasma-processing chamber further comprises a bottom isolation assembly that circumscribes at least a portion of the substrate support assembly and is vertically movable from a loading position to a processing position. A seal is formed between the bottom isolation assembly and the lid assembly when the bottom isolation assembly is in the processing position.

Abstract: A method of forming a three-dimensional printed object having a printed surface image includes ejecting drops of a build material to form the three-dimensional printed object with a plurality of layers of build material and at least one layer of a transparent material. The method operates ejectors to form a printed image with a marking agent so the printed image can be viewed through the at least one transparent layer. A leveler is applied to a surface of the layer of transparent material but not to the printed image.

Abstract: Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.

Abstract: In a method of manufacturing a semiconductor device, by performing a predetermined number of times a cycle of performing supplying reducing gas to a substrate having an insulating surface and a conductive surface and supplying metal-containing gas to the substrate in a time-division manner, a metal film is formed selectively on an insulating surface.

Abstract: The present disclosure provides a method forming a field effect transistor (FET) in accordance with some embodiments. The method includes performing an etching process to a semiconductor substrate, thereby forming recesses in source and drain (S/D) regions of the semiconductor substrate; forming a passivation material layer of a first semiconductor in the recesses; and epitaxially growing a second semiconductor material, thereby forming S/D features in the recesses, wherein the S/D features are separated from the semiconductor substrate by the passivation material layer.

Abstract: Disclosed is a solar cell including a semiconductor substrate, a conductive area including first and second conductive areas disposed on one surface of the semiconductor substrate, and an electrode including a first electrode connected to the first conductive area and a second electrode connected to the second conductive area. The electrode includes an adhesive layer disposed on the semiconductor substrate or the conductive area, an electrode layer disposed on the adhesive layer and including a metal as a main component, and a barrier layer disposed on the electrode layer and including a metal that is different from the metal of the electrode layer as a main component. The electrode layer has a thickness greater than a thickness of each of the adhesive layer and the barrier layer, and the barrier layer has a higher melting point than a melting point of the electrode layer.

Abstract: The present disclosure provides a method for controlling an electronic device and an electronic device, to enable the electronic device to autonomously deform to be matched with an accommodating space thereof, thereby improving intelligence of the electronic device and providing good user experience.

Abstract: A method includes forming a mandrel layer over a target layer, and etching the mandrel layer to form mandrels. The mandrels have top widths greater than respective bottom widths, and the mandrels define a first opening in the mandrel layer. The first opening has an I-shape and includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. Portions of the first opening that are unfilled by the spacers are extended into the target layer.

Abstract: A method of fabricating a semiconductor device includes forming a hard mask (HM) mandrel along a first direction over a material layer, forming a first spacer along a sidewall of the HM mandrel, forming a second spacer along a sidewall of the first spacer and forming a patterned photoresist layer having a first line opening over the HM mandrel, the first spacer and the second spacer. First portions of the HM mandrel, the first spacer and the second spacer are exposed within the first line opening. The method also includes removing the first portion of the first spacer through the first line opening to expose a first portion of the material layer and etching the exposed first portion of the material layer to form a first opening in the material layer by using the exposed first portions of the HM mandrel and the second spacer as a sub-etch-mask.

Abstract: Provided are a structure for which ink wettability/spreadability in the width direction of a line drawn on a substrate is limited and a high aspect ratio can be achieved, a manufacturing method for said structure, and a line pattern. The present invention provides a structure comprising: a droplet overlapping solidification layer obtained by droplets sloping and continuously overlapping each other in the direction of movement of a substrate and solidifying, a droplet flow solidified layer obtained by the droplets flowing on the droplet overlapping solidification layer and continuously being solidified without the droplets overlapping, and recesses formed at the boundary region between the droplet overlapping solidification layer and the droplet flow solidified layer.

Abstract: A method for manufacturing contact structure includes the steps of: providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device includes a gate structure and a source/drain region; forming a patterned mask layer with a stripe hole on the substrate, and concurrently forming a stripe-shaped mask layer on the substrate; forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed right above the source/drain region; and forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask, and the source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed.

Abstract: In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. A gate arrangement is situated in the gate well and includes a gate electrode, a source-side field plate, and a drain-side field plate. The source-side field plate and the drain-side field plate each include steps, and the drain-side field plate is wider than the source-side field plate.

Abstract: A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.

Abstract: A method of processing a semiconductor assembly is presented. The method includes fabricating a photovoltaic module including a semiconductor assembly. The fabrication step includes performing an efficiency enhancement treatment on the semiconductor assembly, wherein the efficiency enhancement treatment includes light soaking the semiconductor assembly, and heating the semiconductor assembly. The semiconductor assembly includes a window layer having an average thickness less than about 80 nanometers, wherein the window layer includes cadmium and sulfur. A related system is also presented.

Abstract: The invention relates to a fabrication apparatus for fabricating a layer structure comprising at least a patterned first layer on a substrate. A layer structure (6) with an unpatterned first layer is provided on the substrate. A protective material application unit (8) applies protective material at least on parts of the provided layer structure for protecting at least the parts of the provided layer structure (6), an ablation unit (12) ablates the unpatterned first layer through the protective material such that the patterned first layer is generated, and the protective material removing unit (15) removes the protective material (9). This allows fabricating a layer structure for, for example, an OLED without necessarily using a technically complex and costly photolithography process. Moreover, ablation debris can be removed with removing the protective material, thereby reducing the probability of unwanted effects like unwanted shortcuts in the OLED caused by unwanted debris.

Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.

Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an energy removable film (ERF) on the sidewalls of each of the portions; forming a second dielectric layer over the ERFs, the portions of the patterned photoresist layer, and the first dielectric layer; removing the portions to leave behind a plurality of openings; filling a conductive material in the openings, the conductive material defining second conductive layer structures; forming a ceiling layer over the second conductive layer structures, the ERFs, and the second dielectric layer; and applying energy to the ERFs to partially remove the ERFs on the sidewalls of the portions thereby forming air gaps.

Abstract: Methods of selectively depositing a feature onto a substrate surface while maintaining substantially straight sidewalls on the feature. A portion of the feature is grown and then covered with a protective film. The protective film is removed from the top of the feature, leaving some of the film on the sides of the feature and the process is repeated to grow a feature of desired thickness.

Abstract: A manufacturing process, which we term Self-Aligned Capillarity-Assisted Lithography for manufacturing devices having nano-scale or micro-scale features, such as flexible electronic circuits, is described.

Abstract: An interposer having a multilayered conductive pattern portion that is constructed by repeating the direct printing on a carrier of one or more conductive pattern layers and application of one or more insulating layers between the printed conductive pattern layers is described. Also, a method for manufacturing the interposer, a semiconductor package using the interposer, and a method for fabricating the semiconductor package are described.

Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure is provided. The semiconductor device structure includes a substrate having a front side and a back side. The semiconductor device structure also includes devices formed on the front side of the substrate and interconnect structures formed on the devices. The semiconductor device structure further includes a protection layer formed on the back side of the substrate, and the protection layer has a thickness over about 10 A.

Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer. A thin spacer layer is used to form spacers alongside a pattern. A reverse image of the spacer pattern is formed and an enlargement process is used to slightly widen the pattern. The widened pattern is subsequently used to pattern an underlying layer. This process may be used to form a pattern in a dielectric layer, which openings may then be filled with a conductive material.

Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.

Abstract: With a stage kept in an as-heated state, a semiconductor wafer is placed over the stage. Then, with the elapse of a first time, a controller causes a pressure inside a vacuum chamber to rise to a second pressure higher than a first pressure (step S40). After the semiconductor wafer is placed over the stage, a pressure difference between a pressure inside the vacuum chamber and a pressure inside an adsorption port is set to a minimum value at which the semiconductor wafer is not allowed to slide over protrusions. Further, in step S40 as well, the pressure difference is kept at the minimum value at which the semiconductor wafer is not allowed to slide over the protrusions.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract: Embodiments of the present invention provide methods of fabricating features of a semiconductor device array, the method including patterning a dielectric layer deposited on a conductive carrier, wherein patterning comprises forming a trench pattern defining at least one device contact, electrodepositing metal into the patterned trenches, transferring the dielectric layer and the electrodeposited metal to a substrate and removing the conductive carrier, and the method further comprising lithographically fabricating one or more further features of the semiconductor device array overlying the dielectric layer and electrodeposited metal.

Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

Abstract: A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or the at least one aperture. The fluid may be pressurized by generating a pressure differential across the substrate, which causes the fluid to flow into or through the at least one aperture or recess. Apparatus for pressurizing fluid so as to cause it to flow into or through recesses or apertures in a substrate are also disclosed.

Abstract: A semiconductor process includes the following steps. Firstly, a conductive substrate is provided. Then, at least one insulating pattern is formed on the conductive substrate. Thereafter at least one metal pattern is formed on the insulating pattern. After that, a passivation layer is formed on the conductive substrate to cover the metal pattern by an electroplating process.

Abstract: Systems and methods are provided for reducing a contact resistivity associated with a semiconductor device structure. A substrate including a semiconductor region is provided. One or more dielectric layers are formed on the semiconductor region, the one or more dielectric layers including an element. A gaseous material is applied on the one or more dielectric layers to change a concentration of the element in the one or more dielectric layers. A contact layer is formed on the one or more dielectric layers to generate a semiconductor device structure. The semiconductor device structure includes the contact layer, the one or more dielectric layers, and the semiconductor region. A contact resistivity associated with the semiconductor device structure is reduced by changing the concentration of the element in the one or more dielectric layers.

Abstract: A lead frame and a semiconductor package including the lead frame are provided. The lead frame includes: a base material; a first metal layer which is formed on at least one side of the base material, of which a surface is roughly formed, and which includes copper or nickel; a second metal layer which is formed on a surface of the first metal layer, of which a surface is roughly formed, and which includes palladium or a palladium alloy; a third metal layer which is formed on a surface of the second metal layer, of which a surface is roughly formed, and which includes gold or a gold alloy; and a fourth metal layer which is formed on a surface of the third metal layer, of which a surface is roughly formed, and which includes metal that includes silver.

Abstract: A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by virtue of a conductive via that intersects a wire bond molded within a package substrate. The via provides a direct electrical connection between an external signal transmitter or receiver and the points connected by the wire bond, and thereby avoiding the need for the signal to transit built up interconnects in the semiconductor device package. Conductive vias can provide connectivity through or to a package substrate, and can be through vias or blind vias. The conductive via is formed by either mechanical or laser drilling, and is filled using standard fill techniques, and is therefore readily incorporated into a package production flow.

Abstract: Disclosed are devices comprising multiple nanogaps having a separation of less than about 5 nm. Also disclosed are methods for fabricating these devices.

Abstract: A semiconductor device manufacturing method allows stably forming a plating layer at low cost on one main surface side of a substrate, while preventing unintended plating layer deposition on the other main surface side. Emitter and collector electrodes are respectively formed on the front and back surfaces of a semiconductor substrate. A first film is attached to the back surface. A notch portion of the substrate is filled with a resin member. A second film is attached to an outer peripheral portion of the substrate, straddling the substrate from the front surface to the back surface. The first and second films push out air remaining between the first and second films and the substrate. An electroless plating process is carried out while the first and second films are attached to the substrate, thereby sequentially forming a nickel plating layer and a gold plating layer on the front surface side.

Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.

Abstract: A crystal manufacturing apparatus capable of manufacturing a crystal in a desired position on a substrate is provided. A spring has one end fixed to a mount and the other end coupled to a magnetic body. The magnetic body has one end coupled to the spring and the other end coupled to a piston. A coil is wound around the magnetic body and electrically connected between a power supply circuit and a ground node (GND). The piston has a linear member inserted in a cylinder. The cylinder has a hollow columnar shape and a small hole at a bottom surface. The cylinder holds a silicon melt. A substrate is supported by an XY stage to be opposed to the small hole of the cylinder. The power supply circuit passes pulse shaped current through the coil to move the piston in an up-down direction (DR1). As a result, a droplet is discharged toward the substrate from the small hole at an initial speed of 1.02 m/s.

Abstract: A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region.