Abstract: A 3D integrated circuit structure comprises a first chip, wherein the first chip comprises: a substrate; a semiconductor device formed on the substrate and a dielectric layer formed on both the substrate and the semiconductor device; a conductive material layer formed within a through hole penetrating through both the substrate and the dielectric layer; a stress releasing layer surrounding the through hole; and a first interconnecting structure connecting the conductive material layer with the semiconductor device. By forming a stress releasing layer to partially release the stress caused by the conductive material in the via, the stress caused by mismatch of CTE between the conductive material and the semiconductor (for example, silicon) surrounding it can be reduced, thereby enhancing the performance of the semiconductor device and the corresponding 3D integrated circuit consisting of the semiconductor devices.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.

Abstract: A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact node within the trench; removing a set of node films disposed above the exposed contact node and on the sides of the trench; and forming a contact region within the trench above the exposed contact node, the contact region contacting the substrate.

Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique. In one example, the method includes forming a patterned hard mask layer above a layer of insulating material, the patterned hard mask having a hard mask opening, forming an erodible spacer in the hard mask opening to thereby define a spacer opening and performing at least one etching process through the spacer opening on the layer of insulating material to define a trench therein for a conductive structure, wherein the erodible spacer is substantially eroded away during the at least one etching process.

Abstract: Randomized coded arrays and methods of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles. Also, a physically unclonable function embodied in a circuit.

Abstract: A semiconductor apparatus with a penetrating electrode having a high aspect ratio is manufactured with a low-temperature process. In one embodiment a first electrode 3 and a second electrode 6 of a semiconductor substrate 1 that are provided at the front and rear surface sides, respectively, are electrically connected by a conductive object 7 filled in a contact hole 4 and an extended portion 6a of the second electrode 6 extends to the contact hole 4. Even though the contact hole 4 has a high aspect ratio, film formation using the low-temperature process is enabled by using the conductive object 7, instead of forming the second electrode 6 on a bottom portion of the contact hole 4.

Abstract: A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.

Abstract: A method for forming an interlevel dielectric (ILD) layer includes the following steps. A MOS transistor on a substrate is provided. A first undoped oxide layer is deposited to cover the substrate and the MOS transistor. The first undoped oxide layer is planarized. A phosphorus containing oxide layer is deposited on the first undoped oxide layer. A second undoped oxide layer is deposited on the phosphorus containing oxide layer.

Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

Abstract: A patch antenna system comprising: an integrated circuit die having an active side including an active layer, and a backside; a dielectric layer formed on the backside; and a redistribution layer formed on the dielectric layer wherein the redistribution layer forms an array of patches. The patch antenna further comprises a plurality of through-silicon vias (TSV), wherein the TSVs electrically connect the array of patches to the active layer.

Abstract: A semiconductor device can be formed by first providing a semiconductor wafer, and forming a conductive via into the semiconductor wafer. A portion of the semiconductor wafer can be removed so that the conductive via extends above a surface of the semiconductor wafer. A first insulating layer can be formed over the surface of the semiconductor wafer and the conductive via, followed by a second insulating layer, the second insulating layer having a different material composition than the first insulating layer. Portions of the insulating layers can be removed to expose the conductive via.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.

Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.

Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.

Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

Abstract: A multilayer microelectronic device package includes one or more vertical electrical contacts. At least one semiconductor material layer is provided having one or more electrical devices fabricated therein. An electrical contact pad can be formed on or in the semiconductor material layer. Another material layer is positioned adjacent to the semiconductor material layer and includes a conductive material stud embedded in or bonded to the layer. A via is formed through at least a portion of the semiconductor material layer and the electrical contact pad and into the adjacent layer conducting material stud. The via is constructed such that the via tip terminates within the conducting material stud, exposing the conducting material. A metallization layer is disposed in the via such that the metallization layer contacts both the electrical contact pad and the conducting material stud exposed by the via tip.

Abstract: A method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer. A conductive material is deposited in the final via opening. The method further includes planarizing the conductive material until reaching a remaining portion of the encapsulant layer such that the conductive material is flush with the encapsulant layer and the passivation layer is preserved.

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract: A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the buried gate electrode and is etched to form a contact hole exposing the semiconductor substrate. A sacrificial spacer is formed on sidewalls of the insulating layer defining the contact hole. A polysilicon layer pattern is formed in the contact hole. The sacrificial spacer is removed to form an air gap around the polysilicon layer pattern. A thermal process is performed to remove a seam existing in the polysilicon layer pattern.

Abstract: Forming a dual damascene structure includes forming a first insulation layer and a second insulation layer, forming a resist mask, forming a via hole down to a lower end of the first insulation layer, forming a hardmask layer in the via hole and on the second insulation layer using a spin-coating method, forming a resist mask, forming a first trench hole down to a lower end of the second insulation layer, respectively removing a part of the hardmask layer in the via hole and a part of the hardmask layer on the second insulation layer, forming a second trench hole by removing a part of the first insulation layer between a top corner of the hardmask layer remaining in the via hole and a bottom corner of the first trench hole, removing the hardmask layer, and filling the via hole and the second trench hole with a conductive material.

Abstract: Disclosed are a method to fabricate interconnection wires of a semiconductor device in a way to utilize benefits of copper interconnection and low k dielectric insulation while avoiding the problem of low k damage due to etching processes, and so fabricated interconnection wires. The method saves fabrication time and cost by reduced number of steps and also resolves metal gap fill issue. The method may comprise providing layers of a substrate, an etch stop layer and a sacrificial layer, forming first spacers, forming first copper interconnecting wires, removing the first spacers; forming polymer-like second spacers by depositing plasma gases in an etching chamber, forming second metal interconnecting wires, removing the second spacers to define channels interwoven with alternating first and second metal interconnecting wires, forming an anti-diffusion barrier around each of the first and second metal interconnecting wires, and filling the channels with a dielectric material for insulation.

Abstract: The present disclosure relates to a dielectric solder barrier for a semiconductor die. In one embodiment, a semiconductor die includes a substrate, a semiconductor body on a first surface of the substrate, one or more first metallization layers on the semiconductor body opposite the substrate, a via that extends from a second surface of the substrate through the substrate and the semiconductor body to the one or more first metallization layers, and a second metallization layer on the second surface of the substrate and within the via. A portion of the second metallization layer within the via provides an electrical connection between the second metallization layer and the one or more first metallization layers. The semiconductor die further includes a dielectric solder barrier on the second metallization layer. Preferably, the dielectric solder barrier is on a surface of the portion of the second metallization layer within the via.

Abstract: The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

Abstract: A method includes applying, between connection conductors of adjacent substrates, a junction material containing the first metal or alloy component and the second metal or alloy component having a higher melting point than said first metal or alloy component. The method further includes melting the junction material by a heat treatment.

Abstract: An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed therein. A porous dielectric layer can be formed on the substrate. A surface treatment can be performed to the porous dielectric layer to form an isolation layer on the porous dielectric layer to prevent moisture absorption of the porous dielectric layer. An interconnect can be formed at least through the isolation layer and the porous dielectric layer to provide electrical connection to the semiconductor device disposed in the substrate.

Abstract: A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.

Abstract: A method for producing a connection region on a side wall of a semiconductor body is disclosed. A first trench is produced on a first surface of a semiconductor body and extends into the semiconductor body. An insulation layer is formed on the side walls and on the bottom of the first trench, and the first trench is only partially filled. The unfilled part of the first trench is filled with an electrically conductive material. A separating trench is produced along the first trench in such a way that a side wall of the separating trench directly adjoins the first trench. The part of the insulation layer which adjoins the separating trench is at least partially removed, with the result that at least some of the electrically conductive material in the first trench is exposed.

Abstract: A method including: forming a dielectric layer over a substrate of a microelectronic device; forming a photoresist layer over the dielectric layer; performing a first exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a first plurality of locations; subsequent to performing the first exposure, performing a second exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a second plurality of locations different from the first plurality of locations; removing the portions of the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations; and etching the dielectric layer at each of i) the first plurality of locations and ii) the second plurality of locations to respectively form a contact hole at each of the i) the first plurality of locations and ii) the second plurality of locations.

Abstract: A method for manufacturing a semiconductor device includes dry etching an interlayer insulating layer provided on a foundation layer by using a mask having a plurality of first openings and a plurality of second openings arranged more closely than the first openings to form simultaneously a first hole reaching the foundation layer under each of the first openings and a second hole reaching the foundation layer under the second openings. The first hole reaches the foundation layer without contacting any other first holes. After starting of the dry etching, a plurality of holes are formed under each of the plurality of second openings, and with the progress of the dry etching, the plurality of holes are connected with each other at least at their upper parts including their open ends to form the second hole having an opening area larger than an opening area of the first hole.

Abstract: A semiconductor device that may prevent an unexposed substrate and generation of bowing profile during a process for forming an open region having a high aspect ratio, and a method for fabricating the semiconductor device. The semiconductor device includes a first material layer formed over a substrate, an open region formed in the first material layer that exposes the first material layer, a second material layer formed on sidewalls of the open region, wherein the second material layer is a compound material including an element of the first material layer, and a conductive layer formed inside the open region.

Abstract: Embodiments of the invention include methods of forming borderless contacts for semiconductor transistors. Embodiments may include providing a transistor structure including a gate, a spacer on a sidewall of the gate, a hard cap above the gate, a source/drain region adjacent to the spacer, and an interlevel dielectric layer around the gate, forming a contact hole above the source/drain region, forming a protective layer on portions of the hard cap and of the spacer exposed by the contact hole; deepening the contact hole by etching the interlevel dielectric layer while the spacer and the hard cap are protected by the protective layer, so that at least a portion of the source/drain region is exposed by the deepening of the contact hole; removing the protective layer; and forming a metal contact in the contact hole.

Abstract: There is provided a method of manufacturing a semiconductor device, which includes forming a TiN film as a hard mask directly on a second p-SiCOH film formed on a substrate, forming an opening passing through the TiN film and the second p-SiCOH film by photolithography and etching, cleaning the inside of the opening, removing the TiN film after cleaning the inside, and forming a second metal film filling the opening directly on the second p-SiCOH film after removing the TiN film.

Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.

Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.

Abstract: Methods for depositing low resistivity tungsten in features of substrates in semiconductor processing are disclosed herein. Methods involve using a germanium-containing reducing agent during tungsten nucleation layer deposition to achieve thin, low resistivity nucleation layers.

Abstract: A method for producing an electrical feedthrough in a substrate includes: forming a first printed conductor on a first side of a substrate which electrically connects a first contact area of the substrate on the first side; forming a second printed conductor on a second side of a substrate which electrically connects a second contact area of the substrate on the second side; forming an annular trench in the substrate, a substrate punch being formed which extends from the first contact area to the second contact area; and selectively depositing an electrically conductive layer on an inner surface of the annular trench, the substrate punch being coated with an electrically conductive layer and remaining electrically insulated from the surrounding substrate due to the annular trench.

Abstract: A method is provided for forming at least one TSV interconnect structure surrounded by at least one isolating trench-like structure having at least one airgap. The method comprises at least the steps of providing a substrate having a first main surface and producing simultaneous at least one a TSV hole and a trench-like structure surrounding the TSV hole and separated by remaining substrate material. The method also comprises thereafter depositing a dielectric liner in order to smoothen the sidewalls of the etched TSV hole and to pinch-off the opening of the trench-like structure at the first main surface of the substrate in order to create at least one airgap in said trench-like structure and depositing a conductive material in said TSV hole in order to create a TSV interconnect. A corresponding substrate is also provided.

Abstract: A method of forming a semiconductor structure in accordance with various embodiments may include: forming at least one opening in a workpiece; forming a first conductive layer within the at least one opening, the first conductive layer not completely filling the at least one opening; forming a fill layer over the first conductive layer within the at least one opening; and forming a second conductive layer over the fill layer.

Abstract: Methods of forming features are disclosed. One method comprises forming a resist over a pool of acidic or basic material on a substrate structure, selectively exposing the resist to an energy source to form exposed resist portions and non-exposed resist portions, and diffusing acid or base of the acidic or basic material from the pool into proximal portions of the resist. Another method comprises forming a plurality of recesses in a substrate structure. The plurality of recesses are filled with a pool material comprising acid or base. A resist is formed over the pool material and the substrate structure and acid or base is diffused into adjacent portions of the resist. The resist is patterned to form openings in the resist. The openings comprise wider portions distal to the substrate structure and narrower portions proximal to the substrate structure. Additional methods and semiconductor device structures including the features are disclosed.

Abstract: According to an embodiment, a method for manufacturing a semiconductor device is provided. The method includes providing a mask layer which is used as an implantation mask when forming a doping region and which is used as an etching mask when forming an opening and a contact element formed in the opening. The contact element is in contact with the doping region.

Abstract: A nonvolatile semiconductor memory device includes: a first interconnect; a second interconnect at a position opposing the first interconnect; and a variable resistance layer between the first interconnect and the second interconnect, the variable resistance layer being capable of reversibly changing between a first state and a second state by a voltage applied via the first interconnect and the second interconnect or a current supplied via the first interconnect and the second interconnect, the first state having a first resistivity, the second state having a second resistivity higher than the first resistivity. Wherein the variable resistance layer has a compound of carbon and silicon as a main component and including hydrogen.

Abstract: Methods include sequentially forming a first mold film, a first support film, a second mold film, and a second support film on a substrate, forming a contact hole through the second support film, the second mold film, the first support film and the first mold film, forming an electrode in the contact hole, and removing portions of the second support film, the second mold film and the first mold film to leave a portion of the first support film as a first support pattern surrounding the electrode and to leave a portion of the second support film as a second support pattern surrounding the electrode.

Abstract: Some embodiments include methods of forming a pattern. First lines are formed over a first material, and second lines are formed over the first lines. The first and second lines form a crosshatch pattern. The first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein. In some embodiments, spacers may be formed along the first and second lines to narrow the openings in the crosshatch pattern.

Abstract: A method for forming a contact window includes: a step of providing a substrate; a step of forming a patterned amorphous carbon layer or spin-on coating layer, in which a surface of the substrate is exposed at two sides of the amorphous carbon layer or spin-on coating layer; a step of forming an interlayer dielectric layer on the substrate; a step of removing a portion of the interlayer dielectric layer until the patterned amorphous carbon layer or spin-on coating layer is exposed; a step of removing the patterned amorphous carbon layer or spin-on coating layer to form an opening; and a step of filling the opening with a conductive material to form the contact window.

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract: Methods and apparatus for flip chip substrates with guard rings. An embodiment comprises a substrate core with a die attach region for attaching an integrated circuit die; at least one dielectric layer overlying a die side surface of the substrate core; and at least one guard ring formed adjacent a corner of the substrate core, the at least one guard ring comprising: a first trace overlying the dielectric layer having rectangular portions extending in two directions from the corner of the substrate core and in parallel to the edges of the substrate core; a second trace underlying the dielectric layer; and at least one via extending through the dielectric layer and coupling the first and second traces; wherein the first trace, the at least one via, and the second trace form a vertical via stack. Methods for forming the flip chip substrates with the guard rings are disclosed.

Abstract: A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region.

Abstract: A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.

Abstract: A III-N semiconductor device can include an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure.