Abstract: A semiconductor device including: a semiconductor substrate including an active region; a plurality of conductive structures formed over the semiconductor substrate; an isolation layer filling a space between the conductive structures and having an opening that exposes the active region between the conductive structures; a pad formed in a bottom portion of the opening and in contact with the active region; a plug liner formed conformally over a sidewall of the opening and exposing the pad; and a contact plug formed over the pad inside the opening.

Abstract: A process for depositing a metal-adhesive, hydrophobic and electrically conductive coating based on electrically conductive microparticles and on a polymer matrix P comprising at least one thermoplastic fluoropolymer P1 and a thermosetting resin P2, comprises: in a first container, dissolve the polymer P1 in an organic solvent; in a second container, disperse the electrically conductive microparticles in an organic solvent; add, in the first container, the thermosetting resin P2 in the liquid state; mix the contents of the containers, then deposit the mixture on the substrate; crosslink the resin P2 and remove the solvents, to obtain a first coating; then impregnate the surface of the substrate with an additional resin solution P2 dissolved in a third solvent, which is a solvent of the resin P2 and a non-solvent of the polymer P1; eliminate the third solvent and crosslink while compressing the additional resin P2 in order to obtain the targeted final coating.

Abstract: A method for fabricating a wafer stack. The method includes forming a tantalum-nitride film on a substrate of the wafer stack using physical vapor deposition, forming a tantalum layer on the tantalum-nitride film using physical vapor deposition, and depositing indium on the tantalum layer using electroplating.

Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.

Abstract: A semiconductor device including: a semiconductor substrate including an active region; a plurality of conductive structures formed over the semiconductor substrate; an isolation layer filling a space between the conductive structures and having an opening that exposes the active region between the conductive structures; a pad formed in a bottom portion of the opening and in contact with the active region; a plug liner formed conformally over a sidewall of the opening and exposing the pad; and a contact plug formed over the pad inside the opening.

Abstract: A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

Abstract: Provided herein are nanostructures for lithium ion battery electrodes and methods of fabrication. In some embodiments, a nanostructure template coated with a silicon coating is provided. The silicon coating may include a non-conformal, more porous layer and a conformal, denser layer on the non-conformal, more porous layer. In some embodiments, two different deposition processes, e.g., a PECVD layer to deposit the non-conformal layer and a thermal CVD process to deposit the conformal layer, are used. Anodes including the nanostructures have longer cycle lifetimes than anodes made using either a PECVD or thermal CVD method alone.

Abstract: A substrate includes at least first, second, and third metal layers and adjacent substrate portions having rotated arrangements of signal traces provided by the metal layers. Each metal layer includes first and second spaced portions. The first portion of the first metal layer includes a first trace configured to carry a first signal and the second portion of the first metal layer includes a second trace configured to carry a second signal. The first portion of the second metal layer includes third and fourth spaced traces configured to carry the second signal and the second portion includes fifth and sixth spaced traces configured to carry the first signal. The first portion of the third metal layer includes a seventh trace configured to carry the first signal and the second portion includes an eighth trace configured to carry the second signal.

Abstract: A method of forming a bottom electrode for MRAM comprises: depositing a conductive material into a trench in a substrate and planarizing; depositing a selective cap on the conductive material; depositing a layer of high stress material on upper surfaces of the substrate and the cap; patterning the high stress material to remove the layer of high stress material on the upper surfaces of the substrate and leaving the layer of high stress material on the upper surfaces of the cap; depositing a layer of dielectric material on the upper surfaces of the substrate and on upper surfaces of the high stress material on the cap; planarizing the layer of dielectric material; and forming a magnetic tunnel junction stack on the dielectric material over the conductive material.

Abstract: Two-terminal memory devices can be formed in part within a dielectric material that is electrically insulating and operates as a blocking layer to mitigate diffusion of metal particles employed in integrated circuit fabrication. This dielectric material can be protected from other fabrication processes corrosive to the dielectric material (e.g., CMP, HF clean, etc) by a silicon containing liner. Use of the silicon containing liner can enable a minimum thickness of the dielectric material to be preserved and can facilitate step height differences between adjacent material surfaces that form a two-terminal memory device to be on the order of less than about five angstroms. This small step height difference, particularly when underlying a switching layer of the two-terminal memory device, can yield excellent switching characteristics.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include depositing a second metal on a first metal without protecting the dielectric, protecting the metal with a cross-linked self-assembled monolayer and depositing a second dielectric on the first dielectric while the metal is protected.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include depositing a second metal on a first metal without protecting the dielectric, protecting the metal with a cross-linked self-assembled monolayer and depositing a second dielectric on the first dielectric while the metal is protected.

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract: Embodiments of the present disclosure digital microfluidic arrays that may be fabricated by a printing method, whereby digital microfluidic electrodes arrays are printed, via a printing method such as inkjet printing, onto a suitable substrate. In some embodiments, a substrate and/or ink is prepared or modified to support the printing of electrode arrays, such as via changes to the surface energy. In some embodiments, porous and/or fibrous substrates are prepared by the addition of a barrier layer, or, for example, by the addition or infiltration of a suitable material to render the surface capable of supporting printed electrodes. Various example embodiments involving hybrid devices formed by the printing of digital microfluidic arrays onto a substrate having a hydrophilic layer are disclosed.

Abstract: A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.

Abstract: A method of manufacturing a through-substrate-via structure. The method comprises providing a substrate having a front-side and an opposite back-side. A through-substrate via opening is formed in the front-side of the substrate. The through-substrate-via opening does not penetrate an outer surface of the back-side of the substrate. The through-substrate-via opening is filled with a solid fill material. Portions of the substrate from the outer surface of the back-side of the substrate are removed to thereby expose the fill material. At least portions of the exposed fill material are removed to form a back-side through-substrate via opening that traverses an entire thickness of the substrate. The back-side through-substrate via opening is filled with an electrically conductive material.

Abstract: Pre-migration of metal ions is achieved in a controlled manner to form a migrated metalover which an inhibitor is applied to prevent further migration. In a semiconductor circuit, pre-migration of metal ions is achieved by exposing a joined metal system to water, oxygen and an electrical field in a controlled manner. Conductors, joined to electrically isolating materials, are exposed to electrical fields in such a manner as to form one or more anodes to corresponding cathodes, thus liberating metal ions. The metal ions are then allowed to migrate in a controlled manner from the anode toward the cathode to form a pre-migrated metal. Finally, an inhibitor is applied on top of the pre-migrated metal to prevent further migration.

Abstract: A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide layer; and a non-conductive metal oxide layer grown on the metal gate structure, wherein the silane layer inhibits nucleation and growth of the non-conductive metal oxide layer.

Abstract: Techniques disclosed herein a method and system for conditioning a polymeric layer on a substrate to enable adhesion of a metal layer to the polymeric layer. Techniques may include conditioning the polymeric layer with nitrogen-containing plasma to generate a nitride layer on the surface of the polymeric layer. In another embodiment, the conditioning may include depositing a CuN layer using a lower power copper sputtering process in a nitrogen rich environment. Following the condition process, a higher power copper deposition or sputtering process may be used to deposit copper onto the polymeric layer with good adhesion properties.

Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.

Abstract: A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber.

Abstract: A method of manufacturing, at a reduced cost, a semiconductor device assembly and a semiconductor device, having a conductive support which is not eroded by an etchant for a lift-off layer even when the lift-off layer is made of a material for which no suitable selective etching solution has been found is provided. In the method of manufacturing the semiconductor device assembly, a plating step of forming a conductive support is carried out such that a first metal which is dissolved with an etchant is encapsulated in second metal which are not dissolved with the etchant, and through-holes for supplying etchant are formed in the second metal.

Abstract: The embodiments fill the need of improving electromigration and reducing stress-induced voids of copper interconnect by enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect. The adhesion between the barrier layer and the copper layer can be improved by making the barrier layer metal-rich prior copper deposition and by limiting the amount of oxygen the barrier layer is exposed prior to copper deposition. Alternatively, a functionalization layer can be deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect with good adhesion between the barrier layer and the copper layer. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in an integrated system in order to improve electromigration performance of the copper interconnect is provided.

Abstract: Provided are methods of depositing N-Metals onto a substrate. Some methods comprise providing an initiation layer of TaM or TiM layer on a substrate, wherein M is selected from aluminum, carbon, noble metals, gallium, silicon, germanium and combinations thereof; and exposing the substrate having the TaM or TiM layer to a treatment process comprising soaking the surface of the substrate with a reducing agent to provided a treated initiation layer.

Abstract: Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.

Abstract: Methods for forming interconnect structures are provided herein. In some embodiments, a method for forming an interconnect on a substrate may include depositing a material atop an upper surface of the substrate and atop one or more surfaces of a feature disposed in the substrate by a first deposition process that deposits the material at a faster rate on the upper surface than on a bottom surface of the feature; depositing the material atop the upper surface of the substrate and atop one or more surfaces of the feature by a second deposition process that deposits the material at a greater rate on the bottom surface of the feature than on the upper surface of the substrate; and heating the deposited material to draw the deposited material towards the bottom surface of the feature to at least partially fill the feature with the deposited material.

Abstract: A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.

Abstract: According to one embodiment, a method for forming an interconnection pattern includes forming an insulating pattern, forming a self-assembled film, and forming a conductive layer. The insulating pattern has a side surface on a major surface of a matrix. The self-assembled film has an affinity with a material of the insulating pattern on the side surface of the insulating pattern. The forming the conductive layer includes depositing a conductive material on a side surface of the self-assembled film.

Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.

Abstract: This invention relates to a process for forming a continuous pattern on a substrate with a liquid media. Upon the deposition of the liquid media on the substrate, a portion the continuous pattern is evaporated upon contact with the substrate.

Abstract: Pre-migration of metal ions is achieved in a controlled manner to form a migrated metalover which an inhibitor is applied to prevent further migration. In a semiconductor circuit, pre-migration of metal ions is achieved by exposing a joined metal system to water, oxygen and an electrical field in a controlled manner. Conductors, joined to electrically isolating materials, are exposed to electrical fields in such a manner as to form one or more anodes to corresponding cathodes, thus liberating metal ions. The metal ions are then allowed to migrate in a controlled manner from the anode toward the cathode to form a pre-migrated metal. Finally, an inhibitor is applied on top of the pre-migrated metal to prevent further migration.

Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: A semiconductor manufacturing method includes: forming a seed film including a first metal over a bottom surface and a side wall of an opening portion formed over interlayer insulating films and a field portion located over the interlayer insulating film except the opening portion, forming a resist over the seed film and filling the opening portion with the resist, removing part of the resist, exposing the seed film formed over the upper portion of the side walls of the opening portion and the field portion, forming a cover film including a second metal, whose resistivity is higher than that of the first metal, over the seed film located over the upper portion of the side wall of the opening portion and the field portion, exposing the seed film by removing the resist, and forming a plating film including the first metal over the exposed seed film.

Abstract: A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.

Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

Abstract: A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

Abstract: There is provided a semiconductor device manufacturing apparatus capable of recovering a damage of a low dielectric insulating film exposed to CO2 plasma to obtain the low dielectric insulating film in a good state, thus improving performance and reliability of a semiconductor device. The semiconductor device manufacturing apparatus includes: an etching processing mechanism for performing an etching process that etches a low dielectric insulating film formed on a substrate; a CO2 plasma processing mechanism for performing a CO2 plasma process that exposes the substrate to CO2 plasma after the etching process; a polarization reducing mechanism for performing a polarization reducing process that reduces polarization in the low dielectric insulating film after the CO2 plasma process; and a transfer mechanism for transferring the substrate.

Abstract: A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.

Abstract: A method of forming an integrated circuit structure includes forming a copper-containing seed layer on a wafer, and performing a descum step on an exposed surface of the copper-containing seed layer. The descum step is performed using a process gas including fluorine and oxygen. A reduction/purge step is then performed on the exposed surface of the copper-containing seed layer using a nitrogen-containing gas. A copper-containing layer is plated on the copper-containing seed layer.

Abstract: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.

Abstract: A method for forming a trench gate field effect transistor includes forming, in a semiconductor region, a trench followed by forming a dielectric layer lining a sidewall and a bottom surface of the trench. The method also includes, forming a first polysilicon layer on the bottom surface of the trench. The method further includes, forming a conductive material layer on an exposed surface of the first polysilicon layer and forming a second polysilicon layer on an exposed surface of the conductive material layer. The method still further includes, performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the conductive material layer to react.

Abstract: Methods for forming a contact metal layer in a contact structure in semiconductor devices are provided in the present invention. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device includes pulsing a deposition precursor gas mixture to a surface of a substrate disposed in a metal deposition processing chamber, pulsing a purge gas mixture to an edge of the substrate, wherein the purge gas mixture includes at least a hydrogen containing gas and an inert gas, and forming a contact metal layer on the substrate from the first deposition precursor gas mixture.

Abstract: According to an embodiment of the present disclosure, a method of pre-migrating metal ions is disclosed. A metal in a semiconductor configuration is exposed to water and oxygen to yield metal ions. The metal couples a conductor to another material. The metal and the conductor are exposed to an electrical field in such a manner that one or both of the metal and the conductor becomes an anode to a corresponding cathode. The metal ions are then allowed to migrate from the anode to the cathode to form a migrated metal. Finally, a migration inhibitor is applied on top of the migrated metal to prevent further migration.

Abstract: Methods of forming a conductive metal layer over a dielectric layer using plasma enhanced atomic layer deposition (PEALD) are provided, along with related compositions and structures. A plasma barrier layer is deposited over the dielectric layer by a non-plasma atomic layer deposition (ALD) process prior to depositing the conductive layer by PEALD. The plasma barrier layer reduces or prevents deleterious effects of the plasma reactant in the PEALD process on the dielectric layer and can enhance adhesion. The same metal reactant can be used in both the non-plasma ALD process and the PEALD process.

Abstract: The method includes steps of adding first ions to a predetermined depth from a main surface of a semiconductor substrate by irradiation of the semiconductor substrate with a planar, linear, or rectangular ion beam, so that a separation layer is formed; adding second ions to part of the separation layer formed in the semiconductor substrate; disposing the main surface of the semiconductor substrate and a main surface of a base substrate to face each other in order to bond a surface of an insulating film and the base substrate; and cleaving the semiconductor substrate using the separation layer as a cleavage plane, so that a single crystal semiconductor layer is formed over the base substrate. The mass number of the second ions is the same as or larger than that of the first ions.

Abstract: Embodiments of the invention provide a method for depositing tungsten-containing materials. In one embodiment, a method includes forming a tungsten nucleation layer over an underlayer disposed on the substrate while sequentially providing a tungsten precursor and a reducing gas into a process chamber during an atomic layer deposition (ALD) process and depositing a tungsten bulk layer over the tungsten nucleation layer, wherein the reducing gas contains hydrogen gas and a hydride compound (e.g., diborane) and has a hydrogen/hydride flow rate ratio of about 500:1 or greater. In some examples, the method includes flowing the hydrogen gas into the process chamber at a flow rate within a range from about 1 slm to about 20 slm and flowing a mixture of the hydride compound and a carrier gas into the process chamber at a flow rate within a range from about 50 sccm to about 500 sccm.

Abstract: Disclosed herein are a variety of microfluidic devices and solid, typically electrically conductive devices that can be formed using such devices as molds. In certain embodiments, the devices that are formed comprise conductive pathways formed by solidifying a liquid metal present in one or more microfluidic channels (such devices hereinafter referred to as “microsolidic” devices). In certain such devices, in which electrical connections can be formed and/or reformed between regions in a microfluidic structure; in some cases, the devices/circuits formed may be flexible and/or involve flexible electrical components. In certain embodiments, the solid metal wires/conductive pathways formed in microfluidic channel(s) may remain contained within the microfluidic structure. In certain such embodiments, the conductive pathways formed may be located in proximity to other microfluidic channel(s) of the structure that carry flowing fluid, such that the conductive pathway can create energy (e.g.