Substrate Dicing Patents (Class 438/68)
  • Patent number: 10347788
    Abstract: In an example, the present invention provides a method of separating a photovoltaic strip from a solar cell. The method includes providing a solar cell, placing the front side of the solar cell on a platen such that the backside is facing a laser source, initiating a laser source to output a laser beam having a wavelength from 200 to 600 nanometers and a spot size of 18 to 30 microns, subjecting a portion of the backside to the laser beam at a power level ranging from about 20 Watts to about 35 Watts to cause an ablation to form a scribe region having a depth, width, and a length, the depth being from 40% to 60% of a thickness of the solar cell, the width being between 16 and 35 microns to create a plurality of scribe regions spatially disposed on the backside of the solar cell.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: July 9, 2019
    Assignee: Solaria Corporation
    Inventors: Kevin R. Gibson, Aureo Parilla, Thomas Phu
  • Patent number: 10008438
    Abstract: In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed, in particular a method of fabricating a package including an exposed die pad.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: June 26, 2018
    Assignee: Adventive IPBank
    Inventor: Richard K Williams
  • Patent number: 9911808
    Abstract: A method for forming a semiconductor device includes incorporating first dopant atoms of a first conductivity type into a semiconductor substrate to form a first doping region of the first conductivity type. Further, the method includes forming an epitaxial semiconductor layer on the semiconductor substrate and incorporating second dopant atoms of a second conductivity type before or after forming the epitaxial semiconductor layer to form a second doping region including the second conductivity type adjacent to the first doping region so that a pn-junction is located between the first doping region and the second doping region. The pn-junction is located in a vertical distance of less than 5 ?m to an interface between the semiconductor substrate and the epitaxial semiconductor layer. Additionally, the method includes thinning the semiconductor substrate based on a self-aligned thinning process. The self-aligned thinning process is self-controlled based on the location of the pn-junction.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: March 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Philipp Seng
  • Patent number: 9793197
    Abstract: In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: October 17, 2017
    Assignee: Adventive IP Bank
    Inventor: Richard K Williams
  • Patent number: 9520427
    Abstract: Provided is an image sensor having improved characteristics. An image sensor in accordance with an embodiment of the present invention may include a photoelectric conversion element formed in a substrate; a transfer gate formed over the photoelectric conversion element, formed over a first surface of the substrate and having at least one through hole, wherein the through hole passes through the transfer gate; a floating diffusion layer formed over the transfer gate; a channel structure formed in the through hole and electrically coupling the photoelectric conversion element to the floating diffusion layer in response to a signal applied to the transfer gate; and a capacitor formed over the floating diffusion layer.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: December 13, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kyungdong Yoo, Kyoung-In Lee
  • Patent number: 9401355
    Abstract: One embodiment of an integrated circuit includes a semiconductor body. In the semiconductor body a first trench region extends into the semiconductor body from a first surface. The integrated circuit further includes a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench region. The other one of the anode region and the cathode region includes a first semiconductor region adjoining the one of the anode region and the cathode region from outside of the first trench region.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: July 26, 2016
    Assignee: Infineon Technologies AG
    Inventors: Joachim Weyers, Anton Mauder, Franz Hirler, Andreas Meiser, Ulrich Glaser
  • Patent number: 9281265
    Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: March 8, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yueh-Se Ho, Yan Xun Xue, Jun Lu, Lei Shi, Liang Zhao, Ping Huang
  • Patent number: 9269676
    Abstract: The present disclosure relates to forming a plurality of through silicon vias guard rings proximate the scribes streets of a microelectronic device wafer. The microelectronic device wafer includes a substrate wherein the through silicon via guard ring is fabricated by forming vias extending completely through the substrate. The through silicon via guard rings act as crack arresters, such that defects caused by cracks resulting from the dicing of the microelectronic wafer are substantially reduced or eliminated.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Cheng Yang, Jiamin Qian, Hai Wu
  • Patent number: 9171876
    Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: October 27, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chi Fu, Kai Tzeng, Wen-Chen Lu
  • Patent number: 9112070
    Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a semiconductor substrate doped with a first conductive type impurity through which a via hole passing from a first surface of the semiconductor substrate to a second surface thereof facing the first surface is formed, wherein the first surface is a light receiving surface, upper and lower emitter layers respectively formed on upper and lower surfaces of the semiconductor substrate and doped with a second conductive type impurity that is different from the first conductive type impurity, current collecting layers formed on sidewalls of the via hole and doped with a higher concentration of the first conductive type impurity than that of the semiconductor substrate, a contact electrode extending from the first surface of the semiconductor substrate to the second surface thereof so as to fill the via hole, and upper and lower electrodes respectively contacting the upper and lower emitter layers.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: August 18, 2015
    Assignee: Shinshung Solar Energy Co., Ltd.
    Inventors: Young Hyun Cho, Ji Sun Kim, Eun Joo Lee, Jong Youb Lim
  • Patent number: 9040389
    Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Gunther Mackh, Maria Heidenblut, Adolf Koller, Anatoly Sotnikov
  • Publication number: 20150140719
    Abstract: An embodiment of a die comprising: a semiconductor body including a front side, a back side, and a lateral surface; an electronic device, formed in said semiconductor body and including an active area facing the front side; a vertical conductive connection, extending through the semiconductor body and defining a conductive path between the front side and the back side of the semiconductor body; and a conductive contact, defining a conductive path on the front side of the semiconductor body, between the active area and the vertical conductive connection, wherein the vertical conductive connection is formed on the lateral surface of the die, outside the active area.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 21, 2015
    Inventor: CROCIFISSO MARCO ANTONIO RENNA
  • Publication number: 20150137294
    Abstract: Image sensor package structure and method are provided. The method includes: providing first substrate having upper surface on which image sensing areas and pads are formed; providing second substrate having through holes; forming tape film on upper surface of second substrate to seal each through hole; contacting lower surface of second substrate with upper surface of first substrate to make image sensing areas in through holes; removing portions of tape film and second substrate, wherein remained tape film and second substrate form cavities including sidewalls made of second substrate and caps sealing sidewalls and made of tape film, and remained second substrate also covers pads; removing portions of remained second substrate to expose pads; slicing first substrate to form single image sensor chips including image sensing areas and pads; and electrically connecting pads with circuits on third substrate through wires. Pollution or damage to image sensing areas may be avoided.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 21, 2015
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Qiong Yu, Wei Wang
  • Patent number: 9029184
    Abstract: To provide a resource-saving photoelectric conversion device with excellent photoelectric conversion characteristics. Thin part of a single crystal semiconductor substrate, typically a single crystal silicon substrate, is detached to structure a photoelectric conversion device using a thin single crystal semiconductor layer, which is the detached thin part of the single crystal semiconductor substrate. The thin part of the single crystal semiconductor substrate is detached by a method in which a substrate is irradiated with ions accelerated by voltage, or a method in which a substrate is irradiated with a laser beam which makes multiphoton absorption occur. A so-called tandem-type photoelectric conversion device is obtained by stacking a unit cell including a non-single-crystal semiconductor layer over the detached thin part of the single crystal semiconductor substrate.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akihisa Shimomura
  • Patent number: 8999816
    Abstract: Approaches for protecting a wafer during plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer with a front surface having a plurality of integrated circuits thereon involves laminating a pre-patterned mask on the front surface of the semiconductor wafer. The pre-patterned mask covers the integrated circuits and exposes streets between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the streets to singulate the integrated circuits. The pre-patterned mask protects the integrated circuits during the plasma etching.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: James M. Holden, Aparna Iyer, Brad Eaton, Ajay Kumar
  • Patent number: 8993361
    Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: March 31, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hiroshi Oguri, Yoshitaka Ishikawa, Akira Sakamoto, Tomoya Taguchi, Yoshimaro Fujii
  • Publication number: 20150087103
    Abstract: A treatment of thin layers for forming a connection of a photovoltaic cell including the thin layers, which includes a first layer, having photovoltaic properties, deposited on a second layer, and the second layer, which is a metal contact layer, deposited on a substrate, the treatment including etching, in the first layer, at least one first trench having a first width so as to expose the second layer; and etching, in the first trench, a second trench so as to expose the substrate, the second trench having a second width less than the first width.
    Type: Application
    Filed: January 28, 2013
    Publication date: March 26, 2015
    Inventor: Brendan Dunne
  • Patent number: 8987030
    Abstract: A method is provided for manufacturing a plurality of packages. The method comprises the steps of: applying a means for adhering two or more covers to a substrate; positioning the two or more covers onto the substrate to create one or more channels bounded by the two or more covers and the substrate; coupling the covers to the substrate; depositing a material into the one or more channels; performing a process on the material to affix the material; and singulating along the channels to create the plurality of packages.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: March 24, 2015
    Assignee: Knowles Electronics, LLC
    Inventors: Peter V. Loeppert, Denise P. Czech, Lawrence A. Grunert, Kurt B. Friel, Qing Wang
  • Patent number: 8987029
    Abstract: A method of protecting a substrate during fabrication of semiconductor, MEMS devices. The method includes application of a protective thin film which typically has a thickness ranging from 3 angstroms to about 1,000 angstroms, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: March 24, 2015
    Assignee: Applied Microstructures, Inc.
    Inventors: Jeffrey D. Chinn, Boris Kobrin, Romuald Nowak
  • Publication number: 20150075604
    Abstract: A base material formed of a thin film, a rear surface electrode located on the base material, a photoelectric conversion layer located on the rear surface electrode, a first surface electrode that is located above the rear surface electrode, is electrically connected to the rear surface electrode, and has a first polarity, and a second surface electrode that is located on the photoelectric conversion layer and has a second polarity different from the first polarity are included. The edge of the base material is located outside the edge of the rear surface electrode with space left therebetween and surrounds the entire perimeter of the rear surface electrode in plan view.
    Type: Application
    Filed: March 21, 2013
    Publication date: March 19, 2015
    Inventor: Hiroshi Yamaguchi
  • Patent number: 8980742
    Abstract: Provided are methods and apparatuses for manufacturing a multilayer metal thin film without additional heat treatment processes. The method of manufacturing a multilayer metal thin film including steps of: (a) forming a first metal layer on a substrate by flowing a first metal precursor into a first reaction container; and (b) forming a second metal layer on the first metal layer by flowing a second metal precursor into a second reaction container, wherein the step (b) is performed in a range of a heat treatment temperature of the first metal layer so that the second metal layer is formed as the first metal layer is heat-treated.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: March 17, 2015
    Assignee: Wonik IPS Co., Ltd.
    Inventors: Jung Wook Lee, Young Hoon Park
  • Patent number: 8980673
    Abstract: Provided are a solar cell and a method of manufacturing the same. The method of manufacturing the solar cell includes stacking a solar cell device layer containing GaN on a sacrificial substrate, etching the solar cell device layer to expose the sacrificial substrate, thereby forming one or more solar cell devices comprising the solar cell device layer, anisotropically etching the exposed sacrificial substrate, contacting the solar cell devices to a stamping processor to remove the solar cell devices from the sacrificial substrate, and transferring the solar cell devices onto a receiving substrate. A high temperature semiconductor process may be performed on a substrate such as a silicon substrate to transfer the solar cell devices onto the substrate, thereby manufacturing flexible solar cells. Also, a large number of solar cells may be excellently aligned on a large area. In addition, economical solar cells may be manufactured.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: March 17, 2015
    Assignees: LG Siltron Incorporated, Korea Advanced Institute of Science
    Inventors: Keon Jae Lee, Sang Yong Lee, Seung Jun Kim
  • Patent number: 8975108
    Abstract: An optical proximity sensor module includes a substrate, a light emitter mounted on a first surface of the substrate, the light emitter being operable to emit light at a first wavelength, and a light detector mounted on the first surface of the substrate, the light detector being operable to detect light at the first wavelength. The module includes an optics member disposed substantially parallel to the substrate, and a separation member disposed between the substrate and the optics member. The separation member may surround the light emitter and the light detector, and may include a wall portion that extends from the substrate to the optics member and that separates the light emitter and the light detector from one another. The separation member may be composed, for example, of a non-transparent polymer material containing a pigment, such as carbon black.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: March 10, 2015
    Assignee: Heptagon Micro Optics Pte. Ltd.
    Inventors: Hartmut Rudmann, Alexander Bietsch, Susanne Westenhöfer, Simon Gubser
  • Publication number: 20150054108
    Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. Projections of the second dike structures onto the first surface of the wafer are included in the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures, while tops of the first dike structures and the surface of the packaging cover are contacted.
    Type: Application
    Filed: August 1, 2014
    Publication date: February 26, 2015
    Inventors: Zhiqi Wang, Qiong Yu, Wei Wang
  • Patent number: 8962363
    Abstract: Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an A, C, M-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the A-axis to form first and second inclined surfaces on the surface of the flat plate. The following mathematical formulae (I)-(III) are satisfied: 45 degrees??b?a?60 degrees (I) 45 degrees??b+a?60 degrees (II), 0 degrees?|a|?7.5 degrees, where angle ?b represents an angle formed between a surface of the edge and a radial direction of the dicing blade in a cross-sectional view which includes the M-axis and the C-axis. The angle a represents an angle formed between the principal surface and the M-axis.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 24, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Akira Inoue, Toshiyuki Fujita, Toshiya Yokogawa
  • Publication number: 20150044810
    Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.
    Type: Application
    Filed: October 28, 2014
    Publication date: February 12, 2015
    Inventors: I-I Cheng, Chih-Mu Huang, Pin Chia Su, Chi-Cherng Jeng, Volume Chien, Chih-Kang Chao
  • Publication number: 20150035109
    Abstract: The present technology relates to a semiconductor device, a manufacturing method of a semiconductor device, a semiconductor wafer, and electronic equipment, which allow a semiconductor device, in which miniaturization is possible, to be provided. A semiconductor device includes a semiconductor substrate, a wiring layer that is formed on the semiconductor substrate, and a drive circuit that is provided in a circuit forming region of the semiconductor substrate. Then, the semiconductor device 110 is configured to include a pad electrode 103 that is electrically connected to the drive circuit and exposed from the side surface of the wiring layer, and an external connection terminal 108 that is provided in side surfaces of the semiconductor substrate and the wiring layer, and is electrically connected to the pad electrode 103.
    Type: Application
    Filed: March 4, 2013
    Publication date: February 5, 2015
    Inventor: Toyotaka Kataoka
  • Patent number: 8946056
    Abstract: In a splitting method for an optical device wafer, the wafer having optical devices formed individually in regions partitioned by a plurality of crossing scheduled splitting lines provided on a front surface and having a reflective film formed on a reverse surface, a focal point of a laser beam is positioned to the inside of the optical device wafer and the laser beam is irradiated along the scheduled splitting lines from the reverse surface side of the wafer to form modification layers in the inside of the wafer. An external force is applied to the wafer to split the wafer along the scheduled splitting lines and form a plurality of optical device chips. The laser beam has a wavelength that produces transmittance through the reflective film equal to or higher than 80%.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: February 3, 2015
    Assignee: Disco Corporation
    Inventors: Hiroumi Ueno, Hitoshi Hoshino
  • Patent number: 8945988
    Abstract: There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: February 3, 2015
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Hiroyuki Numaguchi
  • Patent number: 8941124
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, and an inorganic film. The semiconductor layer includes a first surface having an unevenness, a second surface opposite to the first surface, and a light emitting layer. The semiconductor layer includes gallium nitride. The inorganic film is provided to conform to the unevenness of the first surface and in contact with the first surface. The inorganic film has main components of silicon and nitrogen. The inorganic film has a refractive index between a refractive index of the gallium nitride and a refractive index of air. An unevenness is formed also in a surface of the inorganic film.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Takayoshi Fujii, Yoshiaki Sugizaki
  • Patent number: 8936961
    Abstract: A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.
    Type: Grant
    Filed: May 26, 2012
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoartabari, Paul A. Lauro, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8936952
    Abstract: An object is to provide a manufacturing method of a semiconductor device in which a defect in characteristics due to a crack occurring in a semiconductor device is reduced. Provision of a crack suppression layer formed of a metal film in the periphery of a semiconductor element makes it possible to suppress a crack occurring from the outer periphery of a substrate and reduce damage to the semiconductor element. In addition, even if the semiconductor device is subjected to physical forces from the outer periphery in separation and transposition steps, progression (growth) of a crack to the semiconductor device can be suppressed by the crack suppression layer.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akihiro Chida
  • Patent number: 8933806
    Abstract: The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: January 13, 2015
    Assignee: Thin Film Electronics ASA
    Inventors: Vivek Subramanian, Patrick Smith, Vikram Pavate, Arvind Kamath, Criswell Choi, Aditi Chandra, James Montague Cleeves
  • Patent number: 8921686
    Abstract: A method to fabricate a photovoltaic device includes forming first and second contact regions at the first surface of a semiconductor donor body. A cleave plane may be formed by implanting ions into the donor body, and a lamina that includes the contact regions is cleaved from the donor body at the cleave plane. The first surface of the lamina may be contacted with a temporary support and fabricated into a photovoltaic device, wherein the lamina comprises the base of the photovoltaic device.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: December 30, 2014
    Assignee: GTAT Corporation
    Inventors: Steven M. Zuniga, Christopher J. Petti, Gopal Prabhu
  • Patent number: 8916772
    Abstract: A three-dimensional thin-film semiconductor substrate with selective through-holes is provided. The substrate having an inverted pyramidal structure comprising selectively formed through-holes positioned between the front and back lateral surface planes of the semiconductor substrate to form a partially transparent three-dimensional thin-film semiconductor substrate.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: December 23, 2014
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang
  • Patent number: 8912033
    Abstract: Provided is a method of fabricating a light-emitting diode (LED) device. The method includes providing a substrate having opposite first and second sides. A semiconductor layer is formed on the first side of the substrate. The method includes forming a photoresist layer over the semiconductor layer. The method includes patterning the photoresist layer into a plurality of photoresist components. The photoresist components are separated by openings. The method includes filling the openings with a plurality of thermally conductive components. The method includes separating the semiconductor layer into a plurality of dies using a radiation process that is performed to the substrate from the second side. Each of the first regions of the substrate is aligned with one of the conductive components.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: December 16, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Gordon Kuo
  • Publication number: 20140352777
    Abstract: A method for forming photovoltaic cells comprises providing a first roll of a photovoltaic material and a second roll of an expanded metallic mesh. The photovoltaic material comprises a photoactive material adjacent to a flexible substrate, and the expanded metallic mesh comprises a plurality of openings. Next, an electrically insulating material is provided adjacent to an edge portion of the photovoltaic material. The photovoltaic material from the first roll can then be brought in proximity to the expanded mesh from the second roll to form a nascent photovoltaic cell. The electrically insulating material can be disposed between the expanded metallic mesh and the photovoltaic material. Next, the nascent photovoltaic cell is cut into individual sections to form a plurality of photovoltaic cells.
    Type: Application
    Filed: December 6, 2012
    Publication date: December 4, 2014
    Inventors: Bruce D. Hachtmann, Christine Tsai, Thomas M. Valeri, Herb Delarosa
  • Patent number: 8900925
    Abstract: In a method for manufacturing a diode, a semiconductor crystal wafer is used to produce a p-n or n-p junction, which extends in planar fashion across the top side of a semiconductor crystal wafer. Separation edges form perpendicularly to the top side of the semiconductor crystal wafer, which edges extend across the p-n or n-p junction. The separation of the semiconductor crystal wafer is achieved in that, starting from a disturbance, a fissure is propagated by local heating and local cooling of the semiconductor crystal wafer. The separation fissure thus formed extends along crystal planes of the semiconductor crystal, which avoids the formation of defects in the area of the p-n or n-p junction.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: December 2, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Robert Kolb
  • Patent number: 8895345
    Abstract: The present invention provides a dicing method that achieves excellent dicing properties at low costs by removing a metal film through a metal processing operation with a diamond tool and then performing pulse laser beam irradiation. The dicing method is a method of dicing a substrate to be processed, devices being formed in the substrate to be processed, a metal film being formed on one surface of the substrate to be processed.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: November 25, 2014
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventor: Takanobu Akiyama
  • Patent number: 8884392
    Abstract: Disclosed herein is a method of manufacturing a solid state imaging device, including the steps of: forming a light receiving portion in a light receiving area of a semiconductor substrate; forming a pad portion in a pad area of the semiconductor substrate; forming a microlens material layer over the light receiving portion and the pad portion; providing the microlens material layer with a microlens corresponding to the light receiving portion; forming a low-reflection material layer on the microlens material layer; etching the microlens material layer and the low-reflection material layer over the pad portion to form an opening; and imparting hydrophilicity to a surface of the low-reflection material layer and an inside portion of the opening by a normal temperature oxygen radical treatment.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventors: Yoshinori Toumiya, Ina Hori, Tadayuki Dofuku, Hitomi Kamiya, Atsushi Yamamoto, Taichi Natori
  • Patent number: 8883565
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Mathias Vaupel, Sebastian Bernrieder, Adolf Koller, Stefan Martens
  • Patent number: 8877077
    Abstract: A method of printing comprises the steps of: providing a solid state material having an exposed surface; applying an auxiliary layer to the exposed surface to form a composite structure, the auxiliary layer having a stress pattern; subjecting the composite structure to conditions facilitating fracture of the solid state material along a plane at a depth therein; and removing the auxiliary layer and, therewith, a layer of the solid state material terminating at the fracture depth, wherein an exposed surface of the removed layer of solid state material has a surface topology corresponding to the stress pattern.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: November 4, 2014
    Assignee: Siltectra GmbH
    Inventor: Lukas Lichtensteiger
  • Publication number: 20140322857
    Abstract: A method of fabricating a semiconductor image sensor device is disclosed. A plurality of radiation-sensing regions is formed in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. An opening is formed in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The opening is then filled with an organic material.
    Type: Application
    Filed: July 3, 2014
    Publication date: October 30, 2014
    Inventors: Shou-Shu Lu, Hsun-Ying Huang, Huang-Hsin Jung, Chun-Mao Chiu, Chia-Chi Hsiao, Yung-Cheng Chang
  • Patent number: 8871540
    Abstract: A laser dicing method includes: placing a workpiece substrate on a stage; generating a clock signal; emitting a pulse laser beam synchronous with the clock signal; switching irradiation and non-irradiation of the workpiece substrate with the pulse laser beam in a unit of light pulse in synchronization with the clock signal to perform first irradiation of the pulse laser beam on a first straight line by controlling the pulse laser beam using a pulse picker; performing second irradiation of the pulse laser beam on a second straight line, which is adjacent to the first straight line in a substantially parallel fashion, after the first irradiation; and forming a crack reaching a workpiece substrate surface on the workpiece substrate by the first irradiation and the second irradiation.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventor: Shoichi Sato
  • Patent number: 8871533
    Abstract: A solar cell making method includes steps of making a round P-N junction preform by (a) stacking a P-type silicon layer and a N-type silicon layer on top of each other, and (b) forming a P-N junction near an interface between the P-type silicon layer and the N-type silicon layer, wherein the round P-N junction preform defines a first surface and a second surface; forming a first electrode preform on the first surface and forming a second electrode preform on the second surface, thereby forming a round solar cell preform; and forming a photoreceptive surface with the P-N junction exposed on the photoreceptive surface by cutting the round solar cell preform into a plurality of arc shaped solar cells, the photoreceptive surface being on a curved surface of the arc shaped solar cell and being configured to receive incident light beams.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: October 28, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 8852988
    Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: October 7, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Hyung-Sun Jang, Woon-Seong Kwon, Tae-Je Cho, Un-Byoung Kang, Jung-Hwan Kim
  • Patent number: 8846432
    Abstract: Frontside-illuminated barrier infrared photodetector devices and methods of fabrication are disclosed. In one embodiment, a frontside-illuminated barrier infrared photodetector includes a transparent carrier substrate, and a plurality of pixels. Each pixel of the plurality of pixels includes an absorber layer, a barrier layer on the absorber layer, a collector layer on the barrier layer, and a backside electrical contact coupled to the absorber layer. Each pixel has a frontside and a backside. The absorber layer and the barrier layer are non-continuous across the plurality of pixels, and the barrier layer of each pixel is closer to a scene than the absorber layer of each pixel. A plurality of frontside common electrical contacts is coupled to the frontside of the plurality of pixels, wherein the frontside of the plurality of pixels and the plurality of frontside common electrical contacts are bonded to the transparent carrier substrate.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 30, 2014
    Assignee: L-3 Communications Cincinnati Electronics Corporation
    Inventors: Robert A. Jones, David Forrai, Richard L. Rawe, Jr.
  • Patent number: 8841161
    Abstract: The invention provides for a semiconductor wafer with a metal support element suitable for the formation of a flexible or sag tolerant photovoltaic cell. A method for forming a photovoltaic cell may comprise providing a semiconductor wafer have a thickness greater than 150 ?m, the wafer having a first surface and a second surface opposite the first and etching the semiconductor wafer a first time so that the first etching reduces the thickness of the semiconductor wafer to less than 150 ?m. After the wafer has been etched a first time, a metal support element may be constructed on or over the first surface; and a photovoltaic cell may be fabricated, wherein the semiconductor wafer comprises the base of the photovoltaic cell.
    Type: Grant
    Filed: February 5, 2012
    Date of Patent: September 23, 2014
    Assignee: GTAT.Corporation
    Inventors: Venkatesan Murali, Gopal Prabhu, Thomas Edward Dinan, Jr., Orion Leland
  • Publication number: 20140273329
    Abstract: A multi-step scribing operation is provided for forming scribe lines in solar panels to form multiple interconnected cells on a solar panel substrate. The multi-step scribing operation includes at least one step utilizing a nanosecond laser cutting operation. The nanosecond laser cutting operation is followed by a mechanical cutting operation or a subsequent nanosecond laser cutting operation. In some embodiments, the multi-step scribing operation produces a two-tiered scribe line profile and the method prevents local shunting and minimizes active area loss on the solar panel.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: TSMC SOLAR LTD.
    Inventors: Hsuan-Sheng YANG, Kwang-Ming LIN, Yi-Feng HUANG, Li-Wei CHANG, Chia-Hung TSAI
  • Patent number: 8835283
    Abstract: A fabrication method for producing semiconductor chips with enhanced die strength comprises following steps: forming a semiconductor wafer with enhanced die strength by comprising the substrate, the active layer on the front side of the substrate and the backside metal layer on the backside of the substrate, wherein at least one integrated circuit forms in the active layer; forming a protection layer on a front side of the semiconductor wafer; dicing the semiconductor wafer by at least one laser dicing process and removing the laser dicing residues and removing said protection layer by at least one etching process, whereby plural semiconductor chips with enhanced die strength are produced, and wherein the backside metal layer of said semiconductor chip fully covers the backside of said semiconductor chip after dicing.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: September 16, 2014
    Assignee: WIN Semiconductors Corp.
    Inventor: Chang-Hwang Hua