Substrate Dicing Patents (Class 438/68)
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Patent number: 11804557Abstract: A high efficiency configuration for a solar cell module comprises solar cells arranged in an overlapping shingled manner and conductively bonded to each other in their overlapping regions to form super cells, which may be arranged to efficiently use the area of the solar module.Type: GrantFiled: September 28, 2021Date of Patent: October 31, 2023Assignee: MAXEON SOLAR PTE. LTD.Inventors: Yafu Lin, Benjamin Francois
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Patent number: 11581453Abstract: According to the embodiments provided herein, a method for scribing a layer stack of a photovoltaic device can include directing a laser scribing waveform to a film side of a layer stack. The laser scribing waveform can include pulse groupings that repeat at a group repetition period of greater than or equal to 1.5 ?s. Each pulse of the pulse groupings can have a pulse width of less than or equal to 900 fs.Type: GrantFiled: February 21, 2019Date of Patent: February 14, 2023Assignee: First Solar, Inc.Inventors: Nikhil Bhandari, Charles Wickersham
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Patent number: 11322636Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiode structures and methods of manufacture. The structure includes: a charge region having a first doping concentration and a variable width; a multiplication region adjacent to the charge region; and an absorption region adjacent to the variable width charge region.Type: GrantFiled: February 24, 2020Date of Patent: May 3, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Asif J. Chowdhury, Ajey Poovannummoottil Jacob, Yusheng Bian, Michal Rakowski
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Patent number: 11289380Abstract: Implementations of methods of singulating a plurality of die comprised in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a polymer layer over the backside metal layer and forming a groove entirely through the polymer layer and partially through a thickness of the backside metal layer. The groove may be located in a die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the polymer layer, singulating the plurality of die in the substrate by removing substrate material in the die street.Type: GrantFiled: October 5, 2020Date of Patent: March 29, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Michael J. Seddon
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Patent number: 11233165Abstract: Provided is a multi-junction solar cell in which two or more absorption layers having different bandgaps are stacked on one another. The multi-junction solar cell includes a first cell including a first absorption layer, and a second cell electrically connected in series onto the first cell, wherein the second cell includes a second absorption layer having a higher bandgap compared to the first absorption layer, and a plurality of recesses penetrating through the second absorption layer.Type: GrantFiled: March 27, 2019Date of Patent: January 25, 2022Assignee: Korea Institute of Science and TechnologyInventors: Jeung Hyun Jeong, In Ho Kim, Won Mok Kim, Jong Keuk Park, Hyeong Geun Yu
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Patent number: 11104985Abstract: A deposition apparatus, such as an ultra-fine pattern deposition apparatus is provided. A deposition apparatus includes a base substrate, a heating assembly, a deposition source material and a pattern guide. The heating assembly has at least a part thereof included in the base substrate. The deposition source material is disposed on the heating assembly. The pattern guide overlies the base substrate and has a portion thereof above the heating assembly and the deposition source material. The pattern guide has an opening including a laterally recessed lower region and an upper region. The opening extends from an upper surface of the base substrate to an upper surface of the pattern guide. The lower region of the opening is wider than the upper region of the opening, and the opening of the pattern guide is configured to guide a material emitted from the deposition source material to a target region on a target substrate that is spaced apart from the base substrate.Type: GrantFiled: October 29, 2018Date of Patent: August 31, 2021Assignee: LG DISPLAY CO., LTD.Inventors: Hyungseok Bang, Joonghwan Yang, Dongwook Choi
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Patent number: 11075245Abstract: An image sensing device to control flow of photocharges using a new method is disclosed. The image sensing device includes a photoelectric conversion region formed in a semiconductor substrate, a floating diffusion (FD) region formed apart from the photoelectric conversion region, a vertical pillar formed between the photoelectric conversion region and the floating diffusion region to transfer the photocharges from the photoelectric conversion region to the floating diffusion (FD) region, and a switching element located between the photoelectric conversion region and the floating diffusion (FD) region.Type: GrantFiled: August 20, 2019Date of Patent: July 27, 2021Assignee: SK hynix Inc.Inventors: Kyoung In Lee, Heon Joon Kim
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Patent number: 10553743Abstract: A novel, low cost method for manufacturing flexible crystalline ultra-thin Si solar cells using previously fabricated inflexible crystalline Si solar cells. A stack of metal layers is coated onto a front side of previously completed inflexible crystalline Si solar cells. The stack serves as a bonding layer as well as an electrically conducting layer between the inflexible solar cell and the carrier substrate. The front side of the coated inflexible Si solar cell is bonded onto the carrier substrate. Back side layers from the starting inflexible solar cell are removed, as is much of the base layer, so that only a thin base layer remains, with the thin base layer and emitter region having a total thickness of between 1 ?m and 30 ?m and the final cell having a total thickness of about 10 to about 125 ?m.Type: GrantFiled: November 20, 2018Date of Patent: February 4, 2020Assignee: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Woojun Yoon, Phillip Jenkins, Robert J. Walters, David Scheiman
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Patent number: 10347788Abstract: In an example, the present invention provides a method of separating a photovoltaic strip from a solar cell. The method includes providing a solar cell, placing the front side of the solar cell on a platen such that the backside is facing a laser source, initiating a laser source to output a laser beam having a wavelength from 200 to 600 nanometers and a spot size of 18 to 30 microns, subjecting a portion of the backside to the laser beam at a power level ranging from about 20 Watts to about 35 Watts to cause an ablation to form a scribe region having a depth, width, and a length, the depth being from 40% to 60% of a thickness of the solar cell, the width being between 16 and 35 microns to create a plurality of scribe regions spatially disposed on the backside of the solar cell.Type: GrantFiled: June 13, 2017Date of Patent: July 9, 2019Assignee: Solaria CorporationInventors: Kevin R. Gibson, Aureo Parilla, Thomas Phu
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Patent number: 10008438Abstract: In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed, in particular a method of fabricating a package including an exposed die pad.Type: GrantFiled: October 16, 2017Date of Patent: June 26, 2018Assignee: Adventive IPBankInventor: Richard K Williams
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Patent number: 9911808Abstract: A method for forming a semiconductor device includes incorporating first dopant atoms of a first conductivity type into a semiconductor substrate to form a first doping region of the first conductivity type. Further, the method includes forming an epitaxial semiconductor layer on the semiconductor substrate and incorporating second dopant atoms of a second conductivity type before or after forming the epitaxial semiconductor layer to form a second doping region including the second conductivity type adjacent to the first doping region so that a pn-junction is located between the first doping region and the second doping region. The pn-junction is located in a vertical distance of less than 5 ?m to an interface between the semiconductor substrate and the epitaxial semiconductor layer. Additionally, the method includes thinning the semiconductor substrate based on a self-aligned thinning process. The self-aligned thinning process is self-controlled based on the location of the pn-junction.Type: GrantFiled: January 24, 2017Date of Patent: March 6, 2018Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Philipp Seng
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Patent number: 9793197Abstract: In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed.Type: GrantFiled: January 13, 2017Date of Patent: October 17, 2017Assignee: Adventive IP BankInventor: Richard K Williams
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Patent number: 9520427Abstract: Provided is an image sensor having improved characteristics. An image sensor in accordance with an embodiment of the present invention may include a photoelectric conversion element formed in a substrate; a transfer gate formed over the photoelectric conversion element, formed over a first surface of the substrate and having at least one through hole, wherein the through hole passes through the transfer gate; a floating diffusion layer formed over the transfer gate; a channel structure formed in the through hole and electrically coupling the photoelectric conversion element to the floating diffusion layer in response to a signal applied to the transfer gate; and a capacitor formed over the floating diffusion layer.Type: GrantFiled: March 3, 2016Date of Patent: December 13, 2016Assignee: SK Hynix Inc.Inventors: Kyungdong Yoo, Kyoung-In Lee
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Patent number: 9401355Abstract: One embodiment of an integrated circuit includes a semiconductor body. In the semiconductor body a first trench region extends into the semiconductor body from a first surface. The integrated circuit further includes a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench region. The other one of the anode region and the cathode region includes a first semiconductor region adjoining the one of the anode region and the cathode region from outside of the first trench region.Type: GrantFiled: December 16, 2011Date of Patent: July 26, 2016Assignee: Infineon Technologies AGInventors: Joachim Weyers, Anton Mauder, Franz Hirler, Andreas Meiser, Ulrich Glaser
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Patent number: 9281265Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.Type: GrantFiled: September 17, 2014Date of Patent: March 8, 2016Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Yueh-Se Ho, Yan Xun Xue, Jun Lu, Lei Shi, Liang Zhao, Ping Huang
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Patent number: 9269676Abstract: The present disclosure relates to forming a plurality of through silicon vias guard rings proximate the scribes streets of a microelectronic device wafer. The microelectronic device wafer includes a substrate wherein the through silicon via guard ring is fabricated by forming vias extending completely through the substrate. The through silicon via guard rings act as crack arresters, such that defects caused by cracks resulting from the dicing of the microelectronic wafer are substantially reduced or eliminated.Type: GrantFiled: January 30, 2013Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Cheng Yang, Jiamin Qian, Hai Wu
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Patent number: 9171876Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.Type: GrantFiled: May 30, 2014Date of Patent: October 27, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chi Fu, Kai Tzeng, Wen-Chen Lu
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Patent number: 9112070Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a semiconductor substrate doped with a first conductive type impurity through which a via hole passing from a first surface of the semiconductor substrate to a second surface thereof facing the first surface is formed, wherein the first surface is a light receiving surface, upper and lower emitter layers respectively formed on upper and lower surfaces of the semiconductor substrate and doped with a second conductive type impurity that is different from the first conductive type impurity, current collecting layers formed on sidewalls of the via hole and doped with a higher concentration of the first conductive type impurity than that of the semiconductor substrate, a contact electrode extending from the first surface of the semiconductor substrate to the second surface thereof so as to fill the via hole, and upper and lower electrodes respectively contacting the upper and lower emitter layers.Type: GrantFiled: July 1, 2013Date of Patent: August 18, 2015Assignee: Shinshung Solar Energy Co., Ltd.Inventors: Young Hyun Cho, Ji Sun Kim, Eun Joo Lee, Jong Youb Lim
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Patent number: 9040389Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.Type: GrantFiled: October 9, 2012Date of Patent: May 26, 2015Assignee: Infineon Technologies AGInventors: Gunther Mackh, Maria Heidenblut, Adolf Koller, Anatoly Sotnikov
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Publication number: 20150140719Abstract: An embodiment of a die comprising: a semiconductor body including a front side, a back side, and a lateral surface; an electronic device, formed in said semiconductor body and including an active area facing the front side; a vertical conductive connection, extending through the semiconductor body and defining a conductive path between the front side and the back side of the semiconductor body; and a conductive contact, defining a conductive path on the front side of the semiconductor body, between the active area and the vertical conductive connection, wherein the vertical conductive connection is formed on the lateral surface of the die, outside the active area.Type: ApplicationFiled: January 20, 2015Publication date: May 21, 2015Inventor: CROCIFISSO MARCO ANTONIO RENNA
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Publication number: 20150137294Abstract: Image sensor package structure and method are provided. The method includes: providing first substrate having upper surface on which image sensing areas and pads are formed; providing second substrate having through holes; forming tape film on upper surface of second substrate to seal each through hole; contacting lower surface of second substrate with upper surface of first substrate to make image sensing areas in through holes; removing portions of tape film and second substrate, wherein remained tape film and second substrate form cavities including sidewalls made of second substrate and caps sealing sidewalls and made of tape film, and remained second substrate also covers pads; removing portions of remained second substrate to expose pads; slicing first substrate to form single image sensor chips including image sensing areas and pads; and electrically connecting pads with circuits on third substrate through wires. Pollution or damage to image sensing areas may be avoided.Type: ApplicationFiled: August 19, 2014Publication date: May 21, 2015Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Qiong Yu, Wei Wang
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Patent number: 9029184Abstract: To provide a resource-saving photoelectric conversion device with excellent photoelectric conversion characteristics. Thin part of a single crystal semiconductor substrate, typically a single crystal silicon substrate, is detached to structure a photoelectric conversion device using a thin single crystal semiconductor layer, which is the detached thin part of the single crystal semiconductor substrate. The thin part of the single crystal semiconductor substrate is detached by a method in which a substrate is irradiated with ions accelerated by voltage, or a method in which a substrate is irradiated with a laser beam which makes multiphoton absorption occur. A so-called tandem-type photoelectric conversion device is obtained by stacking a unit cell including a non-single-crystal semiconductor layer over the detached thin part of the single crystal semiconductor substrate.Type: GrantFiled: March 17, 2009Date of Patent: May 12, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akihisa Shimomura
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Patent number: 8999816Abstract: Approaches for protecting a wafer during plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer with a front surface having a plurality of integrated circuits thereon involves laminating a pre-patterned mask on the front surface of the semiconductor wafer. The pre-patterned mask covers the integrated circuits and exposes streets between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the streets to singulate the integrated circuits. The pre-patterned mask protects the integrated circuits during the plasma etching.Type: GrantFiled: April 18, 2014Date of Patent: April 7, 2015Assignee: Applied Materials, Inc.Inventors: James M. Holden, Aparna Iyer, Brad Eaton, Ajay Kumar
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Patent number: 8993361Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions.Type: GrantFiled: August 28, 2013Date of Patent: March 31, 2015Assignee: Hamamatsu Photonics K.K.Inventors: Hiroshi Oguri, Yoshitaka Ishikawa, Akira Sakamoto, Tomoya Taguchi, Yoshimaro Fujii
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Publication number: 20150087103Abstract: A treatment of thin layers for forming a connection of a photovoltaic cell including the thin layers, which includes a first layer, having photovoltaic properties, deposited on a second layer, and the second layer, which is a metal contact layer, deposited on a substrate, the treatment including etching, in the first layer, at least one first trench having a first width so as to expose the second layer; and etching, in the first trench, a second trench so as to expose the substrate, the second trench having a second width less than the first width.Type: ApplicationFiled: January 28, 2013Publication date: March 26, 2015Inventor: Brendan Dunne
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Patent number: 8987029Abstract: A method of protecting a substrate during fabrication of semiconductor, MEMS devices. The method includes application of a protective thin film which typically has a thickness ranging from 3 angstroms to about 1,000 angstroms, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.Type: GrantFiled: November 1, 2011Date of Patent: March 24, 2015Assignee: Applied Microstructures, Inc.Inventors: Jeffrey D. Chinn, Boris Kobrin, Romuald Nowak
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Patent number: 8987030Abstract: A method is provided for manufacturing a plurality of packages. The method comprises the steps of: applying a means for adhering two or more covers to a substrate; positioning the two or more covers onto the substrate to create one or more channels bounded by the two or more covers and the substrate; coupling the covers to the substrate; depositing a material into the one or more channels; performing a process on the material to affix the material; and singulating along the channels to create the plurality of packages.Type: GrantFiled: August 13, 2010Date of Patent: March 24, 2015Assignee: Knowles Electronics, LLCInventors: Peter V. Loeppert, Denise P. Czech, Lawrence A. Grunert, Kurt B. Friel, Qing Wang
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Publication number: 20150075604Abstract: A base material formed of a thin film, a rear surface electrode located on the base material, a photoelectric conversion layer located on the rear surface electrode, a first surface electrode that is located above the rear surface electrode, is electrically connected to the rear surface electrode, and has a first polarity, and a second surface electrode that is located on the photoelectric conversion layer and has a second polarity different from the first polarity are included. The edge of the base material is located outside the edge of the rear surface electrode with space left therebetween and surrounds the entire perimeter of the rear surface electrode in plan view.Type: ApplicationFiled: March 21, 2013Publication date: March 19, 2015Inventor: Hiroshi Yamaguchi
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Patent number: 8980673Abstract: Provided are a solar cell and a method of manufacturing the same. The method of manufacturing the solar cell includes stacking a solar cell device layer containing GaN on a sacrificial substrate, etching the solar cell device layer to expose the sacrificial substrate, thereby forming one or more solar cell devices comprising the solar cell device layer, anisotropically etching the exposed sacrificial substrate, contacting the solar cell devices to a stamping processor to remove the solar cell devices from the sacrificial substrate, and transferring the solar cell devices onto a receiving substrate. A high temperature semiconductor process may be performed on a substrate such as a silicon substrate to transfer the solar cell devices onto the substrate, thereby manufacturing flexible solar cells. Also, a large number of solar cells may be excellently aligned on a large area. In addition, economical solar cells may be manufactured.Type: GrantFiled: January 30, 2014Date of Patent: March 17, 2015Assignees: LG Siltron Incorporated, Korea Advanced Institute of ScienceInventors: Keon Jae Lee, Sang Yong Lee, Seung Jun Kim
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Patent number: 8980742Abstract: Provided are methods and apparatuses for manufacturing a multilayer metal thin film without additional heat treatment processes. The method of manufacturing a multilayer metal thin film including steps of: (a) forming a first metal layer on a substrate by flowing a first metal precursor into a first reaction container; and (b) forming a second metal layer on the first metal layer by flowing a second metal precursor into a second reaction container, wherein the step (b) is performed in a range of a heat treatment temperature of the first metal layer so that the second metal layer is formed as the first metal layer is heat-treated.Type: GrantFiled: September 4, 2008Date of Patent: March 17, 2015Assignee: Wonik IPS Co., Ltd.Inventors: Jung Wook Lee, Young Hoon Park
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Patent number: 8975108Abstract: An optical proximity sensor module includes a substrate, a light emitter mounted on a first surface of the substrate, the light emitter being operable to emit light at a first wavelength, and a light detector mounted on the first surface of the substrate, the light detector being operable to detect light at the first wavelength. The module includes an optics member disposed substantially parallel to the substrate, and a separation member disposed between the substrate and the optics member. The separation member may surround the light emitter and the light detector, and may include a wall portion that extends from the substrate to the optics member and that separates the light emitter and the light detector from one another. The separation member may be composed, for example, of a non-transparent polymer material containing a pigment, such as carbon black.Type: GrantFiled: June 13, 2014Date of Patent: March 10, 2015Assignee: Heptagon Micro Optics Pte. Ltd.Inventors: Hartmut Rudmann, Alexander Bietsch, Susanne Westenhöfer, Simon Gubser
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WAFER LEVEL PACKAGING STRUCTURE FOR IMAGE SENSORS AND WAFER LEVEL PACKAGING METHOD FOR IMAGE SENSORS
Publication number: 20150054108Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. Projections of the second dike structures onto the first surface of the wafer are included in the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures, while tops of the first dike structures and the surface of the packaging cover are contacted.Type: ApplicationFiled: August 1, 2014Publication date: February 26, 2015Inventors: Zhiqi Wang, Qiong Yu, Wei Wang -
Patent number: 8962363Abstract: Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an A, C, M-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the A-axis to form first and second inclined surfaces on the surface of the flat plate. The following mathematical formulae (I)-(III) are satisfied: 45 degrees??b?a?60 degrees (I) 45 degrees??b+a?60 degrees (II), 0 degrees?|a|?7.5 degrees, where angle ?b represents an angle formed between a surface of the edge and a radial direction of the dicing blade in a cross-sectional view which includes the M-axis and the C-axis. The angle a represents an angle formed between the principal surface and the M-axis.Type: GrantFiled: June 6, 2014Date of Patent: February 24, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Akira Inoue, Toshiyuki Fujita, Toshiya Yokogawa
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Publication number: 20150044810Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventors: I-I Cheng, Chih-Mu Huang, Pin Chia Su, Chi-Cherng Jeng, Volume Chien, Chih-Kang Chao
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Publication number: 20150035109Abstract: The present technology relates to a semiconductor device, a manufacturing method of a semiconductor device, a semiconductor wafer, and electronic equipment, which allow a semiconductor device, in which miniaturization is possible, to be provided. A semiconductor device includes a semiconductor substrate, a wiring layer that is formed on the semiconductor substrate, and a drive circuit that is provided in a circuit forming region of the semiconductor substrate. Then, the semiconductor device 110 is configured to include a pad electrode 103 that is electrically connected to the drive circuit and exposed from the side surface of the wiring layer, and an external connection terminal 108 that is provided in side surfaces of the semiconductor substrate and the wiring layer, and is electrically connected to the pad electrode 103.Type: ApplicationFiled: March 4, 2013Publication date: February 5, 2015Inventor: Toyotaka Kataoka
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Patent number: 8945988Abstract: There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines.Type: GrantFiled: September 5, 2013Date of Patent: February 3, 2015Assignee: Lapis Semiconductor Co., Ltd.Inventor: Hiroyuki Numaguchi
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Patent number: 8946056Abstract: In a splitting method for an optical device wafer, the wafer having optical devices formed individually in regions partitioned by a plurality of crossing scheduled splitting lines provided on a front surface and having a reflective film formed on a reverse surface, a focal point of a laser beam is positioned to the inside of the optical device wafer and the laser beam is irradiated along the scheduled splitting lines from the reverse surface side of the wafer to form modification layers in the inside of the wafer. An external force is applied to the wafer to split the wafer along the scheduled splitting lines and form a plurality of optical device chips. The laser beam has a wavelength that produces transmittance through the reflective film equal to or higher than 80%.Type: GrantFiled: May 7, 2012Date of Patent: February 3, 2015Assignee: Disco CorporationInventors: Hiroumi Ueno, Hitoshi Hoshino
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Patent number: 8941124Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, and an inorganic film. The semiconductor layer includes a first surface having an unevenness, a second surface opposite to the first surface, and a light emitting layer. The semiconductor layer includes gallium nitride. The inorganic film is provided to conform to the unevenness of the first surface and in contact with the first surface. The inorganic film has main components of silicon and nitrogen. The inorganic film has a refractive index between a refractive index of the gallium nitride and a refractive index of air. An unevenness is formed also in a surface of the inorganic film.Type: GrantFiled: August 16, 2013Date of Patent: January 27, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Akihiro Kojima, Takayoshi Fujii, Yoshiaki Sugizaki
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Patent number: 8936952Abstract: An object is to provide a manufacturing method of a semiconductor device in which a defect in characteristics due to a crack occurring in a semiconductor device is reduced. Provision of a crack suppression layer formed of a metal film in the periphery of a semiconductor element makes it possible to suppress a crack occurring from the outer periphery of a substrate and reduce damage to the semiconductor element. In addition, even if the semiconductor device is subjected to physical forces from the outer periphery in separation and transposition steps, progression (growth) of a crack to the semiconductor device can be suppressed by the crack suppression layer.Type: GrantFiled: June 8, 2011Date of Patent: January 20, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Akihiro Chida
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Patent number: 8936961Abstract: A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.Type: GrantFiled: May 26, 2012Date of Patent: January 20, 2015Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoartabari, Paul A. Lauro, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
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Patent number: 8933806Abstract: The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.Type: GrantFiled: August 20, 2012Date of Patent: January 13, 2015Assignee: Thin Film Electronics ASAInventors: Vivek Subramanian, Patrick Smith, Vikram Pavate, Arvind Kamath, Criswell Choi, Aditi Chandra, James Montague Cleeves
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Patent number: 8921686Abstract: A method to fabricate a photovoltaic device includes forming first and second contact regions at the first surface of a semiconductor donor body. A cleave plane may be formed by implanting ions into the donor body, and a lamina that includes the contact regions is cleaved from the donor body at the cleave plane. The first surface of the lamina may be contacted with a temporary support and fabricated into a photovoltaic device, wherein the lamina comprises the base of the photovoltaic device.Type: GrantFiled: March 21, 2012Date of Patent: December 30, 2014Assignee: GTAT CorporationInventors: Steven M. Zuniga, Christopher J. Petti, Gopal Prabhu
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Patent number: 8916772Abstract: A three-dimensional thin-film semiconductor substrate with selective through-holes is provided. The substrate having an inverted pyramidal structure comprising selectively formed through-holes positioned between the front and back lateral surface planes of the semiconductor substrate to form a partially transparent three-dimensional thin-film semiconductor substrate.Type: GrantFiled: August 8, 2013Date of Patent: December 23, 2014Assignee: Solexel, Inc.Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang
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Patent number: 8912033Abstract: Provided is a method of fabricating a light-emitting diode (LED) device. The method includes providing a substrate having opposite first and second sides. A semiconductor layer is formed on the first side of the substrate. The method includes forming a photoresist layer over the semiconductor layer. The method includes patterning the photoresist layer into a plurality of photoresist components. The photoresist components are separated by openings. The method includes filling the openings with a plurality of thermally conductive components. The method includes separating the semiconductor layer into a plurality of dies using a radiation process that is performed to the substrate from the second side. Each of the first regions of the substrate is aligned with one of the conductive components.Type: GrantFiled: October 8, 2010Date of Patent: December 16, 2014Assignee: TSMC Solid State Lighting Ltd.Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Gordon Kuo
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AUTOMATED FLEXIBLE SOLAR CELL FABRICATION AND INTERCONNECTION UTILIZING ROLLS EXPANDED METALLIC MESH
Publication number: 20140352777Abstract: A method for forming photovoltaic cells comprises providing a first roll of a photovoltaic material and a second roll of an expanded metallic mesh. The photovoltaic material comprises a photoactive material adjacent to a flexible substrate, and the expanded metallic mesh comprises a plurality of openings. Next, an electrically insulating material is provided adjacent to an edge portion of the photovoltaic material. The photovoltaic material from the first roll can then be brought in proximity to the expanded mesh from the second roll to form a nascent photovoltaic cell. The electrically insulating material can be disposed between the expanded metallic mesh and the photovoltaic material. Next, the nascent photovoltaic cell is cut into individual sections to form a plurality of photovoltaic cells.Type: ApplicationFiled: December 6, 2012Publication date: December 4, 2014Inventors: Bruce D. Hachtmann, Christine Tsai, Thomas M. Valeri, Herb Delarosa -
Patent number: 8900925Abstract: In a method for manufacturing a diode, a semiconductor crystal wafer is used to produce a p-n or n-p junction, which extends in planar fashion across the top side of a semiconductor crystal wafer. Separation edges form perpendicularly to the top side of the semiconductor crystal wafer, which edges extend across the p-n or n-p junction. The separation of the semiconductor crystal wafer is achieved in that, starting from a disturbance, a fissure is propagated by local heating and local cooling of the semiconductor crystal wafer. The separation fissure thus formed extends along crystal planes of the semiconductor crystal, which avoids the formation of defects in the area of the p-n or n-p junction.Type: GrantFiled: June 19, 2013Date of Patent: December 2, 2014Assignee: Robert Bosch GmbHInventors: Richard Spitz, Alfred Goerlach, Robert Kolb
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Patent number: 8895345Abstract: The present invention provides a dicing method that achieves excellent dicing properties at low costs by removing a metal film through a metal processing operation with a diamond tool and then performing pulse laser beam irradiation. The dicing method is a method of dicing a substrate to be processed, devices being formed in the substrate to be processed, a metal film being formed on one surface of the substrate to be processed.Type: GrantFiled: June 13, 2011Date of Patent: November 25, 2014Assignee: Toshiba Kikai Kabushiki KaishaInventor: Takanobu Akiyama
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Patent number: 8883565Abstract: In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process.Type: GrantFiled: October 4, 2011Date of Patent: November 11, 2014Assignee: Infineon Technologies AGInventors: Mathias Vaupel, Sebastian Bernrieder, Adolf Koller, Stefan Martens
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Patent number: 8884392Abstract: Disclosed herein is a method of manufacturing a solid state imaging device, including the steps of: forming a light receiving portion in a light receiving area of a semiconductor substrate; forming a pad portion in a pad area of the semiconductor substrate; forming a microlens material layer over the light receiving portion and the pad portion; providing the microlens material layer with a microlens corresponding to the light receiving portion; forming a low-reflection material layer on the microlens material layer; etching the microlens material layer and the low-reflection material layer over the pad portion to form an opening; and imparting hydrophilicity to a surface of the low-reflection material layer and an inside portion of the opening by a normal temperature oxygen radical treatment.Type: GrantFiled: November 22, 2013Date of Patent: November 11, 2014Assignee: Sony CorporationInventors: Yoshinori Toumiya, Ina Hori, Tadayuki Dofuku, Hitomi Kamiya, Atsushi Yamamoto, Taichi Natori
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Patent number: 8877077Abstract: A method of printing comprises the steps of: providing a solid state material having an exposed surface; applying an auxiliary layer to the exposed surface to form a composite structure, the auxiliary layer having a stress pattern; subjecting the composite structure to conditions facilitating fracture of the solid state material along a plane at a depth therein; and removing the auxiliary layer and, therewith, a layer of the solid state material terminating at the fracture depth, wherein an exposed surface of the removed layer of solid state material has a surface topology corresponding to the stress pattern.Type: GrantFiled: December 18, 2009Date of Patent: November 4, 2014Assignee: Siltectra GmbHInventor: Lukas Lichtensteiger