Substrate Dicing Patents (Class 438/68)
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Publication number: 20140322857Abstract: A method of fabricating a semiconductor image sensor device is disclosed. A plurality of radiation-sensing regions is formed in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. An opening is formed in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The opening is then filled with an organic material.Type: ApplicationFiled: July 3, 2014Publication date: October 30, 2014Inventors: Shou-Shu Lu, Hsun-Ying Huang, Huang-Hsin Jung, Chun-Mao Chiu, Chia-Chi Hsiao, Yung-Cheng Chang
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Patent number: 8871540Abstract: A laser dicing method includes: placing a workpiece substrate on a stage; generating a clock signal; emitting a pulse laser beam synchronous with the clock signal; switching irradiation and non-irradiation of the workpiece substrate with the pulse laser beam in a unit of light pulse in synchronization with the clock signal to perform first irradiation of the pulse laser beam on a first straight line by controlling the pulse laser beam using a pulse picker; performing second irradiation of the pulse laser beam on a second straight line, which is adjacent to the first straight line in a substantially parallel fashion, after the first irradiation; and forming a crack reaching a workpiece substrate surface on the workpiece substrate by the first irradiation and the second irradiation.Type: GrantFiled: July 24, 2012Date of Patent: October 28, 2014Assignee: Toshiba Kikai Kabushiki KaishaInventor: Shoichi Sato
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Patent number: 8871533Abstract: A solar cell making method includes steps of making a round P-N junction preform by (a) stacking a P-type silicon layer and a N-type silicon layer on top of each other, and (b) forming a P-N junction near an interface between the P-type silicon layer and the N-type silicon layer, wherein the round P-N junction preform defines a first surface and a second surface; forming a first electrode preform on the first surface and forming a second electrode preform on the second surface, thereby forming a round solar cell preform; and forming a photoreceptive surface with the P-N junction exposed on the photoreceptive surface by cutting the round solar cell preform into a plurality of arc shaped solar cells, the photoreceptive surface being on a curved surface of the arc shaped solar cell and being configured to receive incident light beams.Type: GrantFiled: July 24, 2012Date of Patent: October 28, 2014Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
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Patent number: 8852988Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.Type: GrantFiled: June 4, 2013Date of Patent: October 7, 2014Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Hyung-Sun Jang, Woon-Seong Kwon, Tae-Je Cho, Un-Byoung Kang, Jung-Hwan Kim
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Patent number: 8846432Abstract: Frontside-illuminated barrier infrared photodetector devices and methods of fabrication are disclosed. In one embodiment, a frontside-illuminated barrier infrared photodetector includes a transparent carrier substrate, and a plurality of pixels. Each pixel of the plurality of pixels includes an absorber layer, a barrier layer on the absorber layer, a collector layer on the barrier layer, and a backside electrical contact coupled to the absorber layer. Each pixel has a frontside and a backside. The absorber layer and the barrier layer are non-continuous across the plurality of pixels, and the barrier layer of each pixel is closer to a scene than the absorber layer of each pixel. A plurality of frontside common electrical contacts is coupled to the frontside of the plurality of pixels, wherein the frontside of the plurality of pixels and the plurality of frontside common electrical contacts are bonded to the transparent carrier substrate.Type: GrantFiled: September 13, 2012Date of Patent: September 30, 2014Assignee: L-3 Communications Cincinnati Electronics CorporationInventors: Robert A. Jones, David Forrai, Richard L. Rawe, Jr.
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Patent number: 8841161Abstract: The invention provides for a semiconductor wafer with a metal support element suitable for the formation of a flexible or sag tolerant photovoltaic cell. A method for forming a photovoltaic cell may comprise providing a semiconductor wafer have a thickness greater than 150 ?m, the wafer having a first surface and a second surface opposite the first and etching the semiconductor wafer a first time so that the first etching reduces the thickness of the semiconductor wafer to less than 150 ?m. After the wafer has been etched a first time, a metal support element may be constructed on or over the first surface; and a photovoltaic cell may be fabricated, wherein the semiconductor wafer comprises the base of the photovoltaic cell.Type: GrantFiled: February 5, 2012Date of Patent: September 23, 2014Assignee: GTAT.CorporationInventors: Venkatesan Murali, Gopal Prabhu, Thomas Edward Dinan, Jr., Orion Leland
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Publication number: 20140273329Abstract: A multi-step scribing operation is provided for forming scribe lines in solar panels to form multiple interconnected cells on a solar panel substrate. The multi-step scribing operation includes at least one step utilizing a nanosecond laser cutting operation. The nanosecond laser cutting operation is followed by a mechanical cutting operation or a subsequent nanosecond laser cutting operation. In some embodiments, the multi-step scribing operation produces a two-tiered scribe line profile and the method prevents local shunting and minimizes active area loss on the solar panel.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: TSMC SOLAR LTD.Inventors: Hsuan-Sheng YANG, Kwang-Ming LIN, Yi-Feng HUANG, Li-Wei CHANG, Chia-Hung TSAI
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Patent number: 8835283Abstract: A fabrication method for producing semiconductor chips with enhanced die strength comprises following steps: forming a semiconductor wafer with enhanced die strength by comprising the substrate, the active layer on the front side of the substrate and the backside metal layer on the backside of the substrate, wherein at least one integrated circuit forms in the active layer; forming a protection layer on a front side of the semiconductor wafer; dicing the semiconductor wafer by at least one laser dicing process and removing the laser dicing residues and removing said protection layer by at least one etching process, whereby plural semiconductor chips with enhanced die strength are produced, and wherein the backside metal layer of said semiconductor chip fully covers the backside of said semiconductor chip after dicing.Type: GrantFiled: August 20, 2013Date of Patent: September 16, 2014Assignee: WIN Semiconductors Corp.Inventor: Chang-Hwang Hua
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Patent number: 8828891Abstract: For modulating laser light for forming a modified region SD3 at an intermediate position between a position closer to a rear face 21 and a position closer to a front face 3 with respect to an object 1, a quality pattern J having a first brightness region extending in a direction substantially orthogonal to a line 5 and second brightness regions located on both sides of the first brightness region in the extending direction of the line 5 is used. After forming modified regions SD1, SD2 at positions closer to the rear face 21 but before forming modified regions SD4, SD5 at positions closer to the rear face 21 while using the front face 3 as a laser light entrance surface, the modified region SD3 is formed at the intermediate position by irradiation with laser light modulated according to a modulation pattern including the quality pattern J.Type: GrantFiled: January 5, 2011Date of Patent: September 9, 2014Assignee: Hamamatsu Photonics K.K.Inventor: Takeshi Sakamoto
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Patent number: 8822258Abstract: A wafer-level bonding method for fabricating wafer level camera lenses is disclosed. The method includes: providing a lens wafer including lenses arranged in an array and a sensor wafer including sensors arranged in an array; measuring and analyzing an FFL of each lens to obtain a corresponding FFL compensation value for each lens; forming a thin transparent film (TTF) on each sensor of the sensor wafer, and the thickness of TTF is determined by the FFL compensation value of the corresponding lens; aligning and bonding the lens wafer with the sensor wafer having TTFs formed thereon. Since the focal length of each lens is adjusted to compensate the FFL of the lens by adding a TTF of transparent optical material with an index of refraction that is similar to the index of refraction of the sensor cover glass, the FFL variation of each camera lens can be reduced.Type: GrantFiled: April 18, 2013Date of Patent: September 2, 2014Assignee: OmniVision Technologies (Shanghai) Co., Ltd.Inventor: Regis Fan
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Patent number: 8809109Abstract: A method for manufacturing a thin-film photovoltaic device includes providing a glass substrate contained sodium species. The glass substrate comprising a surface region and a peripheral edge region surround the surface region. The method further includes forming a barrier material overlying the surface region and partially overlying the peripheral edge region and forming a conductor material overlying the barrier material. Additionally, the method includes forming at least a first trench in a vicinity of the peripheral edge region to remove substantially the conductor material therein and forming precursor materials overlying the patterned conductor material. Furthermore, the method includes thermally treating the precursor materials to transform the precursor materials into a film of photovoltaic absorber. The first trench is configured to maintain the film of photovoltaic absorber substantially free from peeling off the conductor material.Type: GrantFiled: May 21, 2012Date of Patent: August 19, 2014Assignee: Stion CorporationInventors: Laila Dounas, Robert D. Wieting, Chester A. Farris, III
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Patent number: 8802479Abstract: An improved method for interconnecting thin film solar cells to form solar cell modules is provided, the method comprising using a flat metallic mesh formed from a thin metallic strip to provide a current collection grid over a thin film solar cell. The method is particularly useful for forming interconnections between thin film solar cells deposited on flexible substrates. The rectangular cross sectional shape of the mesh elements provides an increased area of electrical contact to the solar cell compared to the small tangential area provided by elements of circular cross section. Mesh elements can be made higher rather than wider to improve conductivity without proportionally increasing shading loss. Various coatings can be applied to the mesh to improve its performance, provide corrosion resistance, and improve its cosmetic appearance.Type: GrantFiled: June 3, 2010Date of Patent: August 12, 2014Assignee: NuvoSun, Inc.Inventors: David B. Pearce, Bruce D. Hachtmann, Liguang Gong, Thomas M. Valeri, Dennis R. Hollars
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Patent number: 8803270Abstract: A light sensor is described that includes an IR interference filter and at least one color interference filter integrated on-chip. The light sensor comprises a semiconductor device (e.g., a die) that includes a substrate. Photodetectors are disposed proximate to the surface of the substrate. An IR interference filter is disposed over the photodetectors. The IR interference filter is configured to filter infrared light from light received by the light sensor to at least substantially block infrared light from reaching the photodetectors. At least one color interference filter is disposed proximate to the IR interference filter. The color interference filter is configured to filter visible light received by the light sensor to pass light in a limited spectrum of wavelengths (e.g., light having wavelengths between a first wavelength and a second wavelength) to at least one of the photo detectors.Type: GrantFiled: October 2, 2013Date of Patent: August 12, 2014Assignee: Maxim Integrated Products, Inc.Inventors: Prashanth Holenarsipur, Zhihai Wang, Nicole D. Kerness
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Publication number: 20140217542Abstract: A semiconductor device, which is configured as a backside illuminated solid-state imaging device, includes a stacked semiconductor chip which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit; a semiconductor-removed region in which a semiconductor section of a part of the first semiconductor chip unit is completely removed; and a plurality of connection wirings which is formed in the semiconductor-removed region and connects the first and second semiconductor chip units to each other.Type: ApplicationFiled: April 9, 2014Publication date: August 7, 2014Applicant: Sony CorporationInventors: Kazuichiroh Itonaga, Machiko Horiike
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Patent number: 8796063Abstract: A method of fabricating a solar cell includes forming a front contact layer over a substrate, and the front contact layer is optically transparent at specified wavelengths and electrically conductive. A first scribed area is scribed through the front contact layer to expose a portion of the substrate. A buffer layer doped with an n-type dopant is formed over the front contact layer and the first scribed area. An absorber layer doped with a p-type dopant is formed over the buffer layer. A back contact layer that is electrically conductive is formed over the absorber layer.Type: GrantFiled: August 13, 2013Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Chin Lee, Wen-Tsai Yen, Liang-Sheng Yu, Yung-Sheng Chiu
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Patent number: 8790950Abstract: A method of manufacturing an optical sensor includes providing a semiconductor wafer including a plurality of pixel areas, providing a light transmissive substrate including a light transmissive wafer with a plurality of light transmissive members attached thereto, the plurality of light transmissive members being arranged on a first main surface of the light transmissive wafer and each of plurality of light transmissive members emitting ? rays, an amount of the ? rays being smaller than or equal to 0.05 c/cm2·h, fixing the light transmissive substrate onto the semiconductor wafer together by a fixing member, and dividing the semiconductor wafer and the light transmissive substrate that are fixed together into individual pieces.Type: GrantFiled: August 16, 2011Date of Patent: July 29, 2014Assignee: Canon Kabushiki KaishaInventors: Takanori Suzuki, Tadashi Kosaka, Koji Tsuduki, Yasuhiro Matsuki, Shin Hasegawa, Akiya Nakayama
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Patent number: 8778719Abstract: The linear semiconductor substrate 1 or 2 of the present invention comprises at least one desired thin film 4 formed on a linear substrate 3 having a length ten or more times greater than a width, thickness, or diameter of the linear substrate itself. Adopting semiconductor as the thin film 4 forms a linear semiconductor thin film. The linear semiconductor substrate 1 or 2 of the present invention is produced by utilizing a fiber-drawing technique which is a fabricating technique of optical fibers.Type: GrantFiled: September 6, 2011Date of Patent: July 15, 2014Assignee: Furukawa Electric Co., Ltd.Inventors: Toshihiro Nakamura, Nobuaki Orita, Hisashi Koaizawa, Kenkichi Suzuki, Hiroshi Kuraseko, Michio Kondo
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Patent number: 8778780Abstract: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.Type: GrantFiled: October 11, 2006Date of Patent: July 15, 2014Assignee: SemiLEDS Optoelectronics Co., Ltd.Inventors: Trung-Tri Doan, Chen-Fu Chu, Hao-Chun Cheng, Feng-Hsu Fan
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Patent number: 8765516Abstract: A reusable substrate and method for forming single crystal silicon solar cells are described. A method of forming a photovoltaic cell includes forming an intermediate layer on a monocrystalline silicon substrate, forming a monocrystalline silicon layer on the intermediate layer, and forming electrical features in the monocrystalline silicon layer. The method further includes forming openings in the monocrystalline silicon layer, and detaching the monocrystalline silicon layer from the substrate by selectively etching the intermediate layer through the openings.Type: GrantFiled: February 7, 2013Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
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Publication number: 20140170798Abstract: Photovoltaic modules may include multiple flexible thin film photovoltaic cells electrically connected in series, and laminated to a substantially transparent top sheet having a conductive grid pattern facing the cells. Methods of manufacturing photovoltaic modules including integrated multi-cell interconnections are provided. Methods may include steps of coordinating, integrating, and registering multiple rolls of substrates in continuous processes.Type: ApplicationFiled: January 9, 2014Publication date: June 19, 2014Applicant: Global Solar Energy, Inc.Inventors: Scott WIEDEMAN, Jeffrey S. BRITT, Zulima RHODES, Eric SHEEHAN
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Patent number: 8753957Abstract: This invention relates to a method for producing solar cells, and photovoltaic panels thereof. The method for producing solar panels comprises employing a number of semiconductor wafers and/or semiconductor sheets of films prefabricated to prepare them for back side metallization, which are placed and attached adjacent to each other and with their front side facing downwards onto the back side of the front glass, before subsequent processing that includes depositing at least one metal layer covering the entire front glass including the back side of the attached wafers/sheets of films. The metallic layer is then patterned/divided into electrically isolated contacts for each solar cell and into interconnections between adjacent solar cells.Type: GrantFiled: April 2, 2009Date of Patent: June 17, 2014Assignee: Rec Solar Pte. Ltd.Inventors: Martin Nese, Erik Sauar, Andreas Bentzen, Paul Alan Basore
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Patent number: 8748291Abstract: A method for testing a strip of MEMS devices, the MEMS devices including at least a respective die of semiconductor material coupled to an internal surface of a common substrate and covered by a protection material; the method envisages: detecting electrical values generated by the MEMS devices in response to at least a testing stimulus; and, before the step of detecting, at least partially separating contiguous MEMS devices in the strip. The step of separating includes defining a separation trench between the contiguous MEMS devices, the separation trench extending through the whole thickness of the protection material and through a surface portion of the substrate, starting from the internal surface of the substrate.Type: GrantFiled: September 27, 2012Date of Patent: June 10, 2014Assignees: STMicroelectronics S.r.l., STMicroelectronics Ltd (Malta)Inventors: Mark Anthony Azzopardi, Conrad Cachia, Stefano Pozzi
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Publication number: 20140154831Abstract: In different embodiments, a method is provided for processing at least one crystalline Silicon-wafer or a Solar-cell wafer. The method may include: a movement of the wafer with respect to a laser producing a laser beam; and therefore the formation of a laser channel in the wafer by means of a laser beam, wherein a thermal budget applied on the wafer by means of the laser beam is reduced in the peripheral region of the wafer, wherein the peripheral region includes a wafer edge, through which the laser beam exits the wafer after formation of the laser channel.Type: ApplicationFiled: December 3, 2013Publication date: June 5, 2014Applicant: SolarWorld Innovations GmbHInventors: Martin Kutzer, Joachim Koenig, Matthias Richter
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Patent number: 8742411Abstract: An adhesive film, and a product and method of encapsulating an organic electronic device (OED) using the same are provided. The adhesive film serves to encapsulate the OED and includes a curable hot-melt adhesive layer including a curable resin and a moisture absorbent, and the curable hot-melt adhesive layer includes a first region coming in contact with the OED upon encapsulation of the OED and a second region not coming in contact with the OED. Also, the moisture absorbent is present at contents of 0 to 20% and 80 to 100% in the first and second regions, respectively, based on the total weight of the moisture absorbent in the adhesive layer.Type: GrantFiled: May 2, 2013Date of Patent: June 3, 2014Assignee: LG Chem, Ltd.Inventors: Hyun Jee Yoo, Yoon Gyung Cho, Jung Sup Shim, Suk Chin Lee, Kwang Jin Jeong, Suk Ky Chang
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Patent number: 8742522Abstract: A method of making a semiconductor radiation detector wherein the metal layers which serve as the cathode and anode electrodes are recessed from the designated prospective dice lines which define the total upper and lower surface areas for each detector such that the dicing blade will not directly engage the metal during dicing and therefore prevent metal from intruding upon (smearing) the vertical side walls of the detector substrate.Type: GrantFiled: April 10, 2012Date of Patent: June 3, 2014Assignee: eV Products, Inc.Inventors: Handong Li, Michael Prokesch, John F. Eger
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Patent number: 8735212Abstract: A silicon solar cell is manufactured by providing a carrier plate, and by applying a first contact pattern to the carrier plate. The first contact pattern includes a set of first laminar contacts. The silicon solar cell is further manufactured by applying a multitude of silicon slices to the first contact pattern, and by applying a second contact pattern to the multitude of silicon slices. Each first laminar contact of the set of first laminar contacts is in spatial laminar contact with maximally two silicon slices. The second contact pattern includes a set of second laminar contacts. Each second laminar contact of the set of second laminar contacts is in spatial laminar contact with maximally two silicon slices.Type: GrantFiled: January 13, 2009Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Rainer Klaus Krause, Gerd Pfeiffer, Hans-Juergen Eickelmann, Thorsten Muehge
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Patent number: 8728849Abstract: A method of laser cutting through dissimilar materials separated by a metal foil. A material stack includes a semiconductor layer or film, with a metal foil layer attached to the back surface. The metal foil layer is attached to an insulative support material layer. A laser parameter is selected and optimized for the material stack. A laser beam creates a kerf in the material stack down to the metal foil layer. The laser beam removes metal through the kerf primarily by gasification rather than melting. Kerf formation continues after optimization of the laser parameter for removal of material from the remaining layers. A debris field resulting from the laser cutting of the metal layer is reduced and/or a portion of the debris is removed in an assisted manner as the beam cuts. The materials are diced by cutting the kerf through all materials.Type: GrantFiled: August 31, 2011Date of Patent: May 20, 2014Assignee: Alta Devices, Inc.Inventors: Laila Mattos, Daniel G. Patterson
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Patent number: 8716070Abstract: A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.Type: GrantFiled: March 15, 2013Date of Patent: May 6, 2014Assignee: Siliconware Precision Industries Co. Ltd.Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
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Patent number: 8710510Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.Type: GrantFiled: June 18, 2007Date of Patent: April 29, 2014Assignee: Cree, Inc.Inventors: Qingchun Zhang, Sei-Hyung Ryu, Charlotte Jonas, Anant K. Agarwal
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Publication number: 20140113390Abstract: A method for producing singulated semiconductor components includes providing a starting substrate. An etching process is carried out to form depressions at a side of the starting substrate. The depressions are arranged in the region of the semiconductor components to be produced. Walls present between the depressions are arranged in the region of separating regions provided for severing the starting substrate. The method furthermore comprises forming a metallic layer on the side of the starting substrate with the depressions and walls and carrying out a further etching process for severing the starting substrate in the separating regions and forming the singulated semiconductor components.Type: ApplicationFiled: August 23, 2013Publication date: April 24, 2014Inventors: Andreas Ploessl, Heribert Zull
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Publication number: 20140103480Abstract: A mask for partially blocking ultraviolet rays in TFT glass substrate manufacturing process is disclosed. The mask includes a panel pattern area for forming the panel patterns, and an additional pattern area for forming additional patterns in a rim of the panel pattern area. In addition, a TFT glass substrate and the manufacturing thereof are also disclosed. By arranging the additional patterns in the rim of the panel patterns, the microstructures in the rim of the panel patterns are substantially the same with that in the middle of the panel patterns.Type: ApplicationFiled: October 19, 2012Publication date: April 17, 2014Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY COInventors: Pei Lin, Hua Zheng, Liangdong Wu, Shangpan Chen, Long Pan, Pan Gao, Mingwen Lin, Shyh-Feng Chen
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Patent number: 8697478Abstract: A removable cover system for protecting solar cells from exposure to moisture during fabrication processes. The cover system includes a cover having a configuration that complements the configuration of a solar cell substrate to be processed in an apparatus where moisture is present. A resiliently deformable seal member attached to the cover is positionable with the cover to engage and seal the top surface of the substrate. In one embodiment, the cover is dimensioned and arranged so that the seal member engages the peripheral angled edges and corners of the substrate for preventing the ingress of moisture beneath the cover. An apparatus for fabricating a solar cell using the cover and associated method are also disclosed.Type: GrantFiled: September 6, 2012Date of Patent: April 15, 2014Assignee: TSMC Solar Ltd.Inventors: Chih-Wei Huang, Keng-Hsin Chi, Chien-Nan Lin, Hua-Tso Wei
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Patent number: 8673743Abstract: A wafer is divided by setting the focal point of a laser beam inside the wafer at positions corresponding to division lines, thereby forming modified layers inside the wafer along the division lines. Each modified layer has a thickness ranging from the vicinity of the front side of the wafer to the vicinity of the back side of the wafer. An etching gas or an etching liquid is supplied to the wafer to erode the modified layers, thereby dividing the wafer into individual devices. The modified layers are not crushed, so fine particles are not generated in dividing the wafer. Accordingly, fine particles do not stick to the surface of each device and cause a reduction in quality. Further, since the modified layers are removed by etching, it is possible to prevent a reduction in die strength of each device due to the remainder of the modified layers.Type: GrantFiled: August 29, 2012Date of Patent: March 18, 2014Assignee: Disco CorporationInventor: Kazuhisa Arai
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Patent number: 8674377Abstract: An optoelectonice device package, an array of optoelectronic device packages and a method of fabricating an optoelectronic device package. The array includes a plurality of optoelectronic device packages, each enclosing an optoelectronic device, and positioned in at least one row. Each package including two geometrically parallel transparent edge portions and two geometrically parallel non-transparent edge portions, oriented substantially orthogonal to the transparent edge portions. The transparent edge portions are configured to overlap at least one adjacent package, and may be hermetically sealed. The optoelectronic device portion fabricated using R2R manufacturing techniques.Type: GrantFiled: August 30, 2011Date of Patent: March 18, 2014Assignee: General Electric CompanyInventor: Donald Seton Farquhar
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Patent number: 8669190Abstract: In a method for manufacturing a semiconductor device, a process of providing a semiconductor wafer having a wiring layer having conductive patterns and a plurality of insulation films containing a first insulation film surrounding side surfaces of the conductive patterns are provided. After the process of providing the semiconductor wafer, a process of removing some regions of the plurality of insulation films to form openings is provided. Herein, the first insulation film is disposed to a position closer to the circumference of the semiconductor wafer than a position closest to the outermost circumference of the wafer among the arrangement positions of the conductive patterns.Type: GrantFiled: February 6, 2012Date of Patent: March 11, 2014Assignee: Canon Kabushiki KaishaInventors: Kenji Togo, Hiroaki Sano
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Publication number: 20140061840Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regionsType: ApplicationFiled: August 28, 2013Publication date: March 6, 2014Applicant: HAMAMATSU PHOTONICS K.K.Inventors: Hiroshi OGURI, Yoshitaka ISHIKAWA, Akira SAKAMOTO, Tomoya TAGUCHI, Yoshimaro FUJII
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Patent number: 8664025Abstract: The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.Type: GrantFiled: July 20, 2011Date of Patent: March 4, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Daniel Richter, Frank Kuechenmeister
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Publication number: 20140048128Abstract: A concentrator-type photovoltaic (CPV) device includes a solar cell comprising a substrate including a light receiving surface and a mounting surface opposite the light receiving surface. A conductive through-substrate interconnect having insulated sidewalls extends through the substrate from the mounting surface to the light receiving surface to provide an electrical connection to a conductive terminal on the light receiving surface. A lens support structure is formed on the light receiving surface, and a lens element is provided on the support structure opposite the light receiving surface. The support structure supports and aligns the lens element with the light receiving surface to concentrate incident light thereon. Related fabrication processes are also discussed.Type: ApplicationFiled: March 14, 2013Publication date: February 20, 2014Applicant: Semprius, Inc.Inventors: Matthew Meitl, Christopher Bower
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Publication number: 20140048123Abstract: A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.Type: ApplicationFiled: October 30, 2013Publication date: February 20, 2014Applicant: Sandia CorporationInventors: Anna Tauke-Pedretti, Gregory N. Nielson, Jeffrey G. Cederberg, Jose Luis Cruz-Campa
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Patent number: 8653629Abstract: A semiconductor device has a semiconductor substrate. The semiconductor device has a plurality of LSI regions that are formed on the semiconductor substrate and are provided with a first power supply wiring layer including a first power supply wire. The semiconductor device has a first power supply terminal formed on the semiconductor substrate. The semiconductor device has a second power supply wiring layer including a second power supply wire that electrically connects the first power supply wire and the first power supply terminal, the second power supply wiring layer is formed in a dicing region between the LSI regions along a dicing line that separates the LSI regions and the dicing line region. A first barrier metal film is formed at least in the LSI regions at a boundary between the first power supply wire and the second power supply wire.Type: GrantFiled: September 19, 2011Date of Patent: February 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Seta, Yojiro Hamasaki
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Publication number: 20140045293Abstract: A method for fabricating thin film solar cells for a concentrated photovoltaic system uses three shadow masks. The first mask, used to deposit a back contact layer, has multiple horizontal and vertical lines defining columns and rows of cells, and multiple tabs each located in a cell along a center of a vertical border. The second mask, used to deposit a CIGS absorption layer, a window layer and a transparent contact layer, is similar to the first mask except the tabs are located along the opposite vertical border of the cells. The third mask, used to deposit a metal grid layer, has multiple bus bar openings and finger openings. Each bus bar opening is located along a horizontal center line of a cell and overlaps the second tab of a neighboring cell. The cells in a horizontal row are connected in series, forming a linear solar receiver.Type: ApplicationFiled: August 7, 2012Publication date: February 13, 2014Applicant: PU NI TAI YANG NENG (HANGZHOU) CO., LIMITEDInventors: Dong Wang, Pingrong Yu, Xuegeng Li
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Patent number: 8647966Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a die attach film, an adhesive and a base film. The die attach film is cut with the sawing blade. During the cutting operation, a contact portion of the sawing blade engages one of the layers and moves at least partly in one direction. While the contact portion of the sawing blade engages the layer, the support structure moves in the opposite direction. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.Type: GrantFiled: June 9, 2011Date of Patent: February 11, 2014Assignee: National Semiconductor CorporationInventors: Ken Fei Lim, You Chye How, Kooi Choon Ooi
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Publication number: 20140038329Abstract: Methods and apparatus are provided for forming an electronic device from a lamina and an epitaxially grown semiconductor material. The method includes providing a donor body comprising a top surface, epitaxially growing a semiconductor material on the top surface and implanting the top surface of the donor body with an ion dosage to form a cleave plane. After implantation, a lamina may be exfoliated from the donor body, wherein the top surface of the donor body becomes a first surface of the lamina. Exfoliating the lamina forms a second surface of the lamina, wherein the first surface is opposite the second surface. A metal support may be constructed on the lamina.Type: ApplicationFiled: August 1, 2013Publication date: February 6, 2014Applicant: GTAT CorporationInventor: Christopher J. Petti
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Patent number: 8642447Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor wafer including a silicon substrate and a laminate having a compound semiconductor layer; etching and removing a part of the laminate in a thickness direction to form trench regions in a grid, each trench region including a plurality of stripe grooves extending in parallel to each other; filling the groove with a material having a lower hardness than the compound semiconductor layer to form a buried region; and dividing the semiconductor wafer into a plurality of chips by dicing using a blade at a dicing line which is defined within the trench region and includes a plurality of the buried regions.Type: GrantFiled: February 9, 2011Date of Patent: February 4, 2014Assignee: Sanken Electric Co., Ltd.Inventors: Hironori Itou, Akio Iwabuchi
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Publication number: 20140027872Abstract: A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL.Type: ApplicationFiled: July 25, 2012Publication date: January 30, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Wen-Chih Chiou, Jing-Cheng Lin
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Patent number: 8637341Abstract: A semiconductor module. In one embodiment, at least two semiconductor chips are placed on a carrier. The at least two semiconductor chips are then covered with a molding material. An exposed portion of the at least two semiconductor chips is provided. A first layer of conductive material is applied over the exposed portion of the at least two semiconductor chips to electrically connect to a contact pad on the exposed portion of the at least two semiconductor chips. The at least two semiconductor chips are singulated.Type: GrantFiled: March 12, 2008Date of Patent: January 28, 2014Assignee: Infineon Technologies AGInventors: Ralf Otremba, Josef Hoeglauer, Helmut Strack, Xaver Schloegel
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Patent number: 8633089Abstract: An array of semiconductor components, comprising a first plurality of semiconductor components and a second plurality of semiconductor components held on a carrier, is bonded onto one or more substrates. The first plurality of semiconductor components is first located for pick-up by a transfer device, and each semiconductor component comprised in the first plurality of semiconductor components is picked up with the transfer device and is bonded onto a respective bonding position on the one or more substrates. After the first plurality of semiconductor components have been picked up and bonded, the carrier is rotated and the second plurality of semiconductor components is located for pick-up by the transfer device. Thereafter, each semiconductor component comprised in the second plurality of semiconductor components is picked up with the transfer device and is bonded onto a respective bonding position on the one or more substrates.Type: GrantFiled: March 28, 2011Date of Patent: January 21, 2014Assignee: ASM Assembly Automation LtdInventors: Man Chung Ng, Keung Chau
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Publication number: 20140014977Abstract: An optoelectronic semiconductor device includes an optoelectronic semiconductor layer sequence on a metal carrier element, which includes as a first component silver and as a second component a material having a lower coefficient of thermal expansion than silver, wherein the first and second components are intermixed in the metal carrier element.Type: ApplicationFiled: February 24, 2012Publication date: January 16, 2014Applicant: OSRAM Opto Semiconductors GmbHInventors: Helmut Fischer, Andreas Plössl
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Patent number: 8624341Abstract: A light sensor is described that includes an IR cut interference filter and at least one color interference filter integrated on-chip. The light sensor comprises a semiconductor device (e.g., a die) that includes a substrate. Photodetectors are formed in the substrate proximate to the surface of the substrate. An IR cut interference filter is disposed over the photodetectors. The IR cut interference filter is configured to filter infrared light from light received by the light sensor to at least substantially block infrared light from reaching the photodetectors. At least one color interference filter is disposed proximate to the IR cut interference filter. The color interference filter is configured to filter visible light received by the light sensor to pass light in a limited spectrum of wavelengths (e.g., light having wavelengths between a first wavelength and a second wavelength) to at least one of the photodetectors.Type: GrantFiled: July 21, 2011Date of Patent: January 7, 2014Assignee: Maxim Integrated Products, Inc.Inventors: Prashanth Holenarsipur, Zhihai Wang, Nicole Dorene Kerness
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Patent number: 8623512Abstract: An adhesive composition for stealth dicing of a semiconductor, an adhesive film, and a semiconductor device including the adhesive film, the adhesive composition including a polymer resin, the polymer resin having a glass transition temperature of about 5° C. to about 35° C., an epoxy resin, the epoxy resin including a liquid epoxy resin and a solid epoxy resin, a phenolic resin curing agent, an inorganic filler, a curing catalyst, and a silane coupling agent.Type: GrantFiled: December 16, 2010Date of Patent: January 7, 2014Assignee: Cheil Industries, Inc.Inventors: Ah Ram Pyun, Jae Hyun Cho, Ki Tae Song