Substrate Dicing Patents (Class 438/68)
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Patent number: 8623137Abstract: A method for slicing a shaped silicon ingot includes providing a single crystal silicon boule characterized by a cropped structure including a first end-face, a second end-face, and a length along an axis in an <100> crystallographic direction substantially vertically extending from the first end-face to the second end-face. The method further includes cutting the single crystal silicon boule substantially through an {110} crystallographic plane in parallel to the axis to separate the single crystal silicon boule into a first portion with a first surface and a second portion with a second surface. Additionally, the method includes exposing either the first surface of the first portion or the second surface of the second portion and performing a layer transfer process to form a single crystal silicon sheet from either the first surface of the first portion or from the second surface of the second portion.Type: GrantFiled: April 10, 2009Date of Patent: January 7, 2014Assignee: Silicon Genesis CorporationInventor: Francois J. Henley
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Publication number: 20140001588Abstract: Monolithic optical sensor devices, and methods for fabricating such devices, are described herein. In an embodiment, a semiconductor wafer substrate includes a plurality of photodetector (PD) regions. A wafer-level inorganic dielectric optical filter is deposited and thereby formed over at least a subset of the plurality of PD regions. One or more wafer-level organic color filter(s) is/are deposited and thereby formed on one or more selected portion(s) of the wafer-level inorganic dielectric optical filter that is/are over selected ones of the PD regions. For example, an organic red filter, an organic green filter and an organic blue filter can be over, respectively, portions of the wafer-level inorganic dielectric optical filter that are over first, second and third PD regions.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Applicant: INTERSIL AMERICAS LLCInventors: Michael I-Shan Sun, Francois Hebert, Kenneth C. Dyer, Eric S. Lee
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Patent number: 8617928Abstract: Provided is a dicing die-bonding film which is excellent in balance between retention of a semiconductor wafer upon dicing and releasability upon picking up. Disclosed is a dicing die-bonding film comprising a dicing film having a pressure-sensitive adhesive layer on a substrate material, and a die-bonding film formed on the pressure-sensitive adhesive layer, wherein the pressure-sensitive adhesive layer contains a polymer including an acrylic acid ester as a main monomer, 10 to 40 mol % of a hydroxyl group-containing monomer based on the acrylic acid ester, and 70 to 90 mol % of an isocyanate compound having a radical reactive carbon-carbon double bond based on the hydroxyl group-containing monomer, and is also cured by irradiation with ultraviolet rays under predetermined conditions after film formation on the substrate material, and wherein the die-bonding film contains an epoxy resin, and is also bonded on the pressure-sensitive adhesive layer after irradiation with ultraviolet rays.Type: GrantFiled: December 16, 2008Date of Patent: December 31, 2013Assignee: Nitto Denko CorporationInventors: Katsuhiko Kamiya, Takeshi Matsumura, Shuuhei Murata, Hironao Ootake
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Patent number: 8609467Abstract: Provided are: a lead frame enabling efficient manufacturing of multiple circuit devices; and a method for manufacturing a circuit device using the same. In the lead frame of the present invention, units are arranged and frame-shaped first and second supporters are provided around the units to mechanically support the units. Moreover, a half groove is provided in the first supporter at a portion on an extended line of a dividing line defined at a boundary between each adjacent two of the units. Furthermore, a penetration groove penetrating a part of the second supporter at a portion on an extended line of another dividing line is provided.Type: GrantFiled: March 31, 2009Date of Patent: December 17, 2013Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Tetsuya Fukushima, Takashi Kitazawa
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Patent number: 8609512Abstract: An improved method for singulation of compound electronic devices is presented. Compound electronic devices are manufactured by combining two or more substrates into an assembly containing multiple devices. Presented are methods for singulation of compound electronic devices using laser processing. The methods presented provide fewer defects such as cracking or chipping of the substrates while minimizing the width of the kerf and maintaining system throughput.Type: GrantFiled: March 27, 2009Date of Patent: December 17, 2013Assignee: Electro Scientific Industries, Inc.Inventors: Peter Pirogovsky, Jeffery A. Albelo, James O'Brien, Yasu Osako
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Publication number: 20130327389Abstract: A method comprising providing a layer structure for a photovoltaic device, the layer structure comprising an electrode, a light absorber comprising a layer of chalcopyrite-type semiconductor material, such as copper indium gallium diselenide, disposed on the electrode and a transparent electrode disposed on the light absorber. The method also comprises delivering a spatially-shaped picosecond pulsed laser beam so as to remove material from a region of the transparent electrode so as to expose at least a portion of the light absorber.Type: ApplicationFiled: September 6, 2011Publication date: December 12, 2013Applicant: FIANIUM LTD.Inventors: Brian W. Baird, Timothy D. Gerke
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Patent number: 8603852Abstract: Disclosed herein is a method of manufacturing a solid state imaging device, including the steps of: forming a light receiving portion in a light receiving area of a semiconductor substrate; forming a pad portion in a pad area of the semiconductor substrate; forming a microlens material layer over the light receiving portion and the pad portion; providing the microlens material layer with a microlens corresponding to the light receiving portion; forming a low-reflection material layer on the microlens material layer; etching the microlens material layer and the low-reflection material layer over the pad portion to form an opening; and imparting hydrophilicity to a surface of the low-reflection material layer and an inside portion of the opening by a normal temperature oxygen radical treatment.Type: GrantFiled: June 2, 2010Date of Patent: December 10, 2013Assignee: Sony CorporationInventors: Yoshinori Toumiya, Ina Hori, Tadayuki Dofuku, Hitomi Kamiya, Atsushi Yamamoto, Taichi Natori
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Publication number: 20130316488Abstract: A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.Type: ApplicationFiled: May 26, 2012Publication date: November 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoartabari, Paul A. Lauro, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
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Patent number: 8580600Abstract: An image capturing system includes an optical component, a sensor below and connected to the optical component for capturing radiation, and a chip below the sensor for processing and/or storing and/or transmitting information captured by the sensor. The sensor and the Chip are directly connected to each other. The disclosure further relates to a production method for an image capturing system.Type: GrantFiled: November 12, 2008Date of Patent: November 12, 2013Assignee: Continental Automotive GmbHInventor: Thorsten Koehler
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Publication number: 20130288419Abstract: A semiconductor device includes a substrate, a region including a semiconductor element on the substrate, and at least one guard ring structure provided around the region. The guard ring structure includes a guard ring and at least one portion comprised of the substrate.Type: ApplicationFiled: June 28, 2013Publication date: October 31, 2013Inventors: Kentaro Akiyama, Masaaki Takizawa
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Publication number: 20130288418Abstract: A method is presented for fabrication of a three-dimensional thin-film solar cell semiconductor substrate from a template. A semiconductor template having three-dimensional surface features comprising a top surfaces substantially aligned along a (100) crystallographic plane of semiconductor template and a plurality of inverted pyramidal cavities defined by sidewalls substantially aligned along a (111) crystallographic plane is formed according to an anisotropic etching process. A dose of relatively of high energy light-mass species is implanted in the template at a uniform depth and parallel to the top surfaces and said sidewalls defining the inverted pyramidal cavities of the template. The semiconductor template is annealed to convert the dose of relatively of high energy light-mass species to a mechanically-weak-thin layer. The semiconductor template is cleaved along the mechanically-weak-thin layer to release a three-dimensional thin-film semiconductor substrate from the semiconductor template.Type: ApplicationFiled: October 15, 2012Publication date: October 31, 2013Applicant: SOLEXEL, INC.Inventors: David Xuan-Qi Wang, Mehrdad M. Moslehi
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Publication number: 20130285067Abstract: The invention relates to a method for fabricating a structure including a semiconductor material comprising: a) implanting one or more ion species to form a weakened region delimiting at least one seed layer in a substrate of semiconductor material, b) forming, before or after step a), at least one metallic layer on the substrate in semiconductor material, c) assembling the at least one metallic layer with a transfer substrate, then fracturing the implanted substrate at the weakened region, d) forming at least one layer in semiconductor material on the at least one seed layer, for example, by epitaxy.Type: ApplicationFiled: November 16, 2011Publication date: October 31, 2013Inventors: Jean-Marc Bethoux, Pascal Guenard
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Publication number: 20130285189Abstract: In a semiconductor device including unit cells which are aligned in one direction, wirings disposed along end portions in the one direction have high Young's moduli.Type: ApplicationFiled: March 14, 2013Publication date: October 31, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Masanori Ogura, Hideo Kobayashi, Tetsunobu Kochi, Masashi Kitani
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Patent number: 8569086Abstract: A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.Type: GrantFiled: August 24, 2011Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Cheng Lin, Chih-Wei Wu, Szu Wei Lu, Shin-Puu Jeng, Chen-Hua Yu
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Patent number: 8569097Abstract: Solar cell structures include stacked layers in reverse order on a germanium substrate wherein a n++ (In)GaAs buffer layer plays dual roles as buffer and contact layers in the inverted structures. The absorbing layers employed in such exemplary structures are III-V layers such as (In)GaAs. Controlled spalling may be employed as part of the fabrication process for the solar cell structures, which may be single or multi-junction. The requirement for etching a buffer layer is eliminated, thereby facilitating the manufacturing process of devices using the disclosed structures.Type: GrantFiled: July 6, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Cheng-Wei Cheng, Bahman Hekmatshoartabari, Ning Li, Devendra K. Sadana, Davood Shahrjerdi
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Publication number: 20130277785Abstract: Methods for glass removal while forming CMOS image sensors. A method for forming a device is provided that includes forming a plurality of pixel arrays on a device wafer; bonding a carrier wafer to a first side of the device wafer; bonding a substrate over a second side of the device wafer; thinning the carrier wafer; forming electrical connections to the first side of the device wafer; subsequently de-bonding the substrate from the second side of the device wafer; and subsequently singulating individuals ones of the plurality of pixel arrays from the device wafer. An apparatus is disclosed.Type: ApplicationFiled: December 13, 2012Publication date: October 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
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Publication number: 20130276885Abstract: Separation layers, usable in devices for converting radiation energy to electrical energy, allow at least some of the components of the devices to be separated from one another for disposal thereof. A separation layer may be interposed between and bonded to adjoining layers, and when acted upon by application of an external source, may be degraded to release the layers from one another. Once released, the layers may be disposed of more efficiently and economically, including proper disposal of hazardous waste, and recycling of materials which may be re-usable.Type: ApplicationFiled: April 23, 2012Publication date: October 24, 2013Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventors: Sung-Wei Chen, Christopher J. Rothfuss
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Patent number: 8563351Abstract: A photovoltaic device manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell using nanoimprint technology to define individual cell units of the photovoltaic device. The methods can include providing a substrate; forming a first conductive layer over the substrate; forming first grooves in the first conductive layer using a nanoimprint and etching process; forming an absorption layer over the first conductive layer, the absorption layer filling in the first grooves; forming second grooves in the absorption layer using a nanoimprint process; forming a second conductive layer over the absorption layer, the second conductive layer filling in the second grooves; and forming third grooves in the second conductive layer and the absorption layer, thereby defining a photovoltaic cell unit.Type: GrantFiled: June 25, 2010Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chiang Tu, Chun-Lang Chen
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Patent number: 8557637Abstract: The disclosure provides a method for fabricating the flexible electronic devices, including: providing a first rigid carrier substrate and a second rigid carrier substrate, wherein at least one flexible electronic device is formed between the first rigid carrier substrate and the second rigid carrier substrate, and a plurality of first de-bonding areas, a first flexible substrate, the flexible electronic device, a second flexible substrate, a plurality of second de-bonding areas and the second rigid carrier substrate are formed on the first rigid carrier substrate; performing a first cutting step to cut through the first de-bonding areas; separating the first rigid carrier substrate from the first de-bonding areas; removing the first rigid carrier substrate from the first de-bonding areas; and performing a second cutting step to cut through the second de-bonding areas; separating and removing the second rigid carrier substrate from the second de-bonding areas.Type: GrantFiled: June 21, 2012Date of Patent: October 15, 2013Assignee: Industrial Technology Research InstituteInventors: Kuang-Jung Chen, Isaac Wing-Tak Chan
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Publication number: 20130267057Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.Type: ApplicationFiled: June 4, 2013Publication date: October 10, 2013Inventors: Hyung-Sun Jang, Woon-Seong Kwon, Tae-Je Cho, Un-Byoung Kang, Jung-Hwan Kim
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Publication number: 20130264669Abstract: A method of making a semiconductor radiation detector wherein the metal layers which serve as the cathode and anode electrodes are recessed from the designated prospective dice lines which define the total upper and lower surface areas for each detector such that the dicing blade will not directly engage the metal during dicing and therefore prevent metal from intruding upon (smearing) the vertical side walls of the detector substrate.Type: ApplicationFiled: April 10, 2012Publication date: October 10, 2013Applicant: Endicott Interconnect Technologies, Inc.Inventors: Handong Li, Michael Prokesch, John Francis Eger
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Patent number: 8554355Abstract: A computer obtains user input from an input to control a cutter and a conveyor to cut a substrate. The control module of the computer calculates a total number of cuts of the substrate and a distance that the substrate moves before each cut of the substrate according to user input. A conveyer control module of the computer controls the conveyer to move the substrate, where a reminder signal is sent out after the substrate has moved the distance. A cutter control module of the computer controls the cutter to cut the substrate.Type: GrantFiled: October 28, 2010Date of Patent: October 8, 2013Assignees: Hong Heng Sheng Electronical Technology (HuaiAn) Co., Ltd, Zhen Ding Technology Co., Ltd.Inventor: Xiao-Bin Wu
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Publication number: 20130249034Abstract: The invention relates to an optical device produced by cutting a wafer-scale package comprising at least one optical module formed from a substrate (1) pierced with a plurality of through-holes (2) and optical elements disposed in the holes. According to the invention, at least one of the holes receives two lenses (3, 4) made from at least one polymer material transparent in the 400 nm-700 nm range, each of the lenses being defined by an external diopter and an internal diopter. The invention is characterised in that a space is formed between the internal diopters of two lenses and in that the substrate contains no polymer material between two adjacent through-holes.Type: ApplicationFiled: July 26, 2011Publication date: September 26, 2013Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventor: Luc Andre
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Publication number: 20130243021Abstract: A method of fabricating epitaxial structures including applying an etch stop to one side of a substrate and then growing at least one epitaxial layer on a first side of said substrate, flipping the substrate, growing a second etch stop and at least one epitaxial layer on a second side of the substrate, applying a carrier medium to the ultimate epitaxial layer on each side, dividing the substrate into two parts generally along an epitaxial plane to create separate epitaxial structures, removing any residual substrate and removing the etch stop.Type: ApplicationFiled: May 10, 2013Publication date: September 19, 2013Applicant: MASIMO SEMICONDUCTOR, INC.Inventor: Brad M. Siskavich
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Patent number: 8530263Abstract: A method of fabricating a solar cell includes forming a front contact layer over a substrate, and the front contact layer is optically transparent at specified wavelengths and electrically conductive. A first scribed area is scribed through the front contact layer to expose a portion of the substrate. A buffer layer doped with an n-type dopant is formed over the front contact layer and the first scribed area. An absorber layer doped with a p-type dopant is formed over the buffer layer. A back contact layer that is electrically conductive is formed over the absorber layer.Type: GrantFiled: August 10, 2011Date of Patent: September 10, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Chin Lee, Wen-Tsai Yen, Liang-Sheng Yu, Yung Sheng Chiu
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Patent number: 8524537Abstract: A semiconductor device has a build-up interconnect structure formed over an active surface of a semiconductor wafer containing a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the interconnect structure. Bumps are formed over the interconnect structure. A protective coating material is deposited over the insulating layer and saw street. A lamination tape is applied over the coating material. A portion of a back surface of the semiconductor wafer is removed. A mounting tape is applied over the back surface. The lamination tape is removed while leaving the coating material over the insulating layer and saw street. A first channel is formed through the saw street extending partially through the semiconductor wafer. The coating material is removed after forming the first channel. A second channel is formed through the saw street and the mounting tape is removed to singulate the semiconductor wafer.Type: GrantFiled: April 30, 2010Date of Patent: September 3, 2013Assignee: STATS ChipPAC, Ltd.Inventors: JaEun Yun, HunTeak Lee, SeungYong Chai, WonJun Ko
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Patent number: 8518774Abstract: Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays.Type: GrantFiled: March 21, 2008Date of Patent: August 27, 2013Assignee: Micron Technology, Inc.Inventor: Pierre Fazan
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Publication number: 20130215309Abstract: There is provided a solid-state imaging device including a pixel part obtained by arranging a plurality of pixels performing photoelectric conversion, and a pixel signal readout part including a logic part and reading out a pixel signal from the pixel part, wherein the pixel part and the logic part are formed as a layered structure, wherein the layered structure includes a low hardness layer at least lower in hardness than another layer out of a plurality of layers, and wherein a dividing part different from the other layer is formed in a side portion of the low hardness layer.Type: ApplicationFiled: January 31, 2013Publication date: August 22, 2013Applicant: SONY CORPORATIONInventor: Sony Corporation
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Publication number: 20130214375Abstract: An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape.Type: ApplicationFiled: February 16, 2012Publication date: August 22, 2013Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Tiejun Dai, Kuei Chen Liang
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Patent number: 8513045Abstract: A laser system with multiple laser pulses for removing material from a solar cell being fabricated. The laser system includes a single pulse laser source and a multi-pulse generator. The multi-pulse generator receives a single pulse laser beam from the single pulse laser source and converts the single pulse laser beam into a multi-pulse laser beam. A laser scanner scans the multi-pulse laser beam onto the solar cell to remove material from the solar cell.Type: GrantFiled: January 31, 2012Date of Patent: August 20, 2013Assignee: SunPower CorporationInventors: John Viatella, Gabriel Harley, Thomas Pass
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Patent number: 8513047Abstract: In accordance with the present invention, the dividing grooves 8 are formed so as not to be parallel to cleavage planes of the semiconductor substrate 1, and the semiconductor substrate 1 is bent along the dividing grooves 8, whereby the semiconductor substrate 1 is fractured along the dividing grooves 8.Type: GrantFiled: November 29, 2012Date of Patent: August 20, 2013Assignee: Sanyo Electric Co., Ltd.Inventors: Hiroyuki Kannou, Masaki Shima
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Patent number: 8507789Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a substrate of a first conductive type having at least one via hole; an emitter layer only on at least a portion of the via hole and at least one selected from a group consisting of an incident surface and side surfaces of the substrate, the emitter layer having a second conductive type opposite the first conductive type; at least one first electrode on the incident surface, the first electrode being electrically connected to the emitter layer; a second electrode connected to an opposite surface to the incident surface; and at least one first electrode current collector on the opposite surface, the at least one first electrode current collector being insulated from the second electrode and being electrically connected to the at least one first electrode through the via hole.Type: GrantFiled: May 18, 2012Date of Patent: August 13, 2013Assignee: LG Electronics Inc.Inventors: Jihoon Ko, Juwan Kang, Jonghwan Kim, Daehee Jang
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Patent number: 8507302Abstract: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.Type: GrantFiled: October 11, 2006Date of Patent: August 13, 2013Assignee: SemiLEDs Optoelectronics Co., Ltd.Inventors: Chen-Fu Chu, Hao-Chun Cheng, Trung Tri Doan, Feng-Hsu Fan
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Patent number: 8497189Abstract: A wafer has, on a front face thereof, a device region in which a device is formed in regions partitioned by a plurality of scheduled division lines. An outer peripheral region surrounds the device region. A reflecting film of a predetermined width is formed from the outermost periphery of the wafer on a rear face of the wafer corresponding to the outer peripheral region. The front face side of the wafer is held in a chuck table, and a focal point of a pulsed laser beam of a wavelength having permeability through the wafer is positioned in the inside of the wafer corresponding to the scheduled division lines. The pulsed laser beam is irradiated from the rear face side of the wafer to form modified layers individually serving as a start point of division along the scheduled division lines in the inside of the wafer.Type: GrantFiled: July 3, 2012Date of Patent: July 30, 2013Assignee: Disco CorporationInventor: Hitoshi Hoshino
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Patent number: 8497146Abstract: Vertical solid-state transducers (“SSTs”) having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the SST, a second semiconductor material at a second side of the SST opposite the first side, and an active region between the first and second semiconductor materials. The SST can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. A portion of the first contact can be covered by a dielectric material, and a portion can remain exposed through the dielectric material. A conductive carrier substrate can be disposed on the dielectric material. An isolating via can extend through the conductive carrier substrate to the dielectric material and surround the exposed portion of the first contact to define first and second terminals electrically accessible from the first side.Type: GrantFiled: August 25, 2011Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Vladimir Odnoblyudov, Martin F. Schubert
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Publication number: 20130181316Abstract: A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.Type: ApplicationFiled: January 16, 2013Publication date: July 18, 2013Applicant: OLYMPUS CORPORATIONInventor: OLYMPUS CORPORATION
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Patent number: 8481847Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a substrate of a first conductive type having at least one via hole; an emitter layer only on at least a portion of the via hole and at least one selected from a group consisting of an incident surface and side surfaces of the substrate, the emitter layer having a second conductive type opposite the first conductive type; at least one first electrode on the incident surface, the first electrode being electrically connected to the emitter layer; a second electrode connected to an opposite surface to the incident surface; and at least one first electrode current collector on the opposite surface, the at least one first electrode current collector being insulated from the second electrode and being electrically connected to the at least one first electrode through the via hole.Type: GrantFiled: May 18, 2012Date of Patent: July 9, 2013Assignee: LG Electronics Inc.Inventors: Jihoon Ko, Juwan Kang, Jonghwan Kim, Daehee Jang
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Patent number: 8481342Abstract: A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.Type: GrantFiled: March 24, 2010Date of Patent: July 9, 2013Assignee: Oki Data CorporationInventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Takahito Suzuki, Masataka Muto
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Publication number: 20130171758Abstract: A solar cell making method includes steps of making a round P-N junction preform by (a) stacking a P-type silicon layer and a N-type silicon layer on top of each other, and (b) forming a P-N junction near an interface between the P-type silicon layer and the N-type silicon layer, wherein the round P-N junction preform defines a first surface and a second surface; forming a first electrode preform on the first surface and forming a second electrode preform on the second surface, thereby forming a round solar cell perform; and forming a photoreceptive surface with the P-N junction exposed on the photoreceptive surface by cutting the round solar cell preform into a plurality of arc shaped solar cells, the photoreceptive surface being on a curved surface of the arc shaped solar cell and being configured to receive incident light beams.Type: ApplicationFiled: July 24, 2012Publication date: July 4, 2013Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITYInventors: YUAN-HAO JIN, QUN-QING LI, SHOU-SHAN FAN
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Patent number: 8476097Abstract: A method for manufacturing a thin-film solar cell includes providing a first conducting layer on a substrate that has an area at least 0.75 m2. The first conducting layer is located in a deposition portion of the area. An ultraviolet laser beam is applied through a lens to the first conducting layer. Portions of the first conducting layer are scribed form a trench through the layer. The lens focuses the beam and has a focal length at least 100 mm. The focused beam includes an effective portion effective for the scribing and an ineffective portion ineffective for the scribing. The substrate sags and the first conducting layer remains in the effective portion of the focused beam across the area during the step of applying. One or more active layers are provided on the first conducting layer. A second conducting layer is provided on the one or more active layers.Type: GrantFiled: August 28, 2008Date of Patent: July 2, 2013Assignee: Oerlikon Solar AG, TrubbachInventor: Jiri Springer
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Publication number: 20130157402Abstract: A method for manufacturing a solar cell system includes the following steps. First, a number of P-N junction cell preforms are provided. The number of the P-N junction cell preforms is M. The M P-N junction cell preforms is named from a first P-N junction cell preform to a Mth P-N junction cell preform. Second, the M P-N junction cell preforms are arranged along a straight line. Third, an inner electrode preform is formed between each two adjacent P-N junction cell preforms, wherein at least one inner electrode is a carbon nanotube array. Axial directions of the carbon nanotubes in the carbon nanotube array are parallel to the straight line.Type: ApplicationFiled: August 13, 2012Publication date: June 20, 2013Applicants: HON HAI PRECISION INDUSTRY CO., LTD., Tsinghua UniversityInventors: YUAN-HAO JIN, QUN-QING LI, SHOU-SHAN FAN
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Publication number: 20130146139Abstract: A reusable substrate and method for forming single crystal silicon solar cells are described. A method of forming a photovoltaic cell includes forming an intermediate layer on a monocrystalline silicon substrate, forming a monocrystalline silicon layer on the intermediate layer, and forming electrical features in the monocrystalline silicon layer. The method further includes forming openings in the monocrystalline silicon layer, and detaching the monocrystalline silicon layer from the substrate by selectively etching the intermediate layer through the openings.Type: ApplicationFiled: February 7, 2013Publication date: June 13, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
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Publication number: 20130139871Abstract: The solar cell module comprises: a string including solar cell elements, each including a first main surface being rectangular in shape and an electrode extending along a longitudinal direction on the first main surface, and an interconnection connecting the solar cell elements adjacent to each other along the longitudinal direction; a light-transmitting member located to cover the string; and a sealing material located between the string and the light-transmitting member. Each of solar cell elements includes a silicon substrate with the first and second main surface, and a first and second side surfaces each connecting the first and second main surface, the second side surface being located on the back side of the first side surface. The first and second side surfaces are arranged along the longitudinal direction, where silicon is exposed on the first side surface and the second side surface is covered with an insulating layer.Type: ApplicationFiled: September 29, 2011Publication date: June 6, 2013Applicant: KYOCERA CORPORATIONInventors: Hiroaki Hirata, Hiroshi Ueda, Kyouichi Ibaraki, Ken-ichiro Sumida, Noriyasu Kawakita, Takeshi Kyouda, Ryota Teshima
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Patent number: 8455332Abstract: A method of manufacturing a light-emitting device using laser scribing to improve overall light output is disclosed. Upon placing a semiconductor wafer having light emitting diode (“LED”) devices separated by streets on a wafer chuck, the process arranges a first surface of semiconductor wafer containing front sides of the LED devices facing up and a second surface of semiconductor wafer containing back sides of the LED devices facing toward the wafer chuck. After aligning a laser device over the first surface of the semiconductor wafer above a street, the process is configured to focus a high intensity portion of a laser beam generated by the laser device at a location in a substrate closer to the back sides of the LED devices.Type: GrantFiled: May 1, 2009Date of Patent: June 4, 2013Assignee: Bridgelux, Inc.Inventors: Norihito Hamaguchi, Ghulam Hasnain
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Patent number: 8455290Abstract: A method of fabricating epitaxial structures including applying an etch stop to one side of a substrate and then growing at least one epitaxial layer on a first side of said substrate, flipping the substrate, growing a second etch stop and at least one epitaxial layer on a second side of the substrate, applying a carrier medium to the ultimate epitaxial layer on each side, dividing the substrate into two parts generally along an epitaxial plane to create separate epitaxial structures, removing any residual substrate and removing the etch stop.Type: GrantFiled: September 4, 2010Date of Patent: June 4, 2013Assignee: Masimo Semiconductor, Inc.Inventor: Brad M. Siskavich
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Publication number: 20130130425Abstract: The invention relates to a method for producing a semiconductor, of the photovoltaic cell type, or similar electronic components. According to the invention, at least one silicon wafer is cut from the cross-section of a silicon rod and, after doping, a substrate is assembled on either side of the silicon wafer and the latter is cut into two parts through the thickness of the silicon, so as to form two semiconductor units each comprising a substrate and a thin silicon film.Type: ApplicationFiled: March 25, 2010Publication date: May 23, 2013Inventor: Jean-Pierre Medina
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Patent number: 8441105Abstract: A semiconductor device includes an element forming region including at least one semiconductor element formed on at least one compound semiconductor layer formed on a substrate and a trench formed between an outer edge of the semiconductor device and the element forming region. The trench spatially separates the compound semiconductor layer, and the trench is formed at least to reach the substrate.Type: GrantFiled: May 7, 2009Date of Patent: May 14, 2013Assignee: Furukawa Electric Co., Ltd.Inventors: Yoshihiro Sato, Takehiko Nomura
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Patent number: 8441088Abstract: A manufacturing method of a solid-state imaging device includes: preparing a photoelectric conversion device; forming an insulating layer on a surface of the photoelectric conversion device; forming a wire-grid polarizer on a support base; bonding a forming surface of the wire-grid polarizer on the support base to the insulating layer on the surface of the photoelectric conversion device and removing the support base from the wire-grid polarizer.Type: GrantFiled: December 16, 2011Date of Patent: May 14, 2013Assignee: Sony CorporationInventor: Yutaka Ooka
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Patent number: 8440487Abstract: The present disclosure provides methods for manufacturing a radio frequency (RF) powder including a plurality of RF particles, each of which includes a circuit element. A plurality of circuit elements, each corresponding to a different RF particle, may be formed on a first surface of a substrate. Grooves may be etched into the first surface of the substrate between the plurality of circuit elements. A protection film may be formed on each of the plurality of circuit elements and a portion of the substrate between a second, opposite surface of the substrate and bottoms of the grooves may be removed so that each of the plurality of circuit elements is associated with the remaining portion of the substrate.Type: GrantFiled: February 24, 2012Date of Patent: May 14, 2013Assignee: Philtech Inc.Inventor: Yuji Furumura
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Patent number: 8431428Abstract: An optical device wafer processing method including a laser processed groove forming step of applying a laser beam for performing ablation to the front side or back side of a substrate of an optical device wafer along streets, thereby forming a laser processed groove as a break start point on the front side or back side of the substrate along each street, and a wafer dividing step of applying an external force to the optical device wafer after performing the laser processed groove forming step to thereby break the wafer along each laser processed groove, thereby dividing the wafer into individual optical devices. In performing the laser processed groove forming step, an etching gas atmosphere for etching a modified substance produced by applying the laser beam to the substrate is generated, whereby an etching gas in the etching gas atmosphere is converted into a plasma by the application of the laser beam to thereby etch away the modified substance.Type: GrantFiled: April 19, 2011Date of Patent: April 30, 2013Assignee: Disco CorporationInventor: Kazuma Sekiya