Utilizing Chemical Vapor Deposition (i.e., Cvd) Patents (Class 438/680)
  • Patent number: 10651015
    Abstract: A substrate support includes an inner portion arranged to support a substrate, an edge ring surrounding the inner portion, and a controller that calculates a desired pocket depth of the substrate support. Pocket depth corresponds to a distance between an upper surface of the edge ring and an upper surface of the substrate. Based on the desired pocket depth, the controller selectively controls an actuator to raise and lower at least one of the edge ring and the inner portion to adjust the distance between the upper surface of the edge ring and the upper surface of the substrate.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: May 12, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Ivelin Angelov, Cristian Siladie, Dean Larson, Brian Severson
  • Patent number: 10626496
    Abstract: A film forming apparatus is provided for forming a film by revolving a substrate placed on a rotary table in a vacuum container, alternately supplying a precursor gas and a reaction gas that reacts with the precursor gas to generate a reaction product multiple times, and depositing the reaction product on the substrate. The film forming apparatus comprises a precursor gas supply region that supplies the precursor gas onto the substrate, one or more plasma generation regions that generate plasma at a position apart from the precursor gas supply region in a rotational direction of the rotary table, and a cleaning region that cleans the rotary table by supplying a cleaning gas onto the rotary table in a region apart from the plasma generation regions and the precursor gas supply region in the rotational direction when a film forming process is not performed on the substrate.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: April 21, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takayuki Karakawa, Jun Ogawa, Noriaki Fukiage, Yasuo Kobayashi
  • Patent number: 10615169
    Abstract: Methods and apparatuses for selectively depositing silicon nitride (SiN) via high-density plasma chemical vapor deposition (HDP CVD) to form a SiN pad on an exposed flat surface of a nitride layer in a 3D NAND staircase structure with alternating oxide and nitride layers are provided. In some embodiments, selective etching is performed to remove undesirable buildup of SiN on sidewalls of the oxide layers of the staircase structure. Nitride layers of the staircase structure are replaced with tungsten (W) to form tungsten wordlines, while the SiN pads are replaced with tungsten to from landing pads, which prevent punchthrough of the tungsten wordlines on the staircase structure by interconnects extending thereto.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: April 7, 2020
    Assignee: Lam Research Corporation
    Inventors: Bart J. van Schravendijk, Awnish Gupta, Patrick A. van Cleemput, Jason Daejin Park
  • Patent number: 10607817
    Abstract: Embodiments described herein generally related to a substrate processing apparatus, and more specifically to an improved showerhead assembly for a substrate processing apparatus. The showerhead assembly includes a gas distribution plate and one or more temperature detection assemblies. The gas distribution plate includes a body having a top surface and a bottom surface. The one or more temperature detection assemblies are interfaced with the top surface of the gas distribution plate such that a thermal bond is formed between the gas distribution plate and each of the one or more temperature detection assemblies. Each temperature detection assembly includes a protruded feature and a temperature probe. The protruded feature is interfaced with the top surface of the gas distribution plate such that an axial load is placed on the gas distribution plate along an axis of the protruded feature. The temperature probe is positioned in a body of the protruded feature.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: March 31, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Timothy Joseph Franklin, Steven E. Babayan, Philip Allan Kraus
  • Patent number: 10600900
    Abstract: In one embodiment, a semiconductor device is provided with a semiconductor layer made of a nitride semiconductor, a first gate electrode, a first structure body between the first gate electrode and the semiconductor layer, and a first insulating layer between the semiconductor layer and the first structure body. The first structure body has a first intermediate layer made of a conductor to suppress generation of charges at respective interfaces with adjacent layers, a first layer having dielectric property between the first gate electrode and the first intermediate layer, and a second layer having dielectric property between the first gate electrode and the first layer, and has dipoles at an interface between the first layer and the second layer.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 24, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Yonehara, Tatsuo Shimizu, Hiroshi Ono, Daimotsu Kato
  • Patent number: 10590534
    Abstract: A film deposition method is provided for filling a recessed pattern formed in a surface of a substrate with a film. In the method, a halogen-containing gas is supplied to a top surface of a substrate and an upper portion of a recessed pattern, thereby forming an adsorption blocking group on the top surface of the substrate and the upper portion of the recessed pattern. A first reaction gas is supplied to a surface of the substrate including the top surface and the recessed pattern to cause the first reaction gas to adsorb on an area where the adsorption blocking group is not formed on. A second reaction gas reactable with the first reaction gas is supplied to the surface of the substrate to produce a reaction product of the first reaction gas adsorbed on the bottom portion of the recessed pattern and the second reaction gas.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: March 17, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Takeshi Kumagai
  • Patent number: 10580736
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
  • Patent number: 10546744
    Abstract: A process is provided for depositing a substantially amorphous titanium oxynitride thin film that can be used, for example, in integrated circuit fabrication, such as in forming spacers in a pitch multiplication process. The process comprises contacting the substrate with a titanium reactant and removing excess titanium reactant and reaction byproducts, if any. The substrate is then contacted with a second reactant which comprises reactive species generated by plasma, wherein one of the reactive species comprises nitrogen. The second reactant and reaction byproducts, if any, are removed. The contacting and removing steps are repeated until a titanium oxynitride thin film of desired thickness has been formed.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: January 28, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami J. Pore, Seiji Okura, Hidemi Suemori
  • Patent number: 10541309
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes first and second metal gates on a substrate with a gap therebetween. The first metal gate has a first sidewall, and the second metal gate has a second sidewall directly facing the first sidewall. A contact etch stop layer (CESL) is disposed within the gap and extends along the first and second sidewalls. The CESL has a first top portion adjacent to a top surface of the first metal gate and a second top portion adjacent to a top surface of the second metal gate. The first top portion and the second top portion have a trapezoid cross-sectional profile. A first sidewall spacer is disposed on the first sidewall and between the CESL and the first metal gate. A second sidewall spacer is disposed on the second sidewall and between the CESL and the second metal gate.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: January 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP
    Inventors: Yi-Fan Li, Kuo-Chin Hung, Wen-Yi Teng, Ti-Bin Chen
  • Patent number: 10529560
    Abstract: There is provided a technique that includes (a) pre-etching a surface of a substrate made of single crystal silicon by supplying a first etching gas to the substrate; (b) forming a silicon film on the substrate with the pre-etched surface, by supplying a first silicon-containing gas to the substrate; (c) etching a portion of the silicon film by supplying a second etching gas, which has a different molecular structure from a molecular structure of the first etching gas, to the substrate; and (d) forming an additional silicon film on the etched silicon film by supplying a second silicon-containing gas to the substrate.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: January 7, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Takahiro Miyakura, Atsushi Moriya, Naoharu Nakaiso, Kensuke Haga
  • Patent number: 10504717
    Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao, Melitta Manyin Hon, Hua Chung, Schubert S. Chu
  • Patent number: 10476000
    Abstract: A method of forming a target layer in semiconductor fabrication is disclosed that includes steps of forming a first layer by performing a first process at least one time and forming a second layer by performing a second process at least one time, wherein the first process may include supplying a first source gas, supplying a second source gas several times, and supplying an inert gas several times.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: November 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeonghee Park, Kyoung Sun Kim
  • Patent number: 10460928
    Abstract: A process is provided for depositing a substantially amorphous titanium oxynitride thin film that can be used, for example, in integrated circuit fabrication, such as in forming spacers in a pitch multiplication process. The process comprises contacting the substrate with a titanium reactant and removing excess titanium reactant and reaction byproducts, if any. The substrate is then contacted with a second reactant which comprises reactive species generated by plasma, wherein one of the reactive species comprises nitrogen. The second reactant and reaction byproducts, if any, are removed. The contacting and removing steps are repeated until a titanium oxynitride thin film of desired thickness has been formed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: October 29, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami J. Pore, Seiji Okura, Hidemi Suemori
  • Patent number: 10385448
    Abstract: A processing chamber is described having a gas evacuation flow path from the center to the edge of the chamber. Purge gas is introduced at an opening around a support shaft that supports a heater plate. A shaft wall around the opening directs the purge gas along the support shaft to an evacuation plenum. Gas flows from the evacuation plenum through an opening in a second plate near the shaft wall and along the chamber bottom to an opening coupled to a vacuum source. Purge gas is also directed to the slit valve.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: August 20, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Juan Carlos Rocha-Alvarez, Amit Kumar Bansal, Ganesh Balasubramanian, Jianhua Zhou, Ramprakash Sankarakrishnan
  • Patent number: 10388530
    Abstract: Provided is a technique of adjusting a work function. A method of manufacturing a semiconductor device includes: (a) forming a titanium nitride layer on a substrate by supplying a first source containing titanium and a second source containing nitrogen to the substrate; (b) forming a titanium aluminum carbonitride layer on the substrate by supplying the first source, the second source and a third source containing aluminum and carbon to the substrate; (c) forming a laminated film on the substrate by performing (a) and (b); and (d) adjusting ratios of titanium, nitrogen, aluminum and carbon in the laminated film based on how many times (a) and (b) are performed.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: August 20, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Arito Ogawa, Kazuhiro Harada, Yukinao Kaga, Hideharu Itatani, Hiroshi Ashihara
  • Patent number: 10355111
    Abstract: A method includes depositing an inhibitor layer on a first surface, depositing a film on a second surface by performing a first set of deposition cycles. Each deposition cycle includes adsorbing a first precursor over the second surface, performing a first purge process, adsorbing a second precursor over the second surface, and performing a second purge process. The method also includes performing a third purge process that is different from the first purge process or the second purge process.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi On Chui, Bo-Cyuan Lu
  • Patent number: 10269569
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
  • Patent number: 10236197
    Abstract: An apparatus and method for processing a substrate in a processing system containing a deposition chamber, a treatment chamber, and an isolation region, separating the deposition chamber from the treatment is described herein. The deposition chamber deposits a film on a substrate. The treatment chamber receives the substrate from the deposition chamber and alters the film deposited in the deposition chamber with a film property altering device. Processing systems and methods are provided in accordance with the above embodiment and other embodiments.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: March 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Karthik Janakiraman, Abhijit Basu Mallick, Hari K. Ponnekanti, Mandyam Sriram, Alexandros T. Demos, Mukund Srinivasan, Juan Carlos Rocha-Alvarez, Dale R. Dubois
  • Patent number: 10236190
    Abstract: Embodiments disclosed herein generally relate to methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a III-V epitaxial growth process or an etch clean process, and prior to additional processing. An oxygen containing gas is flowed to a substrate in a load lock chamber, and subsequently a non-reactive gas is flowed to the substrate in the load lock chamber. As such, hazardous gases and outgassing residuals are decreased and/or removed from the substrate such that further processing may be performed.
    Type: Grant
    Filed: May 6, 2017
    Date of Patent: March 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao
  • Patent number: 10131986
    Abstract: There is provided a method for forming a metal film on a target substrate having a complex-shaped portion and a flat portion, the target substrate being loaded into a chamber which is maintained under a depressurized atmosphere, by sequentially supplying a metal chloride gas as a raw material gas and a reduction gas for reducing a metal chloride into the chamber while purging the chamber in the course of sequentially supplying the metal chloride gas and the reduction gas, the method including: forming a first metal film by supplying the metal chloride gas at a relatively low flow rate; and forming a second metal film by supply the metal chloride gas at a relatively high flow rate.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: November 20, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kenji Suzuki, Takanobu Hotta, Koji Maekawa, Yasushi Aiba
  • Patent number: 10096463
    Abstract: A method of manufacturing a semiconductor device includes: forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: supplying a precursor from a first nozzle to a substrate and exhausting the precursor from an exhaust port; supplying a first reactant from a second nozzle to the substrate and exhausting the first reactant from the exhaust port; and supplying a second reactant from a third nozzle to the substrate and exhausting the second reactant from the exhaust port. A substrate in-plane film thickness distribution of the film formed on the substrate is controlled by controlling a balance between a flow rate of an inert gas supplied from the second nozzle, a flow rate of an inert gas supplied from the third nozzle, and a flow rate of an inert gas supplied from the first nozzle in supplying the precursor.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 9, 2018
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Yoshitomo Hashimoto, Tatsuru Matsuoka, Masaya Nagato, Ryota Horiike, Shintaro Kogura
  • Patent number: 9984870
    Abstract: A technique relates to in-situ cleaning of a high-mobility substrate. Alternating pulses of a metal precursor and exposure to a plasma of a gas or gas mixture are applied. The gas or gas mixture contains both nitrogen and hydrogen (e.g., NH3). A passivation layer is formed on the high-mobility substrate by alternating pulses of the metal precursor and exposure to the plasma of a gas, or gas mixture, containing both nitrogen and hydrogen.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 29, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ULVAC, INC.
    Inventors: Takashi Ando, Vijay Narayanan, Yohei Ogawa, John Rozen
  • Patent number: 9954135
    Abstract: A method for manufacturing solar cell includes the following. A solution containing aluminum elements is misted. The misted solution is sprayed onto the main surface of a p-type silicon substrate in the atmosphere, to thereby form an aluminum oxide film. Then, a solar cell is produced using the p-type silicon substrate including the aluminum oxide film formed thereon.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 24, 2018
    Assignees: Toshiba Mitsubishi-Electric Industrial Systems Corporation, Kyoto University, Kochi Prefectural Public University Corporation
    Inventors: Takahiro Hiramatsu, Hiroyuki Orita, Takahiro Shirahata, Toshiyuki Kawaharamura, Shizuo Fujita
  • Patent number: 9754816
    Abstract: The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: September 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Hayashi, Naoya Inoue, Kishou Kaneko
  • Patent number: 9640784
    Abstract: A deposition apparatus includes a substrate combining unit configured to dispose a substrate on a moving unit including a surface, a first blocking member combining unit configured to raise a first blocking member, a first deposition unit including one or more deposition assemblies configured to deposit a material on the substrate, a first blocking member separation unit configured to separate the first blocking member downward from the moving unit, and a first conveyer unit configured to convey the moving unit in a first direction, where the one or more deposition assemblies are spaced apart from the substrate by a predetermined distance so that the material is deposited on the substrate in the first deposition unit while the moving unit is conveyed in the first direction.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: May 2, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jin-Seok Son
  • Patent number: 9627184
    Abstract: A plasma processing apparatus includes a processing chamber, in which a wafer W is plasma-processed, and a CPU controlling an operation of each component. A processing gas is introduced into the processing chamber under a first condition defined by a flow rate and a molecular weight of the processing gas, specifically based on a magnitude of a product A1 (=Q1×m1) of the flow rate Q1 and the molecular weight m1 of the processing gas, and a surface of the wafer W is physically or chemically etched. And then, a pre-purge gas which may be identical to or different from the processing gas is introduced into the processing chamber through a shower head under a second condition derived from the first condition.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: April 18, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tsuyoshi Moriya, Hiroyuki Nakayama, Hiroshi Nagaike
  • Patent number: 9613818
    Abstract: Provided herein are methods of depositing bulk tungsten by sequential CVD pulses, such as by alternately pulsing tungsten hexafluoride and hydrogen gas in cycles of temporally separated pulses. Some methods include depositing a tungsten nucleation layer at low pressure followed by deposition of bulk tungsten by sequential CVD to form low stress tungsten films with low fluorine content. Methods described herein may also be performed in combination with non-sequential CVD deposition and fluorine-free tungsten deposition techniques.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: April 4, 2017
    Assignee: Lam Research Corporation
    Inventors: Xiaolan Ba, Raashina Humayun, Michal Danek, Lawrence Schloss
  • Patent number: 9589809
    Abstract: A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiH4 base W film on a surface of a substrate to preprocess the surface. The method includes depositing a B2H6 base W layer on the preprocessed surface. The SiH4 base W film may be several atom layers thick. The film and base W layer may be deposited in a single ALD process, include reactive gas soak, reactive gas introduction, and main deposition operations. Forming the film may include introducing SiH4 gas into a reactive cavity during the gas soak operation, and introducing SiH4 and WF6 gas into the cavity during the gas introduction operation. The SiH4 and WF6 gases may be alternately introduced, for a number of cycles depending on the thickness of the tungsten layer to be deposited.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: March 7, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiang Xu, Chao Zhao, Jun Luo, Guilei Wang, Tao Yang, Junfeng Li
  • Patent number: 9583245
    Abstract: A magnet plate assembly includes a plurality of magnetic substances having predetermined magnetic forces, a magnet supporter supporting at least a corresponding one of the plurality of magnetic substances, and a guide support supporting the magnet supporter and comprising at least one guide opening. The magnetic plate assembly further includes a coupler extending through the at least one guide opening and movable within the at least one guide opening, the coupler being connected to the magnet supporter; and a driver unit connected to the coupler and configured to move the corresponding one of the plurality of magnetic substances with respect to the guide support.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 28, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Minpyo Hong, Hongryul Kim
  • Patent number: 9543220
    Abstract: According to the present disclosure, it is possible to prevent particles from being generated and to improve substrate processing quality.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: January 10, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Takeo Sato
  • Patent number: 9530627
    Abstract: Embodiments described herein relate to a thermal chlorine gas cleaning process. In one embodiment, a method for cleaning N-Metal film deposition in a processing chamber includes positioning a dummy substrate on a substrate support. The processing chamber is heated to at least about 50 degrees Celsius. The method further includes flowing chlorine gas into the processing chamber and evacuating chlorine gas from the processing chamber. In another embodiment, a method for cleaning titanium aluminide film deposition in a processing chamber includes heating the processing chamber to a temperature between about 70 about degrees Celsius and about 100 degrees Celsius, wherein the processing chamber and the substrate support include one or more fluid channels configured to heat or cool the processing chamber and the substrate support.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: December 27, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Xinliang Lu, Kyoung-Ho Bu, Jing Zhou, Seshadri Ganguli, David Thompson
  • Patent number: 9508555
    Abstract: To improve quality or manufacturing throughput of a semiconductor device, a method includes supplying a source gas to a substrate in a process chamber; exhausting an inside of the process chamber; supplying a reaction gas to the substrate; and exhausting the inside of the process chamber, wherein the source gas and/or the reaction gas is supplied in temporally separated pulses in the supply of the source gas and/or in the supply of the reaction gas. Then, the source gas and/or the reaction gas is supplied in temporally separated pulses to form a film during a gas supply time determined by a concentration distribution of by-products formed on a surface of the substrate.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: November 29, 2016
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Yukinao Kaga, Arito Ogawa, Atsuro Seino, Atsuhiko Ashitani, Ryohei Maeno, Masanori Sakai
  • Patent number: 9481929
    Abstract: A vapor deposition apparatus for depositing thin films on a substrate includes a supply unit including a plurality of linear supply members configured to supply at least one gas; and a nozzle unit including a plurality of nozzle members connected to the plurality of supply members and configured to supply the at least one gas toward the substrate, wherein two adjacent nozzle members of the plurality of nozzle members are connected to at least one common supply member of the plurality of supply members.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: November 1, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Choel-Min Jang, Sung-Hun Key, In-Kyo Kim, Suk-Won Jung, Myung-Soo Huh
  • Patent number: 9466477
    Abstract: There are provided a method of manufacturing a semiconductor device, a substrate processing apparatus, and a semiconductor device. The method allows rapid formation of a conductive film, which has a low concentration of impurities permeated from a source owing to its dense structure, and a low resistivity. The method is performed by simultaneously supplying two or more kinds of sources into a processing chamber to form a film on a substrate placed in the processing chamber. The method comprises: performing a first source supply process by supplying at least one kind of source into the processing chamber at a first supply flow rate; and performing a second source supply process by supplying the at least one kind of source into the processing chamber at a second supply flow rate different from the first supply flow rate.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: October 11, 2016
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Tatsuyuki Saito, Masanori Sakai, Yukinao Kaga, Takashi Yokogawa
  • Patent number: 9466524
    Abstract: Methods for depositing metal layers, and more specifically TaN layers, using CVD and ALD techniques are provided. In one or more embodiments, the method includes sequentially exposing a substrate to a metal precursor, or more specifically a tantalum precursor, followed by a high frequency plasma.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: October 11, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Paul F. Ma, Guojun Liu, Annamalai Lakshmanan, Dien-Yeh Wu, Anantha K. Subramani
  • Patent number: 9466478
    Abstract: A method of forming an oxide film on an object to be processed, includes: supplying a film-forming raw material gas into a processing chamber; performing at least one of exhausting the processing chamber and supplying a purge gas into the processing chamber to remove gas remaining in the processing chamber; supplying an oxidant gas into the processing chamber; and performing at least one of exhausting the processing chamber and supplying the purge gas into the processing chamber to remove gas remaining in the processing chamber, wherein supplying an oxidant gas includes: supplying a first oxidant gas into the processing chamber at a first concentration; and supplying a second oxidant gas into the processing chamber at a second concentration higher than the first concentration.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 11, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Shimizu, Tsuyoshi Tsunatori, Shigeru Nakajima
  • Patent number: 9449843
    Abstract: Methods of selectively etching metals and metal nitrides from the surface of a substrate are described. The etch selectively removes metals and metal nitrides relative to silicon-containing layers such as silicon, polysilicon, silicon oxide, silicon germanium, silicon carbide, silicon carbon nitride and/or silicon nitride. The etch removes material in a conformal manner by including an oxidation operation which creates a thin uniform metal oxide. The thin uniform metal oxide is then removed by exposing the metal oxide to a metal-halogen precursor in a substrate processing region. The metal oxide may be removed to completion and the etch may stop once the uniform metal oxide layer is removed. Etches described herein may be used to uniformly trim back material on high aspect ratio features which ordinarily show higher etch rates near the opening of a gap compared to deep within the gap.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: September 20, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Mikhail Korolik, Nitin K. Ingle, David Thompson, Jeffrey W. Anthis, David Knapp, Benjamin Schmiege
  • Patent number: 9418855
    Abstract: A halogen element-containing metal material and a nitrogen-containing material are alternately supplied to a process chamber with a flow rate of an inert gas supplied to the process chamber together with the nitrogen-containing material during the supplying of the nitrogen-containing material to the process chamber being more increased than a flow rate of the inert gas supplied to the process chamber together with the metal material during the supplying of the metal material to the process chamber.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 16, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kimihiko Nakatani, Kazuhiro Harada, Hiroshi Ashihara
  • Patent number: 9349586
    Abstract: A thin film having excellent etching resistance and a low dielectric constant is described. A method of manufacturing a semiconductor device includes forming a thin film on a substrate, removing first impurities containing H2O and Cl from the thin film by heating the thin film at a first temperature higher than a temperature of the substrate in the forming of the thin film, and removing second impurities containing a hydrocarbon compound (CxHy-based impurities) from the thin film in which heat treatment is performed at the first temperature by heating the thin film at a second temperature equal to or higher than the first temperature.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: May 24, 2016
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Satoshi Shimamoto, Takaaki Noda, Takeo Hanashima, Yoshiro Hirose, Hiroshi Ashihara, Tsukasa Kamakura, Shingo Nohara
  • Patent number: 9341923
    Abstract: A composite plastic member includes a first stacked body comprised of a plurality of chromium layers stacked on a plastic substrate; and a second stacked body comprised of a plurality of chromium nitride layers stacked on the first stacked body. Each of the first and second stacked bodies is formed such that a lower-hardness layer having a lower hardness than upper and lower layers which contact with and sandwich the lower-hardness layer therebetween and a higher-hardness layer having a higher hardness than upper and lower layers which contact with and sandwich the higher-hardness layer therebetween are alternately stacked in a stacking direction; and a thickness of a higher-hardness chromium nitride layer is not more than 40% of a thickness of a lower-hardness chromium nitride layer in the second stacked body. The composite plastic member has high wear resistance and satisfactory sliding performance, and the conductivity and excellent outer appearance.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: May 17, 2016
    Assignee: NIKON CORPORATION
    Inventors: Yusuke Taki, Yohei Takahashi, Yujiro Urakawa
  • Patent number: 9340880
    Abstract: Semiconductor fabrication processes are described. An embodiment of the semiconductor fabrication process includes providing a layer formed by decomposition of dimethylsilane through chemical vapor deposition, the layer being applied by a fluid material, and then positioning the layer in a system for producing a semiconductor product. Additionally or alternatively, the semiconductor product is produced and/or the layer is on a substrate.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 17, 2016
    Assignee: Silcotek Corp.
    Inventor: James B. Mattzela
  • Patent number: 9330939
    Abstract: Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a contact metal layer on a substrate and annealing the contact metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the contact metal layer on the substrate, exposing the portion of the contact metal layer to a plasma treatment process, and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the contact metal layer to a plasma treatment process until a predetermined thickness of the contact metal layer is achieved.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 3, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bhushan N. Zope, Avgerinos V. Gelatos, Bo Zheng, Yu Lei, Xinyu Fu, Srinivas Gandikota, Sang-Ho Yu, Mathew Abraham
  • Patent number: 9331218
    Abstract: Provided are a solar cell module and a method of manufacturing the same. The solar cell module including: a substrate; a bottom electrode layer discontinuously formed on the substrate; a light absorbing layer formed on the bottom electrode layer and including a first trench that exposes the bottom electrode layer; and a transparent electrode layer extending from the top of the light absorbing layer to the bottom electrode layer at the bottom of the first trench, and including a first oxide layer, a metal layer, and a second oxide layer, all of which are staked on the light absorbing layer and the bottom electrode layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 3, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Woo-Seok Cheong, Rae-Man Park
  • Patent number: 9297072
    Abstract: A film deposition apparatus includes a rotary table having a substrate placement area to support a substrate, a vacuum container including a container and a top panel, an open-and-close mechanism configured to open and close the top panel, reactant gas nozzles disposed through and supported by an outer wall of the container to be situated at different angular positions with respect to a rotation center of the rotary table to face areas in which the substrate placement area passes, the reactant gas nozzles having gas discharge ports arranged in radial directions to supply respective reactant gases to the wafer thereby to form respective process areas, a discharge gas supply unit situated at an angular position between the process areas to supply purge gas to form an isolation area that isolates atmospheres of the process areas from each other, and an exhaustion unit configured to exhaust atmosphere inside the vacuum container.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: March 29, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Manabu Honma
  • Patent number: 9257278
    Abstract: When forming a TiN film to be formed as a metallic hard mask for etching a film formed on a substrate to be processed, a first step and a second step are repeated a plurality of times to form a TiN film having reduced film stress. In the first step (step 1), the substrate to be processed is conveyed into a processing chamber, TiCl4 gas and a nitriding gas are fed into the processing chamber, the interior of which being kept in a depressurized state during this time, and a plasma from the gases is generated to form a TiN unit film. In the second step (step 2), a nitriding gas is fed into the processing container, a plasma of the gas is generated, and the TiN unit film is subjected to plasma nitriding.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: February 9, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hideaki Yamasaki, Takeshi Yamamoto
  • Patent number: 9245780
    Abstract: A vacuum processing apparatus includes a row of containers of vacuum transfer chambers connected to each other behind a lock chamber, a wafer being transferred through depressurized inside of the row of the containers of the vacuum transfer containers, an intermediate chamber disposed between the containers of the vacuum transfer chambers, a plurality of processing units including processing containers respectively connected to left or right side walls of the containers of the vacuum transfer chambers and the wafer is processed therein, and a bypass chamber which constitutes a bypass path connecting the processing units, where only either the wafer which is being transferred from the lock chamber toward one of the processing units or the wafer which was processed in one of the processing units and is being transferred toward the lock chamber is transferred through the containers of the vacuum transfer chambers.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: January 26, 2016
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Takahiro Shimomura, Yoshifumi Ogawa, Susumu Tauchi
  • Patent number: 9200364
    Abstract: A film forming apparatus for forming a film on an object includes: a processing container; gas supply means, having gas jet ports, respectively; a holding means for holding the object; a drive mechanism for moving the holding means relative to the gas jet ports; and a control means which, when repeating P times a cycle, consisting of a supply period for supplying a gas and a supply stop period during which the supply of the gas is stopped, performs control so that as viewed from the center of the object, a gas supply starting position is sequentially shifted in the circumferential direction of the object for every cycle in such a manner that the entire circumference of the object to be processed is divided into K segments (K=P), K being an arbitrary division number, and the gas supply starting position is shifted by one segment for every cycle.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: December 1, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Shozo Ito
  • Patent number: 9153430
    Abstract: Provided is a substrate processing apparatus. The substrate processing apparatus includes: a process chamber configured to accommodate a substrate; a substrate holding member configured to hold the substrate in the process chamber; a first gas supply system including a first gas supply hole for supplying a first process gas into the process chamber; a second gas supply system including a second gas supply hole for supplying a second process gas into the process chamber; and a catalyst supply system including a catalyst supply hole for supplying a catalyst into the process chamber, wherein an angle between a first imaginary line connecting a center of the substrate holding member and the first gas supply hole and a second imaginary line connecting the center of the substrate holding member and the catalyst supply hole ranges from 63.5 degrees to 296.5 degrees.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 6, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takaaki Noda, Jie Wang
  • Patent number: 9123510
    Abstract: A method for controlling in-plane uniformity of a substrate processed by plasma-assisted process in a reactor, includes: supplying a principal gas to a reaction space, and discharging radially the principal gas from the reaction space through an annular duct; and supplying an secondary gas to the reaction space from an area in close proximity to an outer periphery of a susceptor, outside an outer circumference of the substrate as viewed from above, so as to flow at least partially in an inward direction passing the outer circumference of the substrate, reversing the direction of the secondary gas to flow toward the annular duct in a vicinity of the outer circumference of the substrate, and discharging radially the secondary gas together with the principal gas from the reaction space through the annular duct.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 1, 2015
    Assignee: ASM IP HOLDING, B.V.
    Inventors: Ryu Nakano, Naoki Inoue
  • Patent number: 9117658
    Abstract: There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: August 25, 2015
    Assignees: SUMITOMO CHEMICAL COMPANY, LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Mitsuru Takenaka, Shinichi Takagi, Jaehoon Han, Tomoyuki Takada, Takenori Osada, Masahiko Hata