Utilizing Chemical Vapor Deposition (i.e., Cvd) Patents (Class 438/680)
  • Patent number: 12125711
    Abstract: Provided herein are methods and systems for reducing roughness of EUV resists and improving etched features. The methods may involve depositing a thin film on a patterned EUV resist having a stress level that is less compressive than a stress level of the patterned EUV resist. The resulting composite stress may reduce buckling and/or bulging of the patterned EUV resist.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: October 22, 2024
    Assignee: Lam Research Corporation
    Inventors: Xiang Zhou, Teng Hooi Goh, Yoshie Kimura
  • Patent number: 12062545
    Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: August 13, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Ilanit Fisher, Chi-Chou Lin, Kedi Wu, Wen Ting Chen, Shih Chung Chen, Srinivas Gandikota, Mandyam Sriram, Chenfei Shen, Naomi Yoshida, He Ren
  • Patent number: 11974468
    Abstract: A display device includes: a substrate; a TFT layer provided on the substrate; a light-emitting element layer provided on the TFT layer and including a plurality of light-emitting elements; and at least one thermal insulation layer, the thermal insulation layer containing: a cellulosic resin; and a metal oxide or a metal carbonyl compound.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: April 30, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Masanobu Mizusaki
  • Patent number: 11952661
    Abstract: A deposition method includes: forming an adsorption inhibiting region on an adsorption site formed on a substrate, by causing the adsorption site to adsorb adsorption inhibiting radicals by a predetermined amount; causing an area on the adsorption site, on which the adsorption inhibiting region is not formed, to adsorb a raw material gas; and depositing a film of a reaction product on the adsorption site by causing the raw material gas adsorbed on the adsorption site to react with a reactant gas activated by a plasma.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 9, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Kazumi Kubo, Yutaka Takahashi
  • Patent number: 11932935
    Abstract: Provided is a process for the rapid deposition of highly conformal molybdenum- or tungsten-containing films onto microelectronic device substrates under vapor deposition conditions. In the practice of the invention, a first nucleation step is conducted, while utilizing a generally lower concentration of metal precursor than would ordinarily be utilized in the reaction zone. This utilization of lower metal precursor concentrations can be achieved by way of regulating the temperature of the ampoule (housing the precursor), the concentration of the precursor, pressure in the reaction zone, and the duration of the pulse. In this fashion, a generally lower concentration is utilized to form a nucleation layer of greater than or equal to about 3 ?, or up to about 9, 15, or 25 ?, at which time, the conditions for introducing the precursor are advantageously changed and the concentration of the precursor in the reaction zone is increased for the purpose of bulk deposition.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 19, 2024
    Assignee: ENTEGRIS, INC.
    Inventor: Robert L. Wright, Jr.
  • Patent number: 11643721
    Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 9, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Feng Q. Liu, Hua Chung, Schubert Chu, Mei Chang, Jeffrey W. Anthis, David Thompson
  • Patent number: 11600503
    Abstract: A semiconductor processing system comprises a first, a second, and a third process module assembly. The third process module assembly is between the first and the second process module assemblies, and includes an opening for providing substrates to be processed in the various process module assemblies. The process modules are arranged laterally relative to the opening. The first and second process module assemblies each include an associated transfer chamber, an associated substrate transfer device, and a plurality of associated process modules attached the associated transfer chamber. The third process module assembly may include an associated transfer chamber, an associated substrate transfer device, and a single associated process module attached to the associated transfer chamber.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: March 7, 2023
    Assignee: ASM IP HOLDING B.V.
    Inventor: Yukihiro Mori
  • Patent number: 11525184
    Abstract: Methods are provided for dual selective deposition of a first material on a first surface of a substrate and a second material on a second, different surface of the same substrate. The selectively deposited materials may be, for example, metal, metal oxide, or dielectric materials.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 13, 2022
    Assignee: ASM IP HOLDING B.V.
    Inventors: Suvi P. Haukka, Raija H. Matero, Eva Tois, Antti Niskanen, Marko Tuominen, Hannu Huotari, Viljami J. Pore
  • Patent number: 11511303
    Abstract: The invention relates to a system and to a method for coating workpieces using a coating device, which is designed to apply a metal coating to a surface of the workpiece. According to the invention, it is provided that a plurality of coating devices, which are designed as identical coating modules, are provided and are arranged in a module group, that an input measuring station is assigned to the module group, by means of which station a surface of the face of the workpiece to be coated can be detected, that a conveying apparatus is provided, by means of which a workpiece can be supplied to one of the coating modules from the input measuring station, and that an output measuring station is assigned to the module group, by means of which station a surface of the coated face of the workpiece can be detected.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: November 29, 2022
    Assignee: STURM MASCHINEN-& ANLAGENBAU GMBH
    Inventors: Carlos Martin, Roland Baier
  • Patent number: 11502171
    Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. De Souza, Keith E. Fogel, JeeHwan Kim, Devendra K. Sadana
  • Patent number: 11469098
    Abstract: A method for depositing an oxide film on a substrate by a cyclical deposition is disclosed. The method may include: depositing a metal oxide film over the substrate utilizing at least one deposition cycle of a first sub-cycle of the cyclical deposition process; and depositing a silicon oxide film directly on the metal oxide film utilizing at least one deposition cycle of a second sub-cycle of the cyclical deposition process. Semiconductor device structures including an oxide film deposited by the methods of the disclosure are also disclosed.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: October 11, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Fu Tang, Delphine Longrie, Peng-Fu Hsu
  • Patent number: 11447864
    Abstract: There is provided a method and apparatus to deposit a molybdenum comprising layer on a substrate by supplying a precursor comprising molybdenum(VI) dichloride dioxide and a first reactant comprising boron and hydrogen to the substrate in a reaction chamber to react and form the molybdenum layer. The first reactant comprising boron and hydrogen may be diborane.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: September 20, 2022
    Assignee: ASM IP Holding B.V.
    Inventor: Jeroen Fluit
  • Patent number: 11430679
    Abstract: A semiconductor manufacturing apparatus including at least one load module including a load port on which a substrate container is located, a plurality of substrates being mountable on the substrate container; at least one loadlock module including a loadlock chamber directly connected to the substrate container, the loadlock chamber interchangeably having atmospheric pressure and vacuum pressure, a first transfer robot within the loadlock chamber, and a substrate stage within the loadlock chamber, the plurality of substrates being mountable on the substrate stage; a transfer module including a transfer chamber connected to the loadlock chamber, a second transfer robot within the transfer chamber, and a substrate aligner within the transfer chamber; and at least one process module including at least one process chamber connected to the transfer module.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 30, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwangnam Kim, Nohsung Kwak, Sungyeon Kim, Hyungjun Kim, Haejoong Park, Jongwoo Sun, Sangrok Oh, Ilyoung Han, Jungpyo Hong
  • Patent number: 11410880
    Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 11380486
    Abstract: A vertical capacitor includes a stack of layers conformally covering walls of a first material. The walls extend from a substrate made of a second material different from the first material.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: July 5, 2022
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Mohamed Boufnichel
  • Patent number: 11315793
    Abstract: An etching method is performed in a state where a substrate is placed on a substrate support provided in a chamber of a plasma processing apparatus. In the etching method, radio-frequency power is supplied to generate plasma from a gas in the chamber. Subsequently, a negative DC voltage is applied to a lower electrode of the substrate support during the supplying of the radio-frequency power to etch the substrate with positive ions from plasma. Subsequently, the applying of the negative DC voltage to the lower electrode and the supplying of the radio-frequency power are stopped to generate negative ions. Subsequently, a positive DC voltage is applied to the lower electrode in a state where the supply of the radio-frequency power is stopped to supply the negative ions to the substrate.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: April 26, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Gen Tamamushi, Kazuya Nagaseki
  • Patent number: 11315792
    Abstract: A plasma processing apparatus includes a plasma processing chamber processing a sample using plasma, a radio frequency power supply supplying radio frequency power for generating the plasma, a sample stage including an electrode electrostatically chucking the sample, mounting the sample thereon, a DC power supply applying DC voltage to the electrode, and a control device shifting the DC voltage previously set, in a negative direction by a first shift amount during discharge of the plasma, shifting the DC voltage having been shifted in the negative direction by the first shift amount, in a positive direction by a second shift amount after the discharge of the plasma. The first shift amount has a value changing potential over a surface of the sample to 0 V, upon shifting the DC voltage in the positive direction. The second shift amount has a value obtained based on a floating potential of the plasma.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 26, 2022
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Masaki Ishiguro, Masahiro Sumiya, Shigeru Shirayone, Kazuyuki Ikenaga, Tomoyuki Tamura
  • Patent number: 11248291
    Abstract: A method for deposition of a thin film onto a substrate is provided. The method includes providing a source precursor containing on or more of elements constituting the thin film, generating a transient species from the source precursor, and depositing a thin film onto the substrate from the transient species. The transient species being a reactive intermediate that has a limited lifetime in a condensed phase at or above room temperature.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: February 15, 2022
    Assignee: GELEST, INC.
    Inventors: Barry C. Arkles, Alain E. Kaloyeros
  • Patent number: 11242601
    Abstract: According to an embodiment of the present invention, a substrate processing apparatus includes: a chamber in which a process for a substrate is performed; a showerhead installed in the chamber to inject a reaction gas toward the substrate; and a susceptor installed below the showerhead to support the substrate. Here, the showerhead includes: a showerhead main body including an inner space to which the reaction gas is supplied from the outside and a plurality of injection holes configured to inject the reaction gas while communicating with the inner space; an inflow plate installed in the inner space to divide the inner space into an inflow space and a buffer space and including a plurality of inflow holes configured to allow the inflow space and the buffer space to communicate with each other; and a plurality of adjustment plates installed on the inflow holes in a movable manner, respectively, and configured to restrict movement of the reaction gas from the inflow space to the buffer space.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: February 8, 2022
    Assignee: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Sung Tae Je, Chan Yong Park, Jae Ho Lee, Gil Sun Jang, Chang Hoon Yun, Han June Lim, Woo Young Kang
  • Patent number: 11195712
    Abstract: A process is provided for depositing a substantially amorphous titanium oxynitride thin film that can be used, for example, in integrated circuit fabrication, such as in forming spacers in a pitch multiplication process. The process comprises contacting the substrate with a titanium reactant and removing excess titanium reactant and reaction byproducts, if any. The substrate is then contacted with a second reactant which comprises reactive species generated by plasma, wherein one of the reactive species comprises nitrogen. The second reactant and reaction byproducts, if any, are removed. The contacting and removing steps are repeated until a titanium oxynitride thin film of desired thickness has been formed.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: December 7, 2021
    Assignee: ASM IP HOLDING B.V.
    Inventors: Viljami J. Pore, Seiji Okura, Hidemi Suemori
  • Patent number: 11170835
    Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Durai Vishak Nirmal Ramaswamy, F. Daniel Gealy
  • Patent number: 10998207
    Abstract: Product recipes in which a treatment procedure and treatment conditions of heat treatment of product wafers are specified are created timely. Dummy recipes in which a treatment procedure and treatment conditions of heat treatment of dummy wafers are specified are also created. Each of the product recipes and a corresponding one of the dummy recipes are stored in association with each other. Dummy treatment of a dummy wafer starts when a controller receives an advance notice signal indicating that product wafers will arrive at a heat treatment apparatus. The dummy wafers are stored in a dummy carrier permanently installed on a load port exclusive to the dummy carrier. The dummy treatment is performed in accordance with a dummy recipe associated with a product recipe corresponding to the product wafers scheduled to arrive at the heat treatment apparatus.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 4, 2021
    Assignee: SCREEN Holdings Co., Ltd.
    Inventor: Shinichi Ikeda
  • Patent number: 10961624
    Abstract: A thin film deposition process is provided. The process includes, in a single cycle, providing a precursor in the vapor phase with or without a carrier gas to a reaction zone containing a substrate, such that a monolayer of the precursor is adsorbed to a surface of the substrate and the adsorbed monolayer subsequently undergoes conversion to a discrete atomic or molecular layer of a thin film, without any intervening pulse of or exposure to other chemical species or co-reactants.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: March 30, 2021
    Assignee: GELEST TECHNOLOGIES, INC.
    Inventors: Barry C. Arkles, Alain E. Kaloyeros
  • Patent number: 10923334
    Abstract: One or more embodiments described herein generally relate to selective deposition of substrates in semiconductor processes. In these embodiments, a precursor is delivered to a process region of a process chamber. A plasma is generated by delivering RF power to an electrode within a substrate support surface of a substrate support disposed in the process region of the process chamber. In embodiments described herein, delivering the RF power at a high power range, such as greater than 4.5 kW, advantageously leads to greater plasma coupling to the electrode, resulting in selective deposition to the substrate, eliminating deposition on other process chamber areas such as the process chamber side walls. As such, less process chamber cleans are necessary, leading to less time between depositions, increasing throughput and making the process more cost-effective.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: February 16, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Satya Thokachichu, Edward P. Hammond, IV, Viren Kalsekar, Zheng John Ye, Sarah Michelle Bobek, Abdul Aziz Khaja, Vinay K. Prabhakar, Venkata Sharat Chandra Parimi, Prashant Kumar Kulshreshtha, Kwangduk Douglas Lee
  • Patent number: 10872804
    Abstract: The present disclosure relates to a semiconductor processing apparatus having a reaction chamber which can include a baseplate having an opening; a moveable substrate support configured to support a substrate; a movement element configured to move a substrate held on the substrate support towards the opening of the baseplate; a plurality of gas inlets positioned above and configured to direct gas downwardly towards the substrate support; and a sealing element configured to form a seal between the baseplate and the substrate support, the seal positioned at a greater radial distance from a center of the substrate support than an outer edge of the substrate support. In some embodiments, the sealing element can also include a plurality of apertures extend through the sealing element, the apertures configured to provide a flow path between a position below the sealing element to a position above the sealing element. Some embodiments include two or more stacked sealing elements.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: December 22, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Carl Louis White, Kyle Fondurulia, John Kevin Shugrue, David Marquardt
  • Patent number: 10844487
    Abstract: A film deposition method is provided for filling a recessed pattern formed in a surface of a substrate with a film. In the method, an adsorption blocking group is formed by adsorbing chlorine gas activated by plasma on a top surface of the substrate and an upper portion of the recessed pattern. A source gas that contains one of silicon and a metal, and chlorine, is adsorbed on a lower portion of the recessed pattern where the adsorption blocking group is not formed, by supplying the source gas to the surface of the substrate including the recessed pattern. A molecular layer of a nitride film produced by a reaction of the source gas and a nitriding gas is deposited on the lower portion of the trench by supplying the nitriding gas to the surface of the substrate including the recessed pattern.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: November 24, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Yutaka Takahashi, Masahiro Murata, Hitoshi Kato
  • Patent number: 10811421
    Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yong Park, Kee-jeong Rho, Hyeong Park, Tae-wan Lim
  • Patent number: 10734219
    Abstract: Examples of a plasma film forming method include repeating feeding material gas onto a substrate placed on a susceptor via a shower head provided to oppose the susceptor, performing plasma film formation on the substrate by applying high frequency power to the shower head while providing reactant gas onto the substrate, and performing post-purge of discharging the gas used in the plasma film formation while heating the shower head, for a time longer than 0.1 seconds, a plurality of times in this order.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 4, 2020
    Assignee: ASM IP Holdings B.V.
    Inventor: Fumitaka Shoji
  • Patent number: 10727066
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
  • Patent number: 10685848
    Abstract: In a method of an embodiment, a tungsten film is formed on a workpiece. The workpiece includes an underlying film and a mask provided on the underlying film. The tungsten film has a first region extending along the side wall surface of the mask that defines an opening, and a second region extending on the underlying film. Subsequently, the tungsten film is plasma-etched while leaving the first region. In forming the tungsten film, a precursor gas containing tungsten is supplied to the workpiece. Then, plasma of hydrogen gas is generated in order to supply hydrogen active species to the precursor on the workpiece.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 16, 2020
    Assignee: TOKYO ELECTON LIMITED
    Inventors: Yu Nagatomo, Yoshihide Kihara
  • Patent number: 10651015
    Abstract: A substrate support includes an inner portion arranged to support a substrate, an edge ring surrounding the inner portion, and a controller that calculates a desired pocket depth of the substrate support. Pocket depth corresponds to a distance between an upper surface of the edge ring and an upper surface of the substrate. Based on the desired pocket depth, the controller selectively controls an actuator to raise and lower at least one of the edge ring and the inner portion to adjust the distance between the upper surface of the edge ring and the upper surface of the substrate.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: May 12, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Ivelin Angelov, Cristian Siladie, Dean Larson, Brian Severson
  • Patent number: 10626496
    Abstract: A film forming apparatus is provided for forming a film by revolving a substrate placed on a rotary table in a vacuum container, alternately supplying a precursor gas and a reaction gas that reacts with the precursor gas to generate a reaction product multiple times, and depositing the reaction product on the substrate. The film forming apparatus comprises a precursor gas supply region that supplies the precursor gas onto the substrate, one or more plasma generation regions that generate plasma at a position apart from the precursor gas supply region in a rotational direction of the rotary table, and a cleaning region that cleans the rotary table by supplying a cleaning gas onto the rotary table in a region apart from the plasma generation regions and the precursor gas supply region in the rotational direction when a film forming process is not performed on the substrate.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: April 21, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takayuki Karakawa, Jun Ogawa, Noriaki Fukiage, Yasuo Kobayashi
  • Patent number: 10615169
    Abstract: Methods and apparatuses for selectively depositing silicon nitride (SiN) via high-density plasma chemical vapor deposition (HDP CVD) to form a SiN pad on an exposed flat surface of a nitride layer in a 3D NAND staircase structure with alternating oxide and nitride layers are provided. In some embodiments, selective etching is performed to remove undesirable buildup of SiN on sidewalls of the oxide layers of the staircase structure. Nitride layers of the staircase structure are replaced with tungsten (W) to form tungsten wordlines, while the SiN pads are replaced with tungsten to from landing pads, which prevent punchthrough of the tungsten wordlines on the staircase structure by interconnects extending thereto.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: April 7, 2020
    Assignee: Lam Research Corporation
    Inventors: Bart J. van Schravendijk, Awnish Gupta, Patrick A. van Cleemput, Jason Daejin Park
  • Patent number: 10607817
    Abstract: Embodiments described herein generally related to a substrate processing apparatus, and more specifically to an improved showerhead assembly for a substrate processing apparatus. The showerhead assembly includes a gas distribution plate and one or more temperature detection assemblies. The gas distribution plate includes a body having a top surface and a bottom surface. The one or more temperature detection assemblies are interfaced with the top surface of the gas distribution plate such that a thermal bond is formed between the gas distribution plate and each of the one or more temperature detection assemblies. Each temperature detection assembly includes a protruded feature and a temperature probe. The protruded feature is interfaced with the top surface of the gas distribution plate such that an axial load is placed on the gas distribution plate along an axis of the protruded feature. The temperature probe is positioned in a body of the protruded feature.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: March 31, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Timothy Joseph Franklin, Steven E. Babayan, Philip Allan Kraus
  • Patent number: 10600900
    Abstract: In one embodiment, a semiconductor device is provided with a semiconductor layer made of a nitride semiconductor, a first gate electrode, a first structure body between the first gate electrode and the semiconductor layer, and a first insulating layer between the semiconductor layer and the first structure body. The first structure body has a first intermediate layer made of a conductor to suppress generation of charges at respective interfaces with adjacent layers, a first layer having dielectric property between the first gate electrode and the first intermediate layer, and a second layer having dielectric property between the first gate electrode and the first layer, and has dipoles at an interface between the first layer and the second layer.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 24, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Yonehara, Tatsuo Shimizu, Hiroshi Ono, Daimotsu Kato
  • Patent number: 10590534
    Abstract: A film deposition method is provided for filling a recessed pattern formed in a surface of a substrate with a film. In the method, a halogen-containing gas is supplied to a top surface of a substrate and an upper portion of a recessed pattern, thereby forming an adsorption blocking group on the top surface of the substrate and the upper portion of the recessed pattern. A first reaction gas is supplied to a surface of the substrate including the top surface and the recessed pattern to cause the first reaction gas to adsorb on an area where the adsorption blocking group is not formed on. A second reaction gas reactable with the first reaction gas is supplied to the surface of the substrate to produce a reaction product of the first reaction gas adsorbed on the bottom portion of the recessed pattern and the second reaction gas.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: March 17, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Takeshi Kumagai
  • Patent number: 10580736
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun
  • Patent number: 10546744
    Abstract: A process is provided for depositing a substantially amorphous titanium oxynitride thin film that can be used, for example, in integrated circuit fabrication, such as in forming spacers in a pitch multiplication process. The process comprises contacting the substrate with a titanium reactant and removing excess titanium reactant and reaction byproducts, if any. The substrate is then contacted with a second reactant which comprises reactive species generated by plasma, wherein one of the reactive species comprises nitrogen. The second reactant and reaction byproducts, if any, are removed. The contacting and removing steps are repeated until a titanium oxynitride thin film of desired thickness has been formed.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: January 28, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami J. Pore, Seiji Okura, Hidemi Suemori
  • Patent number: 10541309
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes first and second metal gates on a substrate with a gap therebetween. The first metal gate has a first sidewall, and the second metal gate has a second sidewall directly facing the first sidewall. A contact etch stop layer (CESL) is disposed within the gap and extends along the first and second sidewalls. The CESL has a first top portion adjacent to a top surface of the first metal gate and a second top portion adjacent to a top surface of the second metal gate. The first top portion and the second top portion have a trapezoid cross-sectional profile. A first sidewall spacer is disposed on the first sidewall and between the CESL and the first metal gate. A second sidewall spacer is disposed on the second sidewall and between the CESL and the second metal gate.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: January 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP
    Inventors: Yi-Fan Li, Kuo-Chin Hung, Wen-Yi Teng, Ti-Bin Chen
  • Patent number: 10529560
    Abstract: There is provided a technique that includes (a) pre-etching a surface of a substrate made of single crystal silicon by supplying a first etching gas to the substrate; (b) forming a silicon film on the substrate with the pre-etched surface, by supplying a first silicon-containing gas to the substrate; (c) etching a portion of the silicon film by supplying a second etching gas, which has a different molecular structure from a molecular structure of the first etching gas, to the substrate; and (d) forming an additional silicon film on the etched silicon film by supplying a second silicon-containing gas to the substrate.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: January 7, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Takahiro Miyakura, Atsushi Moriya, Naoharu Nakaiso, Kensuke Haga
  • Patent number: 10504717
    Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao, Melitta Manyin Hon, Hua Chung, Schubert S. Chu
  • Patent number: 10476000
    Abstract: A method of forming a target layer in semiconductor fabrication is disclosed that includes steps of forming a first layer by performing a first process at least one time and forming a second layer by performing a second process at least one time, wherein the first process may include supplying a first source gas, supplying a second source gas several times, and supplying an inert gas several times.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: November 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeonghee Park, Kyoung Sun Kim
  • Patent number: 10460928
    Abstract: A process is provided for depositing a substantially amorphous titanium oxynitride thin film that can be used, for example, in integrated circuit fabrication, such as in forming spacers in a pitch multiplication process. The process comprises contacting the substrate with a titanium reactant and removing excess titanium reactant and reaction byproducts, if any. The substrate is then contacted with a second reactant which comprises reactive species generated by plasma, wherein one of the reactive species comprises nitrogen. The second reactant and reaction byproducts, if any, are removed. The contacting and removing steps are repeated until a titanium oxynitride thin film of desired thickness has been formed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: October 29, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami J. Pore, Seiji Okura, Hidemi Suemori
  • Patent number: 10385448
    Abstract: A processing chamber is described having a gas evacuation flow path from the center to the edge of the chamber. Purge gas is introduced at an opening around a support shaft that supports a heater plate. A shaft wall around the opening directs the purge gas along the support shaft to an evacuation plenum. Gas flows from the evacuation plenum through an opening in a second plate near the shaft wall and along the chamber bottom to an opening coupled to a vacuum source. Purge gas is also directed to the slit valve.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: August 20, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Juan Carlos Rocha-Alvarez, Amit Kumar Bansal, Ganesh Balasubramanian, Jianhua Zhou, Ramprakash Sankarakrishnan
  • Patent number: 10388530
    Abstract: Provided is a technique of adjusting a work function. A method of manufacturing a semiconductor device includes: (a) forming a titanium nitride layer on a substrate by supplying a first source containing titanium and a second source containing nitrogen to the substrate; (b) forming a titanium aluminum carbonitride layer on the substrate by supplying the first source, the second source and a third source containing aluminum and carbon to the substrate; (c) forming a laminated film on the substrate by performing (a) and (b); and (d) adjusting ratios of titanium, nitrogen, aluminum and carbon in the laminated film based on how many times (a) and (b) are performed.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: August 20, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Arito Ogawa, Kazuhiro Harada, Yukinao Kaga, Hideharu Itatani, Hiroshi Ashihara
  • Patent number: 10355111
    Abstract: A method includes depositing an inhibitor layer on a first surface, depositing a film on a second surface by performing a first set of deposition cycles. Each deposition cycle includes adsorbing a first precursor over the second surface, performing a first purge process, adsorbing a second precursor over the second surface, and performing a second purge process. The method also includes performing a third purge process that is different from the first purge process or the second purge process.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi On Chui, Bo-Cyuan Lu
  • Patent number: 10269569
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Shiung Tsai, Chung-Chiang Wu, Wei-Fan Liao, Han-Ti Hsiaw
  • Patent number: 10236197
    Abstract: An apparatus and method for processing a substrate in a processing system containing a deposition chamber, a treatment chamber, and an isolation region, separating the deposition chamber from the treatment is described herein. The deposition chamber deposits a film on a substrate. The treatment chamber receives the substrate from the deposition chamber and alters the film deposited in the deposition chamber with a film property altering device. Processing systems and methods are provided in accordance with the above embodiment and other embodiments.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: March 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Karthik Janakiraman, Abhijit Basu Mallick, Hari K. Ponnekanti, Mandyam Sriram, Alexandros T. Demos, Mukund Srinivasan, Juan Carlos Rocha-Alvarez, Dale R. Dubois
  • Patent number: 10236190
    Abstract: Embodiments disclosed herein generally relate to methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a III-V epitaxial growth process or an etch clean process, and prior to additional processing. An oxygen containing gas is flowed to a substrate in a load lock chamber, and subsequently a non-reactive gas is flowed to the substrate in the load lock chamber. As such, hazardous gases and outgassing residuals are decreased and/or removed from the substrate such that further processing may be performed.
    Type: Grant
    Filed: May 6, 2017
    Date of Patent: March 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao
  • Patent number: 10131986
    Abstract: There is provided a method for forming a metal film on a target substrate having a complex-shaped portion and a flat portion, the target substrate being loaded into a chamber which is maintained under a depressurized atmosphere, by sequentially supplying a metal chloride gas as a raw material gas and a reduction gas for reducing a metal chloride into the chamber while purging the chamber in the course of sequentially supplying the metal chloride gas and the reduction gas, the method including: forming a first metal film by supplying the metal chloride gas at a relatively low flow rate; and forming a second metal film by supply the metal chloride gas at a relatively high flow rate.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: November 20, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kenji Suzuki, Takanobu Hotta, Koji Maekawa, Yasushi Aiba