Utilizing Chemical Vapor Deposition (i.e., Cvd) Patents (Class 438/680)
  • Patent number: 9954135
    Abstract: A method for manufacturing solar cell includes the following. A solution containing aluminum elements is misted. The misted solution is sprayed onto the main surface of a p-type silicon substrate in the atmosphere, to thereby form an aluminum oxide film. Then, a solar cell is produced using the p-type silicon substrate including the aluminum oxide film formed thereon.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 24, 2018
    Assignees: Toshiba Mitsubishi-Electric Industrial Systems Corporation, Kyoto University, Kochi Prefectural Public University Corporation
    Inventors: Takahiro Hiramatsu, Hiroyuki Orita, Takahiro Shirahata, Toshiyuki Kawaharamura, Shizuo Fujita
  • Patent number: 9754816
    Abstract: The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: September 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Hayashi, Naoya Inoue, Kishou Kaneko
  • Patent number: 9640784
    Abstract: A deposition apparatus includes a substrate combining unit configured to dispose a substrate on a moving unit including a surface, a first blocking member combining unit configured to raise a first blocking member, a first deposition unit including one or more deposition assemblies configured to deposit a material on the substrate, a first blocking member separation unit configured to separate the first blocking member downward from the moving unit, and a first conveyer unit configured to convey the moving unit in a first direction, where the one or more deposition assemblies are spaced apart from the substrate by a predetermined distance so that the material is deposited on the substrate in the first deposition unit while the moving unit is conveyed in the first direction.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: May 2, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jin-Seok Son
  • Patent number: 9627184
    Abstract: A plasma processing apparatus includes a processing chamber, in which a wafer W is plasma-processed, and a CPU controlling an operation of each component. A processing gas is introduced into the processing chamber under a first condition defined by a flow rate and a molecular weight of the processing gas, specifically based on a magnitude of a product A1 (=Q1×m1) of the flow rate Q1 and the molecular weight m1 of the processing gas, and a surface of the wafer W is physically or chemically etched. And then, a pre-purge gas which may be identical to or different from the processing gas is introduced into the processing chamber through a shower head under a second condition derived from the first condition.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: April 18, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tsuyoshi Moriya, Hiroyuki Nakayama, Hiroshi Nagaike
  • Patent number: 9613818
    Abstract: Provided herein are methods of depositing bulk tungsten by sequential CVD pulses, such as by alternately pulsing tungsten hexafluoride and hydrogen gas in cycles of temporally separated pulses. Some methods include depositing a tungsten nucleation layer at low pressure followed by deposition of bulk tungsten by sequential CVD to form low stress tungsten films with low fluorine content. Methods described herein may also be performed in combination with non-sequential CVD deposition and fluorine-free tungsten deposition techniques.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: April 4, 2017
    Assignee: Lam Research Corporation
    Inventors: Xiaolan Ba, Raashina Humayun, Michal Danek, Lawrence Schloss
  • Patent number: 9589809
    Abstract: A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiH4 base W film on a surface of a substrate to preprocess the surface. The method includes depositing a B2H6 base W layer on the preprocessed surface. The SiH4 base W film may be several atom layers thick. The film and base W layer may be deposited in a single ALD process, include reactive gas soak, reactive gas introduction, and main deposition operations. Forming the film may include introducing SiH4 gas into a reactive cavity during the gas soak operation, and introducing SiH4 and WF6 gas into the cavity during the gas introduction operation. The SiH4 and WF6 gases may be alternately introduced, for a number of cycles depending on the thickness of the tungsten layer to be deposited.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: March 7, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiang Xu, Chao Zhao, Jun Luo, Guilei Wang, Tao Yang, Junfeng Li
  • Patent number: 9583245
    Abstract: A magnet plate assembly includes a plurality of magnetic substances having predetermined magnetic forces, a magnet supporter supporting at least a corresponding one of the plurality of magnetic substances, and a guide support supporting the magnet supporter and comprising at least one guide opening. The magnetic plate assembly further includes a coupler extending through the at least one guide opening and movable within the at least one guide opening, the coupler being connected to the magnet supporter; and a driver unit connected to the coupler and configured to move the corresponding one of the plurality of magnetic substances with respect to the guide support.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 28, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Minpyo Hong, Hongryul Kim
  • Patent number: 9543220
    Abstract: According to the present disclosure, it is possible to prevent particles from being generated and to improve substrate processing quality.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: January 10, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Takeo Sato
  • Patent number: 9530627
    Abstract: Embodiments described herein relate to a thermal chlorine gas cleaning process. In one embodiment, a method for cleaning N-Metal film deposition in a processing chamber includes positioning a dummy substrate on a substrate support. The processing chamber is heated to at least about 50 degrees Celsius. The method further includes flowing chlorine gas into the processing chamber and evacuating chlorine gas from the processing chamber. In another embodiment, a method for cleaning titanium aluminide film deposition in a processing chamber includes heating the processing chamber to a temperature between about 70 about degrees Celsius and about 100 degrees Celsius, wherein the processing chamber and the substrate support include one or more fluid channels configured to heat or cool the processing chamber and the substrate support.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: December 27, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Xinliang Lu, Kyoung-Ho Bu, Jing Zhou, Seshadri Ganguli, David Thompson
  • Patent number: 9508555
    Abstract: To improve quality or manufacturing throughput of a semiconductor device, a method includes supplying a source gas to a substrate in a process chamber; exhausting an inside of the process chamber; supplying a reaction gas to the substrate; and exhausting the inside of the process chamber, wherein the source gas and/or the reaction gas is supplied in temporally separated pulses in the supply of the source gas and/or in the supply of the reaction gas. Then, the source gas and/or the reaction gas is supplied in temporally separated pulses to form a film during a gas supply time determined by a concentration distribution of by-products formed on a surface of the substrate.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: November 29, 2016
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Yukinao Kaga, Arito Ogawa, Atsuro Seino, Atsuhiko Ashitani, Ryohei Maeno, Masanori Sakai
  • Patent number: 9481929
    Abstract: A vapor deposition apparatus for depositing thin films on a substrate includes a supply unit including a plurality of linear supply members configured to supply at least one gas; and a nozzle unit including a plurality of nozzle members connected to the plurality of supply members and configured to supply the at least one gas toward the substrate, wherein two adjacent nozzle members of the plurality of nozzle members are connected to at least one common supply member of the plurality of supply members.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: November 1, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Choel-Min Jang, Sung-Hun Key, In-Kyo Kim, Suk-Won Jung, Myung-Soo Huh
  • Patent number: 9466524
    Abstract: Methods for depositing metal layers, and more specifically TaN layers, using CVD and ALD techniques are provided. In one or more embodiments, the method includes sequentially exposing a substrate to a metal precursor, or more specifically a tantalum precursor, followed by a high frequency plasma.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: October 11, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Paul F. Ma, Guojun Liu, Annamalai Lakshmanan, Dien-Yeh Wu, Anantha K. Subramani
  • Patent number: 9466477
    Abstract: There are provided a method of manufacturing a semiconductor device, a substrate processing apparatus, and a semiconductor device. The method allows rapid formation of a conductive film, which has a low concentration of impurities permeated from a source owing to its dense structure, and a low resistivity. The method is performed by simultaneously supplying two or more kinds of sources into a processing chamber to form a film on a substrate placed in the processing chamber. The method comprises: performing a first source supply process by supplying at least one kind of source into the processing chamber at a first supply flow rate; and performing a second source supply process by supplying the at least one kind of source into the processing chamber at a second supply flow rate different from the first supply flow rate.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: October 11, 2016
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Tatsuyuki Saito, Masanori Sakai, Yukinao Kaga, Takashi Yokogawa
  • Patent number: 9466478
    Abstract: A method of forming an oxide film on an object to be processed, includes: supplying a film-forming raw material gas into a processing chamber; performing at least one of exhausting the processing chamber and supplying a purge gas into the processing chamber to remove gas remaining in the processing chamber; supplying an oxidant gas into the processing chamber; and performing at least one of exhausting the processing chamber and supplying the purge gas into the processing chamber to remove gas remaining in the processing chamber, wherein supplying an oxidant gas includes: supplying a first oxidant gas into the processing chamber at a first concentration; and supplying a second oxidant gas into the processing chamber at a second concentration higher than the first concentration.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 11, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Shimizu, Tsuyoshi Tsunatori, Shigeru Nakajima
  • Patent number: 9449843
    Abstract: Methods of selectively etching metals and metal nitrides from the surface of a substrate are described. The etch selectively removes metals and metal nitrides relative to silicon-containing layers such as silicon, polysilicon, silicon oxide, silicon germanium, silicon carbide, silicon carbon nitride and/or silicon nitride. The etch removes material in a conformal manner by including an oxidation operation which creates a thin uniform metal oxide. The thin uniform metal oxide is then removed by exposing the metal oxide to a metal-halogen precursor in a substrate processing region. The metal oxide may be removed to completion and the etch may stop once the uniform metal oxide layer is removed. Etches described herein may be used to uniformly trim back material on high aspect ratio features which ordinarily show higher etch rates near the opening of a gap compared to deep within the gap.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: September 20, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Mikhail Korolik, Nitin K. Ingle, David Thompson, Jeffrey W. Anthis, David Knapp, Benjamin Schmiege
  • Patent number: 9418855
    Abstract: A halogen element-containing metal material and a nitrogen-containing material are alternately supplied to a process chamber with a flow rate of an inert gas supplied to the process chamber together with the nitrogen-containing material during the supplying of the nitrogen-containing material to the process chamber being more increased than a flow rate of the inert gas supplied to the process chamber together with the metal material during the supplying of the metal material to the process chamber.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 16, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kimihiko Nakatani, Kazuhiro Harada, Hiroshi Ashihara
  • Patent number: 9349586
    Abstract: A thin film having excellent etching resistance and a low dielectric constant is described. A method of manufacturing a semiconductor device includes forming a thin film on a substrate, removing first impurities containing H2O and Cl from the thin film by heating the thin film at a first temperature higher than a temperature of the substrate in the forming of the thin film, and removing second impurities containing a hydrocarbon compound (CxHy-based impurities) from the thin film in which heat treatment is performed at the first temperature by heating the thin film at a second temperature equal to or higher than the first temperature.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: May 24, 2016
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Satoshi Shimamoto, Takaaki Noda, Takeo Hanashima, Yoshiro Hirose, Hiroshi Ashihara, Tsukasa Kamakura, Shingo Nohara
  • Patent number: 9341923
    Abstract: A composite plastic member includes a first stacked body comprised of a plurality of chromium layers stacked on a plastic substrate; and a second stacked body comprised of a plurality of chromium nitride layers stacked on the first stacked body. Each of the first and second stacked bodies is formed such that a lower-hardness layer having a lower hardness than upper and lower layers which contact with and sandwich the lower-hardness layer therebetween and a higher-hardness layer having a higher hardness than upper and lower layers which contact with and sandwich the higher-hardness layer therebetween are alternately stacked in a stacking direction; and a thickness of a higher-hardness chromium nitride layer is not more than 40% of a thickness of a lower-hardness chromium nitride layer in the second stacked body. The composite plastic member has high wear resistance and satisfactory sliding performance, and the conductivity and excellent outer appearance.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: May 17, 2016
    Assignee: NIKON CORPORATION
    Inventors: Yusuke Taki, Yohei Takahashi, Yujiro Urakawa
  • Patent number: 9340880
    Abstract: Semiconductor fabrication processes are described. An embodiment of the semiconductor fabrication process includes providing a layer formed by decomposition of dimethylsilane through chemical vapor deposition, the layer being applied by a fluid material, and then positioning the layer in a system for producing a semiconductor product. Additionally or alternatively, the semiconductor product is produced and/or the layer is on a substrate.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 17, 2016
    Assignee: Silcotek Corp.
    Inventor: James B. Mattzela
  • Patent number: 9330939
    Abstract: Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a contact metal layer on a substrate and annealing the contact metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the contact metal layer on the substrate, exposing the portion of the contact metal layer to a plasma treatment process, and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the contact metal layer to a plasma treatment process until a predetermined thickness of the contact metal layer is achieved.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 3, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bhushan N. Zope, Avgerinos V. Gelatos, Bo Zheng, Yu Lei, Xinyu Fu, Srinivas Gandikota, Sang-Ho Yu, Mathew Abraham
  • Patent number: 9331218
    Abstract: Provided are a solar cell module and a method of manufacturing the same. The solar cell module including: a substrate; a bottom electrode layer discontinuously formed on the substrate; a light absorbing layer formed on the bottom electrode layer and including a first trench that exposes the bottom electrode layer; and a transparent electrode layer extending from the top of the light absorbing layer to the bottom electrode layer at the bottom of the first trench, and including a first oxide layer, a metal layer, and a second oxide layer, all of which are staked on the light absorbing layer and the bottom electrode layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 3, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Woo-Seok Cheong, Rae-Man Park
  • Patent number: 9297072
    Abstract: A film deposition apparatus includes a rotary table having a substrate placement area to support a substrate, a vacuum container including a container and a top panel, an open-and-close mechanism configured to open and close the top panel, reactant gas nozzles disposed through and supported by an outer wall of the container to be situated at different angular positions with respect to a rotation center of the rotary table to face areas in which the substrate placement area passes, the reactant gas nozzles having gas discharge ports arranged in radial directions to supply respective reactant gases to the wafer thereby to form respective process areas, a discharge gas supply unit situated at an angular position between the process areas to supply purge gas to form an isolation area that isolates atmospheres of the process areas from each other, and an exhaustion unit configured to exhaust atmosphere inside the vacuum container.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: March 29, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Manabu Honma
  • Patent number: 9257278
    Abstract: When forming a TiN film to be formed as a metallic hard mask for etching a film formed on a substrate to be processed, a first step and a second step are repeated a plurality of times to form a TiN film having reduced film stress. In the first step (step 1), the substrate to be processed is conveyed into a processing chamber, TiCl4 gas and a nitriding gas are fed into the processing chamber, the interior of which being kept in a depressurized state during this time, and a plasma from the gases is generated to form a TiN unit film. In the second step (step 2), a nitriding gas is fed into the processing container, a plasma of the gas is generated, and the TiN unit film is subjected to plasma nitriding.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: February 9, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hideaki Yamasaki, Takeshi Yamamoto
  • Patent number: 9245780
    Abstract: A vacuum processing apparatus includes a row of containers of vacuum transfer chambers connected to each other behind a lock chamber, a wafer being transferred through depressurized inside of the row of the containers of the vacuum transfer containers, an intermediate chamber disposed between the containers of the vacuum transfer chambers, a plurality of processing units including processing containers respectively connected to left or right side walls of the containers of the vacuum transfer chambers and the wafer is processed therein, and a bypass chamber which constitutes a bypass path connecting the processing units, where only either the wafer which is being transferred from the lock chamber toward one of the processing units or the wafer which was processed in one of the processing units and is being transferred toward the lock chamber is transferred through the containers of the vacuum transfer chambers.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: January 26, 2016
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Takahiro Shimomura, Yoshifumi Ogawa, Susumu Tauchi
  • Patent number: 9200364
    Abstract: A film forming apparatus for forming a film on an object includes: a processing container; gas supply means, having gas jet ports, respectively; a holding means for holding the object; a drive mechanism for moving the holding means relative to the gas jet ports; and a control means which, when repeating P times a cycle, consisting of a supply period for supplying a gas and a supply stop period during which the supply of the gas is stopped, performs control so that as viewed from the center of the object, a gas supply starting position is sequentially shifted in the circumferential direction of the object for every cycle in such a manner that the entire circumference of the object to be processed is divided into K segments (K=P), K being an arbitrary division number, and the gas supply starting position is shifted by one segment for every cycle.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: December 1, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Shozo Ito
  • Patent number: 9153430
    Abstract: Provided is a substrate processing apparatus. The substrate processing apparatus includes: a process chamber configured to accommodate a substrate; a substrate holding member configured to hold the substrate in the process chamber; a first gas supply system including a first gas supply hole for supplying a first process gas into the process chamber; a second gas supply system including a second gas supply hole for supplying a second process gas into the process chamber; and a catalyst supply system including a catalyst supply hole for supplying a catalyst into the process chamber, wherein an angle between a first imaginary line connecting a center of the substrate holding member and the first gas supply hole and a second imaginary line connecting the center of the substrate holding member and the catalyst supply hole ranges from 63.5 degrees to 296.5 degrees.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 6, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takaaki Noda, Jie Wang
  • Patent number: 9123510
    Abstract: A method for controlling in-plane uniformity of a substrate processed by plasma-assisted process in a reactor, includes: supplying a principal gas to a reaction space, and discharging radially the principal gas from the reaction space through an annular duct; and supplying an secondary gas to the reaction space from an area in close proximity to an outer periphery of a susceptor, outside an outer circumference of the substrate as viewed from above, so as to flow at least partially in an inward direction passing the outer circumference of the substrate, reversing the direction of the secondary gas to flow toward the annular duct in a vicinity of the outer circumference of the substrate, and discharging radially the secondary gas together with the principal gas from the reaction space through the annular duct.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 1, 2015
    Assignee: ASM IP HOLDING, B.V.
    Inventors: Ryu Nakano, Naoki Inoue
  • Patent number: 9117658
    Abstract: There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: August 25, 2015
    Assignees: SUMITOMO CHEMICAL COMPANY, LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Mitsuru Takenaka, Shinichi Takagi, Jaehoon Han, Tomoyuki Takada, Takenori Osada, Masahiko Hata
  • Patent number: 9087619
    Abstract: A collimator for an imaging system includes a first region comprising a first one-dimensional array of apertures along a channel direction, and a second region comprising a second one-dimensional array of apertures along the channel direction, wherein an aspect ratio of the apertures of the first region is greater than an aspect ratio of the second region.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: July 21, 2015
    Assignee: General Electric Company
    Inventors: Jiang Hsieh, Thomas Murray Leeds, Abdelaziz Ikhlef
  • Patent number: 9087864
    Abstract: In some embodiments, apparatus are provided that provide for flexible processing in high productivity combinatorial (HPC) system. The apparatus allow for interchangeable functionality that includes deposition, plasma treatment, ion beam treatment, in-situ annealing, and in-situ metrology. The apparatus are designed so that the functionality may be integrated within a single processing chamber for enhanced flexibility.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: July 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Chen-An Chen, Tony P. Chiang, Frank Greer, Martin Romero, James Tsung
  • Patent number: 9059255
    Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 16, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Xunyuan Zhang
  • Patent number: 9040413
    Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and lifetime by custom tailoring the average concentration of defects in the resistive switching film and methods of forming the same. The nonvolatile memory element includes a first electrode layer, a second electrode layer, and a resistive switching layer disposed between the first electrode layer and the second electrode layer. The resistive switching layer comprises a first sub-layer and a second sub-layer, wherein the first sub-layer has more defects than the first sub-layer. A method includes forming a first sub-layer on the first electrode layer by a first ALD process and forming a second sub-layer on the first sub-layer by a second ALD process, where the first sub-layer has a different amount of defects than the second sub-layer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 26, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Randall J. Higuchi, Chien-Lan Hsueh, Yun Wang
  • Publication number: 20150137275
    Abstract: The present invention relates to a method for decreasing the impedance of a titanium nitride element for use in an electrode component. The method comprises obtaining a titanium nitride element and hydrothermally treating the titanium nitride element by immersing the titanium nitride element in a liquid comprising water while heating said liquid.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 21, 2015
    Applicant: IMEC VZW
    Inventor: Silke Musa
  • Patent number: 9034761
    Abstract: Disclosed are metal-containing precursors having the formula Compound (I) wherein: —M is a metal selected from Ni, Co, Mn, Pd; and —each of R-1, R2, R3, R4, R5, R6, R7, R8, R9, and R10 are independently selected from H; a C1-C4 linear, branched, or cyclic alkyl group; a C1-C4 linear, branched, or cyclic alkylsilyl group (mono, bis, or tris alkyl); a C1-C4 linear, branched, or cyclic alkylamino group; or a C1-C4 linear, branched, or cyclic fluoroalkyl group. Also disclosed are methods of synthesizing and using the disclosed metal-containing precursors to deposit metal-containing films on a substrate via a vapor deposition process.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 19, 2015
    Assignees: L'Air Liquide, SociétéAnonyme pour l'Etude et l'Exploitation des Procédés Georges Claude, American Air Liquide, Inc.
    Inventors: Clément Lansalot-Matras, Andrey V. Korolev
  • Patent number: 9034760
    Abstract: Methods, apparatus, and systems for depositing tensile or compressive tungsten films are described. In one aspect, a method includes providing a substrate to a chamber. The substrate has a field region and a feature recessed from the field region. Then, the substrate is exposed to an organometallic tungsten precursor. The organometallic tungsten precursor not adsorbed onto the substrate is removed from the chamber. The substrate is treated with a first treatment including a heat treatment or a plasma treatment to form a tungsten layer on the substrate. After treating the substrate, residual gasses are removed from the chamber. The tungsten layer on the substrate is treated with a second treatment including a heat treatment or a plasma treatment.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: May 19, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Roey Shaviv, Raashina Humayun, Deqi Wang
  • Patent number: 9029253
    Abstract: Nitrogen-containing phase-stabilized films, methods of forming phase-stabilized films, and structures and devices including the phase-stabilized films are disclosed. The phase-stabilized films include a matrix material and a phase stabilizer, which provides a morphologically stabilizing effect to a matrix material within the films. The phase-stabilized films may be used as, for example, gate electrodes and similar films in microelectronic devices.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: May 12, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Robert Brennan Milligan, Fred Alokozai
  • Publication number: 20150126031
    Abstract: A process for depositing a metal includes disposing an activating catalyst on a substrate; contacting the activating catalyst with a metal cation from a vapor deposition composition; contacting the substrate with a reducing anion from the vapor deposition composition; performing an oxidation-reduction reaction between the metal cation and the reducing anion in a presence of the activating catalyst; and forming a metal from the metal cation to deposit the metal on the substrate.
    Type: Application
    Filed: January 14, 2015
    Publication date: May 7, 2015
    Inventor: Owen HILDRETH
  • Patent number: 9018050
    Abstract: A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: April 28, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Wen Huang
  • Patent number: 9011600
    Abstract: A chemical vapour deposition system, including: a process tube for receiving at least one sample, the process tube being constructed of silicon carbide, impregnated with silicon, and coated with silicon carbide; a pumping system to evacuate the process tube to high vacuum; one or more gas inlets for introducing one or more process gases into the evacuated process tube; and a heater to heat the process tube and thereby heat the one or more process gases and the at least one sample within the process tube to cause a material to be deposited onto the at least one sample within the process tube by chemical vapour deposition.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: April 21, 2015
    Assignee: Griffith University
    Inventor: Alan Victor Iacopi
  • Publication number: 20150099359
    Abstract: Systems, methods and apparatus for processing a substrate are disclosed. A reactor for processing a substrate includes a reaction chamber, a substrate support, a nozzle, and an outlet. The chamber is configured to process a single substrate on the substrate support. The nozzle extends along an axis of elongation along a side of the chamber. The nozzle includes a nozzle body forming an inner volume, an inlet providing fluid communication between a reactant source and the inner volume, and a plurality of holes spaced along the axis of elongation. The holes provide fluid communication between the inner volume of the nozzle body and the reaction chamber. The nozzle is configured such that fluid conductance through the holes increases with increasing distance from the inlet. The outlet is configured to allow flow from the nozzle through the reaction chamber to the outlet. The flow is parallel to a major surface of the substrate.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Ana R. Londergan, Sandeep K. Giri, Teruo Sasagawa, Shih Chou Chiang
  • Patent number: 8999805
    Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.
    Type: Grant
    Filed: October 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 8987148
    Abstract: With a stage kept in an as-heated state, a semiconductor wafer is placed over the stage. Then, with the elapse of a first time, a controller causes a pressure inside a vacuum chamber to rise to a second pressure higher than a first pressure (step S40). After the semiconductor wafer is placed over the stage, a pressure difference between a pressure inside the vacuum chamber and a pressure inside an adsorption port is set to a minimum value at which the semiconductor wafer is not allowed to slide over protrusions. Further, in step S40 as well, the pressure difference is kept at the minimum value at which the semiconductor wafer is not allowed to slide over the protrusions.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Misato Sakamoto, Yoshitake Katou, Youichi Yamamoto, Takashi Kyouno, Chikara Yamamoto, Terukazu Motosawa, Mitsuo Maeda, Hiroshi Itou
  • Patent number: 8980682
    Abstract: Methods of forming absorber layers in a TFPV device are provided. Methods are described to provide the formation of metal oxide films and heating the metal oxide films in the presence of a chalcogen to form a metal-oxygen-chalcogen alloy. Methods are described to provide the formation of metal oxide films, forming a layer of elemental chalcogen on the metal oxide film, and heating the stack to form a metal-oxygen-chalcogen alloy. In some embodiments, the metal oxide film includes zinc oxide and the chalcogen includes selenium.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Jeroen Van Duren
  • Patent number: 8975184
    Abstract: Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Michal Danek
  • Patent number: 8962350
    Abstract: Multi-step deposition of lead-zirconium-titanate (PZT) ferroelectric material. An initial portion of the PZT material is deposited by metalorganic chemical vapor deposition (MOCVD) at a low deposition rate, for example at a temperature below about 640 deg C. from vaporized liquid precursors of lead, zirconium, and titanium, and a solvent at a collective flow rate below about 1.1 ml/min, in combination with an oxidizing gas. Following deposition of the PZT material at the low flow rate, the remainder of the PZT film is deposited at a high deposition rate, attained by changing one or more of precursor and solvent flow rate, oxygen concentration in the oxidizing gas, A/B ratio of the precursors, temperature, and the like.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: February 24, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Bhaskar Srinivasan, Brian E. Goodlin, Haowen Bu, Mark Visokay
  • Patent number: 8962461
    Abstract: Consistent with an example embodiment, a GaN heterojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectriclayer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 24, 2015
    Assignee: NXP B.V.
    Inventors: Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers, Stephan Heil, Jan Sonsky
  • Patent number: 8951878
    Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Hironobu Shoji, Hideto Ohnuma, Shunpei Yamazaki
  • Publication number: 20150031203
    Abstract: A method for processing a workpiece may include: providing a workpiece including a first region and a second region; forming a porous metal layer over the first region and the second region; wherein the first region and the second region are configured such that an adhesive force between the second region and the porous metal layer is lower than an adhesive force between the first region and the porous metal layer.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Inventors: Michael KRENZER, Thomas KUNSTMANN, Eva-Maria HESS, Manfred FRANK
  • Publication number: 20150031167
    Abstract: A deposition apparatus for performing a deposition process on a substrate includes: an injection unit including a plasma generating member which receives a raw material gas and converts the raw material gas to a deposition source material in a radical form; and a plasma processor disposed adjacent to the injection unit and facing a side of the injection unit, wherein the plasma processor performs a plasma process in a direction facing the substrate.
    Type: Application
    Filed: May 4, 2014
    Publication date: January 29, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Myung-Soo HUH, Suk-Won JUNG, Sung-Chul KIM, Sang-Hyuk HONG, Choel-Min JANG
  • Patent number: 8937020
    Abstract: One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Keiji Sato