Silicide Patents (Class 438/682)
  • Patent number: 9691917
    Abstract: A photovoltaic device (e.g., solar cell) includes: a front substrate (e.g., glass substrate); a semiconductor absorber film; a back contact including a first conductive layer of or including copper (Cu) and a second conductive layer of or including molybdenum (Mo); and a rear substrate (e.g., glass substrate). A selenium blocking layer is provided between at least the Cu inclusive layer and the Mo inclusive layer.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: June 27, 2017
    Assignee: Guardian Industries Corp.
    Inventor: Alexey Krasnov
  • Patent number: 9543167
    Abstract: A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin, the metal layer extends from the first diamond shaped epitaxial layer to the second diamond shaped epitaxial layer, the laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers, and the silicide layer takes on a crystal orientation of the first and the second epitaxial layers.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brent A. Anderson, Nicolas Breil, Christian Lavoie
  • Patent number: 9142430
    Abstract: Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: September 22, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Richard A. Dunipace
  • Patent number: 9093425
    Abstract: Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nicolas Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg, Jian Yu
  • Patent number: 9070664
    Abstract: A device includes a substrate and a metal-oxide-semiconductor (MOS) device. The MOS device includes a gate dielectric over the substrate, a gate electrode over the gate dielectric, a source/drain region adjacent the gate dielectric, and a source/drain silicide over and contacting the source/drain region. The source/drain silicide comprises silicon, nickel, and a secondary metal. A ratio of a volume percentage of the secondary metal to a volume percentage of the silicon in the source/drain silicide is between about 0.005 and about 0.1. The secondary metal has a density between about 5,000 kg/m3 and about 15,000 kg/m3.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 30, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Ying-Lang Wang, Kei-Wei Chen
  • Publication number: 20150137794
    Abstract: The present invention generally relates to nanoscale wires for use in sensors and other applications. In various embodiments, a probe comprising a nanotube (or other nanoscale wire) is provided that can be directly inserted into a cell to determine a property of the cell, e.g., an electrical property. In some cases, only the tip of the nanoscale wire is inserted into the cell; this tip may be very small relative to the cell, allowing for very precise study. In some aspects, the tip of the probe is held by a holding member positioned on a substrate, e.g., at an angle, which makes it easier for the probe to be inserted into the cell. The nanoscale wire may also be connected to electrodes and/or form part of a transistor, such that a property of the nanoscale wire, and thus of the cell, may be determined. Such probes may also be useful for studying other samples besides cells.
    Type: Application
    Filed: May 2, 2013
    Publication date: May 21, 2015
    Inventors: Charles M. Lieber, Ruixuan Gao, Steffen Strehle, Xiaojie Duan, Bozhi Tian, Itzhaq Cohen-Karni, Ping Xie, Quan Qing
  • Publication number: 20150111381
    Abstract: Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 23, 2015
    Inventors: Yoon-Hae KIM, Jong-Shik YOON, Hwa-Sung RHEE, Byung-Sung KIM
  • Patent number: 9006104
    Abstract: In one example, the method includes forming a metal layer on a silicon-containing structure, after forming the metal layer, performing an ion implantation process to implant silicon atoms into at least one of the metal layer and the silicon-containing structure and performing a first millisecond anneal process so as to form a first metal silicide region in the silicon-containing structure.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Vidmantas Sargunas
  • Patent number: 9000494
    Abstract: A structure includes a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor having metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a hard mask formed as a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer. The hard mask protects the underlying material during a MEMS/NEMS HF vapor release procedure.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Fei Liu, Ying Zhang
  • Publication number: 20150084183
    Abstract: Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided.
    Type: Application
    Filed: September 23, 2013
    Publication date: March 26, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Joachim Patzer, Hans-Peter Moll
  • Patent number: 8987071
    Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: March 24, 2015
    Assignee: National Applied Research Laboratories
    Inventors: Min-Cheng Chen, Chang-Hsien Lin, Chia-Yi Lin, Tung-Yen Lai, Chia-Hua Ho
  • Patent number: 8987127
    Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: March 24, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Jun Luo, Chao Zhao, Huicai Zhong, Junfeng Li, Dapeng Chen
  • Publication number: 20150079767
    Abstract: A semiconductor device includes semiconductor bodies formed substantially perpendicular to a semiconductor substrate, buried bit lines formed in the semiconductor bodies and including a metal silicide; and barrier layers formed under and over the buried bit lines and containing germanium.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 19, 2015
    Inventors: Ju-Hyun MYUNG, Eui-Seong HWANG, Eun-Shil PARK, Tae-Yoon KIM
  • Patent number: 8981565
    Abstract: In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Dong-Ick Lee, Ahmet Serkan Ozcan, Zhen Zhang
  • Patent number: 8969202
    Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 3, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Ying-Tso Chen, Shih-Chang Tsai, Chun-Fu Chen
  • Patent number: 8962431
    Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, John Mark Meldrim, Rita J. Klein
  • Patent number: 8962439
    Abstract: A method of programming a memory cell includes causing a current to flow through a first silicide-containing portion and a second silicide-containing portion of the memory cell; and causing, by the current, an electron-migration effect to form an extended silicide-containing portion within the gap such that the memory cell is converted from a first state into a second state. The memory cell includes a silicon-containing line continuously extending between a first region and a second region; the first silicide-containing portion over the silicon-containing line and adjacent to the first region; and the second silicide-containing portion over the silicon-containing line and adjacent to the second region. The first silicide-containing portion and the second silicide-containing portion are separated by a gap if the memory cell is at the first state. The extended silicide-containing portion extends from the second silicide-containing portion towards the first silicide-containing portion.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyun-Ying Lin, Chun-Yao Ko, Ting-Chen Hsu
  • Patent number: 8952541
    Abstract: A contact may be fabricated by a method including depositing a dielectric layer on a substrate having a transistor, etching a first opening in the dielectric layer that extends to a source region, forming an insulator on the source region, forming a contact metal on the insulator, the insulator separating the contact metal from the source region, and filling substantially all of the first opening, wherein the contact metal remains separated from the source region after the first opening is filled.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Gilbert Dewey, Matthew V. Metz, Jack Kavalieros, Robert S. Chau
  • Patent number: 8946071
    Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 3, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Jun Luo, Chao Zhao, Huicai Zhong, Junfeng Li, Dapeng Chen
  • Publication number: 20150024593
    Abstract: A semiconductor device production method includes forming a transition metal film, irradiating a surface of the transition metal film with a mono-silane gas to form a silicon-containing transition metal film, and oxidizing the silicon-containing transition metal film by an oxygen plasma treatment, thereby forming a transition metal silicate film.
    Type: Application
    Filed: August 1, 2014
    Publication date: January 22, 2015
    Inventors: Ippei Kume, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 8927366
    Abstract: A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hae Lee, Ki-hyun Hwang, Jin-gyun Kim
  • Patent number: 8927422
    Abstract: A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide, a width of the silicide and the contact trench are substantially equal; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° C. in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Nathaniel Berliner, Christian Lavoie, Kam-Leung Lee, Ahmet Serkan Ozcan
  • Patent number: 8912059
    Abstract: Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD overlying the substrate to expose the substrate; forming a silicide layer over the substrate; forming a conductor over the silicide layer and the at least one gate structure; forming an opening in the conductor to expose a portion of a gate region of the at least one gate structure; and forming a dielectric in the opening in the conductor.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, David V. Horak, Edward J. Nowak
  • Patent number: 8912096
    Abstract: Methods for precleaning native oxides or other contaminants from a surface of a substrate prior to forming a metal silicide layer on the substrate. In one embodiment, a method for removing native oxides from a substrate includes transferring a substrate having an oxide layer disposed thereon into a processing chamber, performing a pretreatment process on the substrate by supplying a pretreatment gas mixture into the processing chamber, performing an oxide removal process on the substrate by supplying a cleaning gas mixture into the processing chamber, wherein the cleaning gas mixture includes at least an ammonium gas and a nitrogen trifluoride, and performing a post treatment process on the cleaned substrate by supplying a post treatment gas mixture into the processing chamber.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: December 16, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Bo Zheng, Arvind Sundarrajan, Manish Hamkar
  • Patent number: 8901740
    Abstract: A contact may be fabricated by a method including depositing a dielectric layer on a substrate having a transistor, etching a first opening in the dielectric layer that extends to a source region, forming an insulator on the source region, forming a contact metal on the insulator, the insulator separating the contact metal from the source region, and filling substantially all of the first opening, wherein the contact metal remains separated from the source region after the first opening is filled.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Gilbert Dewey, Matthew V. Metz, Jack Kavalieros, Robert S. Chau
  • Patent number: 8895426
    Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jeff J. Xu
  • Publication number: 20140342556
    Abstract: A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region.
    Type: Application
    Filed: May 20, 2013
    Publication date: November 20, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Mohamed Salama, Tuhin Guha Neogi, Scott Beasor
  • Patent number: 8889552
    Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangline Park, Boun Yoon, Jeongnam Han, Kee-Sang Kwon, Byung-Kwon Cho, Wongsang Choi
  • Patent number: 8890106
    Abstract: A hybrid circuit comprises a nitride-based transistor portion and a memristor portion. The transistor includes a source and a drain and a gate for controlling conductance of a channel region between the source and the drain. The memristor includes a first electrode and a second electrode separated by an active switching region. The source or drain of the transistor forms one of the electrodes of the memristor.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: November 18, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Gilberto Medeiros Ribeiro, Byung-Joon Choi, Stanley Williams
  • Patent number: 8859431
    Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: October 14, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Anh Duong, John Foster, Olov Karlsson, James Mavrinac, Usha Raghuram
  • Patent number: 8853079
    Abstract: A method of forming a device includes forming a silicon-containing line continuously extending between a first node and a second node. A first silicide-containing portion and a second silicide-containing portion are formed over the silicon-containing line. The first silicide-containing portion is separated from the second silicide-containing portion by a predetermined distance, and the predetermined distance is substantially equal to or less than a length of the silicon-containing line.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyun-Ying Lin, Chun-Yao Ko, Ting-Chen Hsu
  • Patent number: 8841190
    Abstract: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first space
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: September 23, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Changliang Qin, Huaxiang Yin
  • Patent number: 8835318
    Abstract: Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 16, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Clemens Fitz, Jochen Poth, Kristin Schupke
  • Patent number: 8835316
    Abstract: The disclosure provides a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. The transistor comprises: an active area, a gate stack, a primary spacer, and source/drain regions, wherein the active area is on a semiconductor substrate; the gate stack, the primary spacer, and the source/drain regions are on the active area; the primary spacer surrounds the gate stack; the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer. Wherein the transistor further comprises: a silicide spacer, wherein the silicide spacer is located at opposite sides of the primary spacer, and a dielectric material is filled between the two ends of the silicide spacer in the width direction of the gate stack, so as to isolate the source/drain regions from each other.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: September 16, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Jun Luo, Huilong Zhu, Zhijiong Luo
  • Patent number: 8828868
    Abstract: A method for forming a hard mask in semiconductor device fabrication comprises: forming first and second patterned material layers on a third material layer, the second patterned material layer only covering the top of predetermined regions of the first patterned material layer; changing a property of exposed top and side portions of the first patterned material layer using the second patterned material layer as a mask, forming property-changed roofs at the exposed top portions of the first patterned material layer and forming property-changed sidewalls with a predetermined width at the exposed side portions of the first patterned material layer; removing the second patterned material layer and portions of the first patterned material layer with exposed tops and an unchanged property located between the property-changed sidewalls, to form the hard mask.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Zhongshan Hong
  • Publication number: 20140242796
    Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.
    Type: Application
    Filed: November 13, 2013
    Publication date: August 28, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Koichi TOBA, Hiraku CHAKIHARA, Yoshiyuki KAWASHIMA, Kentaro SAITO, Takashi HASHIMOTO
  • Patent number: 8815736
    Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Peter Javorka, Stefan Flachowsky, Clemens Fitz
  • Patent number: 8809077
    Abstract: In a method of manufacturing of a semiconductor device according to an embodiment, an inspection transistor is subjected to silicidation and subsequently a characteristic of the inspection transistor is measured after the inspection transistor and a product transistor on a substrate are subjected to an annealing process. Thereafter, based on the measured characteristic, a characteristic adjustment annealing process to make a characteristic of the product transistor close to a desired characteristic is performed, and then the product transistor is subjected to silicidation.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Amane Oishi
  • Patent number: 8803243
    Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
  • Patent number: 8796143
    Abstract: A semiconductor device in which a metal silicide layer is formed by a salicide process is improved in reliability. By a salicide process according to a partial reaction method, metal silicide layers are formed over respective surfaces of gate electrodes, n+-type semiconductor regions, and p+-type semiconductor regions. In a first heat treatment when the metal silicide layers are formed, a heat-conduction type anneal apparatus is used for the heat treatment of a semiconductor wafer. In a second heat treatment, a microwave anneal apparatus is used for the heat treatment of the semiconductor wafer, thereby reducing the temperature of the second heat treatment and preventing abnormal growth of the metal silicide layers. Thus, a junction leakage current in the metal silicide layers is reduced.
    Type: Grant
    Filed: November 12, 2011
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tadashi Yamaguchi
  • Patent number: 8796131
    Abstract: An ion implantation system and method, providing cooling of dopant gas in the dopant gas feed line, to combat heating and decomposition of the dopant gas by arc chamber heat generation, e.g., using boron source materials such as B2F4 or other alternatives to BF3. Various arc chamber thermal management arrangements are described, as well as modification of plasma properties, specific flow arrangements, cleaning processes, power management, eqillibrium shifting, optimization of extraction optics, detection of deposits in flow passages, and source life optimization, to achieve efficient operation of the ion implantation system.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: August 5, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Edward E. Jones, Sharad N. Yedave, Ying Tang, Barry Lewis Chambers, Robert Kaim, Joseph D. Sweeney, Oleg Byl, Peng Zou
  • Publication number: 20140206190
    Abstract: Embodiments of the present invention include methods of forming a silicide layer on a semiconductor substrate. In an exemplary embodiment, a metal layer may first be deposited above a semiconductor substrate using a chemical vapor deposition process with a metal amidinate precursor and then the semiconductor substrate may be annealed, causing the semiconductor substrate to react with the metal layer forming a metal-rich silicide layer on the semiconductor substrate. Embodiments may also include forming a low-oxygen capping layer above the metal layer prior to annealing the semiconductor substrate to protect the metal layer from oxidation. The low-oxygen capping layer may, for example, be made of titanium nitride containing less than 20 parts per million of oxygen. Embodiments may further include forming a silicide layer using the above process in a contact hole above a source/drain region of a field-effect transistor, and forming a metal contact above the silicide layer.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: BAOZHEN LI, YUN Y. WANG, KEITH KWONG HON WONG, CHIH-CHAO YANG
  • Patent number: 8785310
    Abstract: A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: July 22, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Toshio Hasegawa, Kunihiro Tada, Hideaki Yamasaki, David L. O'Meara, Gerrit J. Leusink
  • Publication number: 20140191298
    Abstract: A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region. The gate structure is disposed on the semiconductor substrate within the gate region. The epitaxial layer is disposed on the semiconductor substrate within the source/drain region. The interlayer dielectric covers the semiconductor substrate, the gate structure and the epitaxial layer. The contact hole penetrates the interlayer dielectric to reach the epitaxial layer. The metal silicide layer is formed in the epitaxial layer and is located on the bottom of the contact hole. The fluorine-containing layer is disposed on or in the epitaxial layer and is around sides of the metal silicide layer.
    Type: Application
    Filed: January 10, 2013
    Publication date: July 10, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Wei Chen, Chien-Chung Huang, Kok Seen Lew
  • Publication number: 20140191295
    Abstract: A method of forming a semiconductor device comprising a dummy gate interconnect includes forming a dummy gate on a substrate, the dummy gate comprising a dummy gate metal layer located on the substrate, and a dummy gate polysilicon layer located on the dummy gate metal layer; forming an active gate on the substrate, the active gate comprising an active gate metal layer located on the substrate, and an active gate polysilicon layer located on the active gate metal layer; and etching the dummy gate polysilicon layer to remove at least a portion of the dummy gate polysilicon layer to form the dummy gate interconnect, wherein the active gate polysilicon layer is not etched during the etching of the dummy gate polysilicon layer.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian J. Greene, Yue Liang, Xiaojun Yu
  • Patent number: 8765586
    Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 1, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Clemens Fitz, Peter Baars, Markus Lenski
  • Patent number: 8759213
    Abstract: A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Francois Pagette, Anna W. Topol
  • Patent number: 8741773
    Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Asa Frye, Andrew Simon
  • Publication number: 20140134816
    Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.
    Type: Application
    Filed: January 16, 2014
    Publication date: May 15, 2014
    Applicant: Micron Technology, Inc.
    Inventors: David H. Wells, John Mark Meldrim, Rita J. Klein
  • Patent number: 8697573
    Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process, comprising using an aqua regia cleaning solution (comprising a mixture of nitric acid and hydrochloric acid) with microwave assisted heating. Low boiling temperature of hydrochloric acid prevents heating the aqua regia solution to a high temperature, impeding the effectiveness of post silicidation nickel and platinum residue removal. Therefore, embodiments of the invention provide a microwave assisted heating of the substrate in an aqua regia solution, selectively heating platinum residues without significantly increasing the temperature of the aqua regia solution, rendering platinum residues to be more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: April 15, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Anh Duong, Olov Karlsson